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Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)

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* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.

* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.

Optionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.

* Add r0p1 errata support to IAR port as well

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change macro name to configENABLE_ERRATA_837070_WORKAROUND

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Paul Bartell 2022-06-29 22:05:26 -07:00 • committed by GitHub
parent 8e89acfc98
commit 2dfdfc4ba4
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8 changed files with 122 additions and 24 deletions
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4
portable/GCC/ARM_CM7/r0p1/port.c
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@ -445,11 +445,11 @@ void xPortPendSVHandler( void )
" \n"
" stmdb sp!, {r0, r3} \n"
" mov r0, %0 \n"
" cpsid i \n"/* Errata workaround. */
" cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
" msr basepri, r0 \n"
" dsb \n"
" isb \n"
" cpsie i \n"/* Errata workaround. */
" cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
" bl vTaskSwitchContext \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"