len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-20 10:08:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)

Browse source 
* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.

* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.

Optionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.

* Add r0p1 errata support to IAR port as well

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change macro name to configENABLE_ERRATA_837070_WORKAROUND

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Paul Bartell 2022-06-29 22:05:26 -07:00 • committed by GitHub
parent 8e89acfc98
commit 2dfdfc4ba4
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
8 changed files with 122 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

31
portable/GCC/ARM_CM4_MPU/portmacro.h
View file

@ -71,6 +71,7 @@ typedef unsigned long UBaseType_t;
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@ -346,10 +347,16 @@ portFORCE_INLINE static void vPortRaiseBASEPRI( void )
__asm volatile
(
" mov %0, %1 \n"\
" msr basepri, %0 \n"\
" isb \n"\
" dsb \n"\
" mov %0, %1 \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
" cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
" msr basepri, %0 \n"
" isb \n"
" dsb \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
" cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
@ -362,11 +369,17 @@ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
__asm volatile
(
" mrs %0, basepri \n"\
" mov %1, %2 \n"\
" msr basepri, %1 \n"\
" isb \n"\
" dsb \n"\
" mrs %0, basepri \n"
" mov %1, %2 \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
" cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
" msr basepri, %1 \n"
" isb \n"
" dsb \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
" cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);