Prepare Fujitsu ports for release.

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h

@@ -0,0 +1,69 @@
+/*----------------------------------------------------------------------------
+*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name           : Board.h
+* Object              : AT91SAM7X Evaluation Board Features Definition File.
+*
+* Creation            : JG   20/Jun/2005
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include <AT91SAM7X256.h>
+#define __inline inline
+#include <lib_AT91SAM7X256.h>
+
+#define true	-1
+#define false	0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
+
+#define  FLASH_PAGE_NB		256
+#define  FLASH_PAGE_SIZE	128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+#define LED1            (1<<19)	// PB19
+#define LED2            (1<<20)	// PB20
+#define LED3            (1<<21)	// PB21
+#define LED4            (1<<22)	// PB22
+#define NB_LED			4
+
+#define LED_MASK        (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+
+#define SW1_MASK        (1<<21)	// PA21
+#define SW2_MASK        (1<<22)	// PA22
+#define SW3_MASK        (1<<23)	// PA23
+#define SW4_MASK        (1<<24)	// PA24
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 	(1<<21)	// PA21
+#define SW2 	(1<<22)	// PA22
+#define SW3 	(1<<23)	// PA23
+#define SW4 	(1<<24)	// PA24
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
+#define MCK             47923200   // MCK (PLLRC div by 2)
+#define MCKKHz          (MCK/1000) //
+
+#endif /* Board_h */

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s

@@ -0,0 +1,302 @@
+;* ----------------------------------------------------------------------------
+;*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+;* ----------------------------------------------------------------------------
+;* Copyright (c) 2006, Atmel Corporation
+;
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* - Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the disclaimer below.
+;*
+;* - Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the disclaimer below in the documentation and/or
+;* other materials provided with the distribution.
+;*
+;* Atmel's name may not be used to endorse or promote products derived from
+;* this software without specific prior written permission.
+;*
+;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* ----------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+; Include your AT91 Library files
+;------------------------------------------------------------------------------
+#include "AT91SAM7X256_inc.h"
+;------------------------------------------------------------------------------
+
+#define TOP_OF_MEMORY    (AT91C_ISRAM + AT91C_ISRAM_SIZE)
+#define IRQ_STACK_SIZE   200
+     ; 3 words to be saved per interrupt priority level
+
+; Mode, correspords to bits 0-5 in CPSR
+MODE_BITS DEFINE  0x1F    ; Bit mask for mode bits in CPSR
+USR_MODE  DEFINE  0x10    ; User mode
+FIQ_MODE  DEFINE  0x11    ; Fast Interrupt Request mode
+IRQ_MODE  DEFINE  0x12    ; Interrupt Request mode
+SVC_MODE  DEFINE  0x13    ; Supervisor mode
+ABT_MODE  DEFINE  0x17    ; Abort mode
+UND_MODE  DEFINE  0x1B    ; Undefined Instruction mode
+SYS_MODE  DEFINE  0x1F    ; System mode
+
+I_BIT     DEFINE  0x80
+F_BIT     DEFINE  0x40
+
+;------------------------------------------------------------------------------
+; ?RESET
+; Reset Vector.
+; Normally, segment INTVEC is linked at address 0.
+; For debugging purposes, INTVEC may be placed at other addresses.
+; A debugger that honors the entry point will start the
+; program in a normal way even if INTVEC is not at address 0.
+;------------------------------------------------------------------------------
+        SECTION .intvec:CODE:NOROOT(2)
+        PUBLIC  __vector
+        PUBLIC  __iar_program_start
+		EXTERN	vPortYieldProcessor
+
+		ARM
+__vector:
+        ldr  pc,[pc,#+24]             ;; Reset
+__und_handler:
+        ldr  pc,[pc,#+24]             ;; Undefined instructions
+__swi_handler:
+        ldr  pc,[pc,#+24]             ;; Software interrupt (SWI/SVC)
+__prefetch_handler:
+        ldr  pc,[pc,#+24]             ;; Prefetch abort
+__data_handler:
+        ldr  pc,[pc,#+24]             ;; Data abort
+        DC32  0xFFFFFFFF              ;; RESERVED
+__irq_handler:
+        LDR			PC, [PC, #-0xF20]
+__fiq_handler:
+        ldr  pc,[pc,#+24]             ;; FIQ
+
+        DC32  __iar_program_start
+        DC32  __und_handler
+        DC32  vPortYieldProcessor
+        DC32  __prefetch_handler
+        DC32  __data_handler
+        B .
+        DC32  IRQ_Handler_Entry
+        DC32  FIQ_Handler_Entry
+
+;------------------------------------------------------------------------------
+;- Manage exception: The exception must be ensure in ARM mode
+;------------------------------------------------------------------------------
+        SECTION text:CODE:NOROOT(2)
+        ARM
+;------------------------------------------------------------------------------
+;- Function             : FIQ_Handler_Entry
+;- Treatments           : FIQ Controller Interrupt Handler.
+;-                        R8 is initialize in Cstartup
+;- Called Functions     : None only by FIQ
+;------------------------------------------------------------------------------
+FIQ_Handler_Entry:
+
+;- Switch in SVC/User Mode to allow User Stack access for C code
+; because the FIQ is not yet acknowledged
+
+;- Save and r0 in FIQ_Register
+        mov         r9,r0
+        ldr         r0 , [r8, #AIC_FVR]
+        msr         CPSR_c,#I_BIT | F_BIT | SVC_MODE
+;- Save scratch/used registers and LR in User Stack
+        stmfd       sp!, { r1-r3, r12, lr}
+
+;- Branch to the routine pointed by the AIC_FVR
+        mov         r14, pc
+        bx          r0
+
+;- Restore scratch/used registers and LR from User Stack
+        ldmia       sp!, { r1-r3, r12, lr}
+
+;- Leave Interrupts disabled and switch back in FIQ mode
+        msr         CPSR_c, #I_BIT | F_BIT | FIQ_MODE
+
+;- Restore the R0 ARM_MODE_SVC register
+        mov         r0,r9
+
+;- Restore the Program Counter using the LR_fiq directly in the PC
+        subs        pc,lr,#4
+;------------------------------------------------------------------------------
+;- Function             : IRQ_Handler_Entry
+;- Treatments           : IRQ Controller Interrupt Handler.
+;- Called Functions     : AIC_IVR[interrupt]
+;------------------------------------------------------------------------------
+IRQ_Handler_Entry:
+;-------------------------
+;- Manage Exception Entry
+;-------------------------
+;- Adjust and save LR_irq in IRQ stack
+    sub         lr, lr, #4
+    stmfd       sp!, {lr}
+
+;- Save r0 and SPSR (need to be saved for nested interrupt)
+    mrs         r14, SPSR
+    stmfd       sp!, {r0,r14}
+
+;- Write in the IVR to support Protect Mode
+;- No effect in Normal Mode
+;- De-assert the NIRQ and clear the source in Protect Mode
+    ldr         r14, =AT91C_BASE_AIC
+    ldr         r0 , [r14, #AIC_IVR]
+    str         r14, [r14, #AIC_IVR]
+
+;- Enable Interrupt and Switch in Supervisor Mode
+    msr         CPSR_c, #SVC_MODE
+
+;- Save scratch/used registers and LR in User Stack
+    stmfd       sp!, { r1-r3, r12, r14}
+
+;----------------------------------------------
+;- Branch to the routine pointed by the AIC_IVR
+;----------------------------------------------
+    mov         r14, pc
+    bx          r0
+
+;----------------------------------------------
+;- Manage Exception Exit
+;----------------------------------------------
+;- Restore scratch/used registers and LR from User Stack
+    ldmia       sp!, { r1-r3, r12, r14}
+
+;- Disable Interrupt and switch back in IRQ mode
+    msr         CPSR_c, #I_BIT | IRQ_MODE
+
+;- Mark the End of Interrupt on the AIC
+    ldr         r14, =AT91C_BASE_AIC
+    str         r14, [r14, #AIC_EOICR]
+
+;- Restore SPSR_irq and r0 from IRQ stack
+    ldmia       sp!, {r0,r14}
+    msr         SPSR_cxsf, r14
+
+;- Restore adjusted  LR_irq from IRQ stack directly in the PC
+    ldmia       sp!, {pc}^
+
+;------------------------------------------------------------------------------
+;- Exception Vectors
+;------------------------------------------------------------------------------
+    PUBLIC    AT91F_Default_FIQ_handler
+    PUBLIC    AT91F_Default_IRQ_handler
+    PUBLIC    AT91F_Spurious_handler
+
+    ARM      ; Always ARM mode after exeption
+
+AT91F_Default_FIQ_handler
+    b         AT91F_Default_FIQ_handler
+
+AT91F_Default_IRQ_handler
+    b         AT91F_Default_IRQ_handler
+
+AT91F_Spurious_handler
+    b         AT91F_Spurious_handler
+
+
+;------------------------------------------------------------------------------
+; ?INIT
+; Program entry.
+;------------------------------------------------------------------------------
+
+    SECTION FIQ_STACK:DATA:NOROOT(3)
+    SECTION IRQ_STACK:DATA:NOROOT(3)
+    SECTION SVC_STACK:DATA:NOROOT(3)
+    SECTION ABT_STACK:DATA:NOROOT(3)
+    SECTION UND_STACK:DATA:NOROOT(3)
+    SECTION CSTACK:DATA:NOROOT(3)
+    SECTION text:CODE:NOROOT(2)
+    REQUIRE __vector
+    EXTERN  ?main
+    PUBLIC  __iar_program_start
+    EXTERN  AT91F_LowLevelInit
+
+
+__iar_program_start:
+
+;------------------------------------------------------------------------------
+;- Low level Init is performed in a C function: AT91F_LowLevelInit
+;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
+;------------------------------------------------------------------------------
+
+;- Retrieve end of RAM address
+
+                ldr     r13,=TOP_OF_MEMORY          ;- Temporary stack in internal RAM for Low Level Init execution
+                ldr     r0,=AT91F_LowLevelInit
+                mov     lr, pc
+                bx      r0                          ;- Branch on C function (with interworking)
+
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+
+                mrs     r0,cpsr                             ; Original PSR value
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#SVC_MODE                     ; Set SVC mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(SVC_STACK)                  ; End of SVC_STACK
+
+				bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#UND_MODE                     ; Set UND mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(UND_STACK)                  ; End of UND_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#ABT_MODE                     ; Set ABT mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(ABT_STACK)                  ; End of ABT_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#FIQ_MODE                     ; Set FIQ mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(FIQ_STACK)                  ; End of FIQ_STACK
+                ;- Init the FIQ register
+                ldr     r8, =AT91C_BASE_AIC
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(IRQ_STACK)                  ; End of IRQ_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(CSTACK)                     ; End of CSTACK
+
+
+#ifdef __ARMVFP__
+; Enable the VFP coprocessor.
+                mov     r0, #0x40000000                 ; Set EN bit in VFP
+                fmxr    fpexc, r0                       ; FPEXC, clear others.
+
+; Disable underflow exceptions by setting flush to zero mode.
+; For full IEEE 754 underflow compliance this code should be removed
+; and the appropriate exception handler installed.
+                mov     r0, #0x01000000		        ; Set FZ bit in VFP
+                fmxr    fpscr, r0                       ; FPSCR, clear others.
+#endif
+
+; Add more initialization here
+		        msr   CPSR_c,#I_BIT | F_BIT | SVC_MODE
+
+
+; Continue to ?main for more IAR specific system startup
+
+                ldr     r0,=?main
+                bx      r0
+
+    END         ;- Terminates the assembly of the last module in a file

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c

@@ -0,0 +1,97 @@
+//-----------------------------------------------------------------------------
+//         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//-----------------------------------------------------------------------------
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//-----------------------------------------------------------------------------
+// File Name           : Cstartup_SAM7.c
+// Object              : Low level initialisations written in C for Tools
+//                       For AT91SAM7X256 with 2 flash plane
+// Creation            : JPP  14-Sep-2006
+//-----------------------------------------------------------------------------
+
+
+#include "Board.h"
+//  The following functions must be write in ARM mode this function called
+// directly by exception vector
+extern void AT91F_Spurious_handler(void);
+extern void AT91F_Default_IRQ_handler(void);
+extern void AT91F_Default_FIQ_handler(void);
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit(void) @ "ICODE"
+{
+    unsigned char i;
+    ///////////////////////////////////////////////////////////////////////////
+    // EFC Init
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 1. Enable Main Oscillator
+    // Main Oscillator startup time is board specific:
+    // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
+    // (0x40 for AT91C_CKGR_OSCOUNT field)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
+    // Wait Main Oscillator stabilization
+    while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 2.
+    // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
+    // PLL Startup time depends on PLL RC filter: worst case is choosen
+    // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus
+    // Specification (+/- 0.25% for full speed)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1           |
+    						   (16 << 8)                     |
+                               (AT91C_CKGR_MUL & (72 << 16)) |
+                               (AT91C_CKGR_DIV & 14);
+    // Wait for PLL stabilization
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
+    // Wait until the master clock is established for the case we already
+    // turn on the PLL
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 3.
+    // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz
+    // The PMC_MCKR register must not be programmed in a single write operation
+    // (see. Product Errata Sheet)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+    // Wait until the master clock is established
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+
+    AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
+    // Wait until the master clock is established
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+
+    ///////////////////////////////////////////////////////////////////////////
+    //  Disable Watchdog (write once register)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+    ///////////////////////////////////////////////////////////////////////////
+    //  Init AIC: assign corresponding handler for each interrupt source
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
+    for (i = 1; i < 31; i++) {
+        AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
+    }
+    AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
+}

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h

@@ -0,0 +1,195 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Emac.h
+//* Object              : Emac header file
+//* Creation            : Hi   11/18/2002
+//*
+//*----------------------------------------------------------------------------
+#ifndef AT91C_EMAC_H
+#define AT91C_EMAC_H
+
+
+//* Allows to display all IP header in the main.c
+//* If not defined, only ICMP packets are displayed
+#define AT91C_DISPLAY_ALL_IPHEADER		0
+
+#define NB_RX_BUFFERS			25			//* Number of receive buffers
+#define ETH_RX_BUFFER_SIZE		128         //*
+
+#define NB_TX_BUFFERS			2		//* Number of Transmit buffers
+#define ETH_TX_BUFFER_SIZE		UIP_BUFSIZE       //*
+
+#define AT91C_NO_IPPACKET		0
+#define AT91C_IPPACKET	        1
+
+#define ARP_REQUEST				0x0001
+#define ARP_REPLY				0x0002
+#define PROT_ARP				0x0806
+#define PROT_IP					0x0800
+#define PROT_ICMP				0x01
+#define ICMP_ECHO_REQUEST		0x08
+#define ICMP_ECHO_REPLY			0x00
+
+#define AT91C_EMAC_CLKEN 0x2
+#define SWAP16(x)	(((x & 0xff) << 8) | (x >> 8))
+
+#if 0
+//* Transfer descriptor structure
+typedef struct _AT91S_TdDescriptor {
+	unsigned int addr;
+	unsigned int status;
+}AT91S_TdDescriptor, *AT91PS_TdDescriptor;
+#endif
+
+//* Receive Transfer descriptor structure
+typedef struct  _AT91S_RxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:1;
+			unsigned int Rxbuf_off:2;
+			unsigned int StartOfFrame:1;
+			unsigned int EndOfFrame:1;
+			unsigned int Cfi:1;
+			unsigned int VlanPriority:3;
+			unsigned int PriorityTag:1;
+			unsigned int VlanTag:1;
+			unsigned int TypeID:1;
+			unsigned int Sa4Match:1;
+			unsigned int Sa3Match:1;
+			unsigned int Sa2Match:1;
+			unsigned int Sa1Match:1;
+			unsigned int Res1:1;
+			unsigned int ExternalAdd:1;
+			unsigned int UniCast:1;
+			unsigned int MultiCast:1;
+			unsigned int BroadCast:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
+
+
+//* Transmit Transfer descriptor structure
+typedef struct _AT91S_TxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:4;
+			unsigned int LastBuff:1;
+			unsigned int NoCrc:1;
+			unsigned int Res1:10;
+			unsigned int BufExhausted:1;
+			unsigned int TransmitUnderrun:1;
+			unsigned int TransmitError:1;
+			unsigned int Wrap:1;
+			unsigned int BuffUsed:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
+
+#define AT91C_OWNERSHIP_BIT		0x00000001
+
+/* Receive status defintion */
+#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
+#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
+#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
+#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
+#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
+#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
+#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
+#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
+#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
+#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
+#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
+#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
+#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
+#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
+#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
+#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
+#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
+
+/* Transmit Status definition */
+#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
+#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
+#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
+#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
+#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
+#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
+#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
+
+#define ARP_ETHER	 		1		/* Ethernet  hardware address	*/
+#define ARPOP_REQUEST    	1		/* Request  to resolve  address	*/
+#define ARPOP_REPLY	    	2		/* Response to previous request	*/
+#define RARPOP_REQUEST   	3		/* Request  to resolve  address	*/
+#define RARPOP_REPLY	    4		/* Response to previous request */
+
+
+typedef struct _AT91S_EthHdr
+{
+	unsigned char		et_dest[6];	/* Destination node		*/
+	unsigned char		et_src[6];	/* Source node			*/
+	unsigned short		et_protlen;	/* Protocol or length		*/
+} AT91S_EthHdr, *AT91PS_EthHdr;
+
+typedef struct _AT91S_ArpHdr
+{
+	unsigned short		ar_hrd;		/* Format of hardware address	*/
+	unsigned short		ar_pro;		/* Format of protocol address	*/
+	unsigned char		ar_hln;		/* Length of hardware address	*/
+	unsigned char		ar_pln;		/* Length of protocol address	*/
+	unsigned short		ar_op;		/* Operation			*/
+	unsigned char		ar_sha[6];	/* Sender hardware address	*/
+	unsigned char		ar_spa[4];	/* Sender protocol address	*/
+	unsigned char		ar_tha[6];	/* Target hardware address	*/
+	unsigned char		ar_tpa[4];	/* Target protocol address	*/
+} AT91S_ArpHdr, *AT91PS_ArpHdr;
+
+//* IP Header structure
+typedef struct _AT91S_IPheader {
+	unsigned char	ip_hl_v;	/* header length and version	*/
+	unsigned char	ip_tos;		/* type of service		*/
+	unsigned short	ip_len;		/* total length			*/
+	unsigned short	ip_id;		/* identification		*/
+	unsigned short	ip_off;		/* fragment offset field	*/
+	unsigned char	ip_ttl;		/* time to live			*/
+	unsigned char	ip_p;		/* protocol			*/
+	unsigned short	ip_sum;		/* checksum			*/
+	unsigned char	ip_src[4];	/* Source IP address		*/
+	unsigned char	ip_dst[4];	/* Destination IP address	*/
+	unsigned short	udp_src;	/* UDP source port		*/
+	unsigned short	udp_dst;	/* UDP destination port		*/
+	unsigned short	udp_len;	/* Length of UDP packet		*/
+	unsigned short	udp_xsum;	/* Checksum			*/
+} AT91S_IPheader, *AT91PS_IPheader;
+
+//* ICMP echo header structure
+typedef struct _AT91S_IcmpEchoHdr {
+    unsigned char   type;       /* type of message */
+    unsigned char   code;       /* type subcode */
+    unsigned short  cksum;      /* ones complement cksum of struct */
+    unsigned short  id;         /* identifier */
+    unsigned short  seq;        /* sequence number */
+}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;
+
+
+typedef struct _AT91S_EthPack
+{
+	AT91S_EthHdr	EthHdr;
+	AT91S_ArpHdr	ArpHdr;
+} AT91S_EthPack, *AT91PS_EthPack;
+
+
+#endif //* AT91C_EMAC_H

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c

@@ -0,0 +1,95 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : dbgu.c
+//* Object              : DBGU routines written in C
+//* Creation            : JG   16/Aug/2004
+//*----------------------------------------------------------------------------
+
+// Include Standard files
+#include "Board.h"
+
+//*--------------------------1--------------------------------------------------
+//* \fn    AT91F_DBGU_Printk
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
+//*----------------------------------------------------------------------------
+void AT91F_DBGU_Printk(	char *buffer)
+{
+    AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+    unsigned int temp;
+    
+    while(*buffer != '\0') 
+    {
+        temp=0;
+        
+	while (temp==0)
+	{
+	  if ( (pDbgu->DBGU_CSR & 0x0200) == 0)
+	    temp=0;
+	  else
+	    temp=1;
+	}
+
+        pDbgu->DBGU_THR = *buffer;
+        buffer++;
+    }
+}
+
+
+void Init_DBGU_CLK(void)
+{
+  AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+void Init_DBGU_BGR(unsigned short baud)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_BRGR = (unsigned short)baud;
+}
+
+void DBGU_TX_Enable(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_CR = 0x00000040;
+}
+
+void DBGU_RX_Enable(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_CR = 0x00000010;
+}
+
+void DBGU_RX_TX_RST_DIS(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  pDbgu->DBGU_CR = 0x000000AC;
+}
+
+void DBGU_Parity_Cfg(unsigned int par)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_MR = par << 9;
+}
+
+
+void Init_DBGU(void)
+{ 
+  AT91F_DBGU_CfgPIO();
+  DBGU_RX_TX_RST_DIS();
+  Init_DBGU_BGR(26);  //26 <=> 115kBd
+  DBGU_Parity_Cfg(4);
+  DBGU_TX_Enable();   
+  DBGU_RX_Enable();
+}
+
+

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h

@@ -0,0 +1,22 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : dbgu.c
+//* Object              : DBGU routines written in C
+//* Creation            : JG   16/Aug/2004
+//*----------------------------------------------------------------------------
+
+// Include Standard files
+extern void APPLI_DBGU(void);   
+extern void D1_TEST_REGISTER_RESET_VALUES(void);
+extern void D2_CHIP_ID_VALUES(void);
+
+
+
+

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c

@@ -0,0 +1,31 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : init.c
+//* Object              : Low level initialisations written in C
+//* Creation            : ODi   06/26/2002
+//*
+//*----------------------------------------------------------------------------
+#include "board.h"
+//#include "init.h"
+#include <string.h>
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_Printk
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
+//*----------------------------------------------------------------------------
+void AT91F_DBGU_Printk(
+	char *buffer) // \arg pointer to a string ending by \0
+{
+	while(*buffer != '\0') {
+		while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
+		AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
+	}
+}
+

20080217/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h

@@ -0,0 +1,105 @@
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x007f  /* Unused...                   */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x07c0  /* Unused...                   */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_RESV                0x1c00  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+#define SPEED_10				10
+#define SPEED_100				100
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF				0x00
+#define DUPLEX_FULL				0x01
+
+/* PHY ID */
+#define MII_DM9161_ID     0x0181b8a0
+#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
+
+#define AT91C_PHY_ADDR	31