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Set ARM byte alignment to 8.

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This commit is contained in:
Richard Barry 2009-09-29 19:58:05 +00:00
parent 98ed4f2a20
commit 2d958d3d2c
8 changed files with 35 additions and 60 deletions
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2
Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
View file

@ -106,7 +106,7 @@ extern "C" {
/* Hardware specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portBYTE_ALIGNMENT 8
#define portYIELD() asm volatile ( "SWI" )
#define portNOP() asm volatile ( "NOP" )

2
Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
View file

@ -106,7 +106,7 @@ extern "C" {
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portBYTE_ALIGNMENT 8
#define portNOP() asm volatile ( "NOP" );
/*-----------------------------------------------------------*/

3
Source/portable/GCC/ARM7_LPC2000/port.c
View file

@ -164,12 +164,11 @@ portSTACK_TYPE *pxOriginalTOS;
system mode, with interrupts enabled. */
*pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
#ifdef THUMB_INTERWORK
if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00 )
{
/* We want the task to start in thumb mode. */
*pxTopOfStack |= portTHUMB_MODE_BIT;
}
#endif
pxTopOfStack--;

17
Source/portable/GCC/ARM7_LPC2000/portISR.c
View file

@ -73,7 +73,6 @@
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to handle interrupts. */
#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
@ -116,13 +115,13 @@ void vPortYieldProcessor( void )
/* Within an IRQ ISR the link register has an offset from the true return
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
asm volatile ( "ADD LR, LR, #4" );
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
portSAVE_CONTEXT();
/* Find the highest priority task that is ready to run. */
vTaskSwitchContext();
__asm volatile ( "bl vTaskSwitchContext" );
/* Restore the context of the new task. */
portRESTORE_CONTEXT();
@ -140,10 +139,10 @@ void vTickISR( void )
/* Increment the RTOS tick count, then look for the highest priority
task that is ready to run. */
vTaskIncrementTick();
__asm volatile( "bl vTaskIncrementTick" );
#if configUSE_PREEMPTION == 1
vTaskSwitchContext();
__asm volatile( "bl vTaskSwitchContext" );
#endif
/* Ready for the next interrupt. */
@ -168,7 +167,7 @@ void vTickISR( void )
void vPortDisableInterruptsFromThumb( void )
{
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
@ -179,7 +178,7 @@ void vTickISR( void )
void vPortEnableInterruptsFromThumb( void )
{
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
@ -197,7 +196,7 @@ in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
@ -222,7 +221,7 @@ void vPortExitCritical( void )
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */

39
Source/portable/GCC/ARM7_LPC2000/portmacro.h
View file

@ -45,29 +45,6 @@
licensing and training services.
*/
/*
Changes from V3.2.3
+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
Changes from V3.2.4
+ Removed the use of the %0 parameter within the assembler macros and
replaced them with hard coded registers. This will ensure the
assembler does not select the link register as the temp register as
was occasionally happening previously.
+ The assembler statements are now included in a single asm block rather
than each line having its own asm block.
Changes from V4.5.0
+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
and replaced them with portYIELD_FROM_ISR() macro. Application code
should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
macros as per the V4.5.1 demo code.
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
@ -106,8 +83,8 @@ extern "C" {
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portNOP() asm volatile ( "NOP" );
#define portBYTE_ALIGNMENT 8
#define portNOP() __asm volatile ( "NOP" );
/*-----------------------------------------------------------*/
@ -126,7 +103,7 @@ extern volatile void * volatile pxCurrentTCB; \
extern volatile unsigned portLONG ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
asm volatile ( \
__asm volatile ( \
"LDR R0, =pxCurrentTCB \n\t" \
"LDR R0, [R0] \n\t" \
"LDR LR, [R0] \n\t" \
@ -163,7 +140,7 @@ extern volatile void * volatile pxCurrentTCB; \
extern volatile unsigned portLONG ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" \
\
/* Set R0 to point to the task stack pointer. */ \
@ -203,9 +180,9 @@ extern volatile unsigned portLONG ulCriticalNesting; \
( void ) pxCurrentTCB; \
}
extern void vTaskSwitchContext( void );
#define portYIELD_FROM_ISR() vTaskSwitchContext()
#define portYIELD() asm volatile ( "SWI" )
#define portYIELD() __asm volatile ( "SWI" )
/*-----------------------------------------------------------*/
@ -229,7 +206,7 @@ extern volatile unsigned portLONG ulCriticalNesting; \
#else
#define portDISABLE_INTERRUPTS() \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
@ -237,7 +214,7 @@ extern volatile unsigned portLONG ulCriticalNesting; \
"LDMIA SP!, {R0} " ) /* Pop R0. */
#define portENABLE_INTERRUPTS() \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \

16
Source/portable/GCC/ARM7_LPC23xx/portISR.c
View file

@ -97,13 +97,13 @@ void vPortYieldProcessor( void )
/* Within an IRQ ISR the link register has an offset from the true return
address, but an SWI ISR does not. Add the offset manually so the same
ISR return code can be used in both cases. */
asm volatile ( "ADD LR, LR, #4" );
__asm volatile ( "ADD LR, LR, #4" );
/* Perform the context switch. First save the context of the current task. */
portSAVE_CONTEXT();
/* Find the highest priority task that is ready to run. */
vTaskSwitchContext();
__asm volatile( "bl vTaskSwitchContext" );
/* Restore the context of the new task. */
portRESTORE_CONTEXT();
@ -140,8 +140,8 @@ void vPortYieldProcessor( void )
/* Increment the RTOS tick count, then look for the highest priority
task that is ready to run. */
vTaskIncrementTick();
vTaskSwitchContext();
__asm volatile( "bl vTaskIncrementTick" );
__asm volatile( "bl vTaskSwitchContext" );
/* Ready for the next interrupt. */
T0IR = 2;
@ -167,7 +167,7 @@ void vPortYieldProcessor( void )
void vPortDisableInterruptsFromThumb( void )
{
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
@ -178,7 +178,7 @@ void vPortYieldProcessor( void )
void vPortEnableInterruptsFromThumb( void )
{
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
@ -196,7 +196,7 @@ in a variable, which is then saved as part of the stack context. */
void vPortEnterCritical( void )
{
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
@ -221,7 +221,7 @@ void vPortExitCritical( void )
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable interrupts as per portEXIT_CRITICAL(). */
asm volatile (
__asm volatile (
"STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */

14
Source/portable/GCC/ARM7_LPC23xx/portmacro.h
View file

@ -106,8 +106,8 @@ extern "C" {
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portNOP() asm volatile ( "NOP" );
#define portBYTE_ALIGNMENT 8
#define portNOP() __asm volatile ( "NOP" );
/*-----------------------------------------------------------*/
@ -126,7 +126,7 @@ extern volatile void * volatile pxCurrentTCB; \
extern volatile unsigned portLONG ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
asm volatile ( \
__asm volatile ( \
"LDR R0, =pxCurrentTCB \n\t" \
"LDR R0, [R0] \n\t" \
"LDR LR, [R0] \n\t" \
@ -163,7 +163,7 @@ extern volatile void * volatile pxCurrentTCB; \
extern volatile unsigned portLONG ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" \
\
/* Set R0 to point to the task stack pointer. */ \
@ -205,7 +205,7 @@ extern volatile unsigned portLONG ulCriticalNesting; \
#define portYIELD_FROM_ISR() vTaskSwitchContext()
#define portYIELD() asm volatile ( "SWI" )
#define portYIELD() __asm volatile ( "SWI" )
/*-----------------------------------------------------------*/
@ -229,7 +229,7 @@ extern volatile unsigned portLONG ulCriticalNesting; \
#else
#define portDISABLE_INTERRUPTS() \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
@ -237,7 +237,7 @@ extern volatile unsigned portLONG ulCriticalNesting; \
"LDMIA SP!, {R0} " ) /* Pop R0. */
#define portENABLE_INTERRUPTS() \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \

2
Source/portable/GCC/ARM_CM3/portmacro.h
View file

@ -84,7 +84,7 @@ extern "C" {
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/