diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.HardwareDebuglinker b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.HardwareDebuglinker
new file mode 100644
index 000000000..a232c8ba1
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.HardwareDebuglinker
@@ -0,0 +1,130 @@
+
+
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diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.cproject b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.cproject
new file mode 100644
index 000000000..31136a9d5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.cproject
@@ -0,0 +1,202 @@
+
+
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diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.info b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.info
new file mode 100644
index 000000000..3946e66d7
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.info
@@ -0,0 +1,6 @@
+TOOL_CHAIN=KPIT GNURX-ELF Toolchain
+VERSION=v12.01
+TC_INSTALL=C:\devtools\Renesas\e2studio\GNURXV~1.01-\rx-elf\
+GCC_STRING=4.6-GNURX_v12.01
+VERISON_IDE=3.06.02.080
+E2STUDIO_VERSION=1.1.1.7
\ No newline at end of file
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.project b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.project
new file mode 100644
index 000000000..411200c3c
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.project
@@ -0,0 +1,83 @@
+
+
+ RTOSDemo_GCC
+
+
+
+
+
+ com.renesas.cdt.core.genmakebuilder
+
+
+ ?name?
+
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.autoBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.buildArguments
+
+
+
+ org.eclipse.cdt.make.core.buildCommand
+ make
+
+
+ org.eclipse.cdt.make.core.buildLocation
+ ${workspace_loc:/RTOSDemo_GCC/HardwareDebug}
+
+
+ org.eclipse.cdt.make.core.cleanBuildTarget
+ clean
+
+
+ org.eclipse.cdt.make.core.contents
+ org.eclipse.cdt.make.core.configurationIds
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ false
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.fullBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ true
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ com.renesas.cdt.core.kpitcnature
+ com.renesas.cdt.core.kpitccnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.settings/Project_Generation_Prefrences.prefs
new file mode 100644
index 000000000..83f742619
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/.settings/Project_Generation_Prefrences.prefs
@@ -0,0 +1,22 @@
+#Mon Mar 11 11:21:23 GMT 2013
+Library\ Generator\ Command=rx-elf-libgen
+com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}\\src";
+com.renesas.cdt.core.Compiler.option.includeFileDir.316833280="${TCINSTALL}\\rx-elf\\optlibinc";
+com.renesas.cdt.core.LibraryGenerator.option.ctype=true
+com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built
+com.renesas.cdt.core.LibraryGenerator.option.math=false
+com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized
+com.renesas.cdt.core.LibraryGenerator.option.stdio=false
+com.renesas.cdt.core.LibraryGenerator.option.stdlib=true
+com.renesas.cdt.core.LibraryGenerator.option.string=true
+com.renesas.cdt.core.Linker.option.userDefinedOptions=[Ljava.lang.String;@13ec853
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType=RX100
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType.2018307272=RX100
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian=Little-endian data
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.disableFPUInstructions=false
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX610=false
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.generateRXas100output=false
+com.renesas.cdt.rx.HardwareDebug.Compiler.option.make64bitDouble=false
+com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles=${ProjName};gcc;
+com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.770090581="${CONFIGDIR}";"${TCINSTALL}\\lib\\gcc\\rx-elf\\\\${GCC_VERSION}";
+eclipse.preferences.version=1
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/CreateProjectDirectoryStructure.bat b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/CreateProjectDirectoryStructure.bat
new file mode 100644
index 000000000..2fc474125
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/CreateProjectDirectoryStructure.bat
@@ -0,0 +1,52 @@
+REM This file should be executed from the command line prior to the first
+REM build. It will be necessary to refresh the Eclipse project once the
+REM .bat file has been executed (normally just press F5 to refresh).
+
+REM Copies all the required files from their location within the standard
+REM FreeRTOS directory structure to under the Eclipse project directory.
+REM This permits the Eclipse project to be used in 'managed' mode and without
+REM having to setup any linked resources.
+
+REM Standard paths
+SET FREERTOS_SOURCE=..\..\Source
+SET COMMON_SOURCE=..\Common\minimal
+SET COMMON_INCLUDE=..\Common\include
+
+REM Have the files already been copied?
+IF EXIST RTOSDemo\FreeRTOS_Source Goto END
+
+ REM Create the required directory structure.
+ MD RTOSDemo\FreeRTOS_Source
+ MD RTOSDemo\FreeRTOS_Source\include
+ MD RTOSDemo\FreeRTOS_Source\portable
+ MD RTOSDemo\FreeRTOS_Source\portable\MemMang
+ MD RTOSDemo\FreeRTOS_Source\portable\GCC
+ MD RTOSDemo\FreeRTOS_Source\portable\GCC\RX100
+ MD RTOSDemo\Common_Demo_Tasks
+ MD RTOSDemo\Common_Demo_Tasks\include
+
+ REM Copy the core kernel files into the project directory
+ copy %FREERTOS_SOURCE%\tasks.c RTOSDemo\FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\queue.c RTOSDemo\FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\list.c RTOSDemo\FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\timers.c RTOSDemo\FreeRTOS_Source
+
+ REM Copy the common header files into the project directory
+ copy %FREERTOS_SOURCE%\include\*.* RTOSDemo\FreeRTOS_Source\include
+
+ REM Copy the portable layer files into the project directory
+ copy %FREERTOS_SOURCE%\portable\GCC\RX100\*.* RTOSDemo\FreeRTOS_Source\portable\GCC\RX100
+
+ REM Copy the memory allocation files into the project directory
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c RTOSDemo\FreeRTOS_Source\portable\MemMang
+
+ REM Copy the files that define the common demo tasks.
+ copy %COMMON_SOURCE%\death.c RTOSDemo\Common_Demo_Tasks
+ copy %COMMON_SOURCE%\blocktim.c RTOSDemo\Common_Demo_Tasks
+ copy %COMMON_SOURCE%\GenQTest.c RTOSDemo\Common_Demo_Tasks
+ copy %COMMON_SOURCE%\recmutex.c RTOSDemo\Common_Demo_Tasks
+
+ REM Copy the common demo file headers.
+ copy %COMMON_INCLUDE%\*.h RTOSDemo\Common_Demo_Tasks\include
+
+: END
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h
new file mode 100644
index 000000000..acb109f9e
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/FreeRTOSConfig.h
@@ -0,0 +1,186 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+
+/*
+ * The following #error directive is to remind users that a batch file must be
+ * executed prior to this project being built. The batch file *cannot* be
+ * executed from within the IDE! Once it has been executed, re-open or refresh
+ * the Eclipse project and remove the #error line below.
+ */
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/* Hardware specifics. */
+#include "platform.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* DEMO SPECIFIC SETTING:
+ * Set configCREATE_LOW_POWER_DEMO to one to run the low power demo with tick
+ * suppression, or 0 to run the more comprehensive test and demo application.
+ * If configCREATE_LOW_POWER_DEMO is set to 1 then main() calls main_low_power().
+ * If configCREATE_LOW_POWER_DEMO is set to 0 then main() calls main_full().
+ */
+#define configCREATE_LOW_POWER_DEMO 1
+
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE configCREATE_LOW_POWER_DEMO
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( ICLK_HZ ) /* Set in mcu_info.h. */
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_HZ ) /* Set in muc_info.h. */
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 9 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions - only included when the demo is configured to
+build the full demo (as opposed to the low power demo). */
+#if configCREATE_LOW_POWER_DEMO == 1
+ #define configUSE_TIMERS 0
+#else
+ #define configUSE_TIMERS 1
+ #define configTIMER_TASK_PRIORITY ( 3 )
+ #define configTIMER_QUEUE_LENGTH 5
+ #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
+#endif /* configCREATE_LOW_POWER_DEMO */
+
+/* The interrupt priority used by the kernel itself for the tick interrupt and
+the pended interrupt. This would normally be the lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY 1
+
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.
+Interrupts that use a priority above this will not be effected by anything the
+kernel is doing but must not make any use of FreeRTOS functionality.
+interrupts that use a priority at or below configMAX_SYSCALL_INTERRUPT_PRIORITY
+can make use of FreeRTOS API function but *only* functions that end in
+"FromISR()". */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+
+extern void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled();
+
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros
+allow the application writer to add additional code before and after the MCU is
+placed into the low power state respectively. The implementations provided in
+this demo can be extended to save even more power - for example the analog
+input used by the low power demo could be switched off in the pre-sleep macro
+and back on again in the post sleep macro. */
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c
new file mode 100644
index 000000000..827da190d
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/ParTest.c
@@ -0,0 +1,200 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/*-----------------------------------------------------------
+ * Simple IO routines to control the LEDs.
+ *-----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo includes. */
+#include "partest.h"
+
+#define partestNUM_LEDS ( 4 )
+
+long lParTestGetLEDState( unsigned long ulLED );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+ /* Port pin configuration is done by the low level set up prior to this
+ function being called. */
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned long ulLED, signed long xValue )
+{
+ if( ulLED < partestNUM_LEDS )
+ {
+ if( xValue != 0 )
+ {
+ /* Turn the LED on. */
+ taskENTER_CRITICAL();
+ {
+ switch( ulLED )
+ {
+ case 0: LED0 = LED_ON;
+ break;
+ case 1: LED1 = LED_ON;
+ break;
+ case 2: LED2 = LED_ON;
+ break;
+ case 3: LED3 = LED_ON;
+ break;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ /* Turn the LED off. */
+ taskENTER_CRITICAL();
+ {
+ switch( ulLED )
+ {
+ case 0: LED0 = LED_OFF;
+ break;
+ case 1: LED1 = LED_OFF;
+ break;
+ case 2: LED2 = LED_OFF;
+ break;
+ case 3: LED3 = LED_OFF;
+ break;
+ }
+
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned long ulLED )
+{
+ if( ulLED < partestNUM_LEDS )
+ {
+ taskENTER_CRITICAL();
+ {
+ if( lParTestGetLEDState( ulLED ) != 0x00 )
+ {
+ vParTestSetLED( ulLED, 0 );
+ }
+ else
+ {
+ vParTestSetLED( ulLED, 1 );
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+/*-----------------------------------------------------------*/
+
+long lParTestGetLEDState( unsigned long ulLED )
+{
+long lReturn = pdTRUE;
+
+ if( ulLED < partestNUM_LEDS )
+ {
+ switch( ulLED )
+ {
+ case 0 : if( LED0 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 1 : if( LED1 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 2 : if( LED2 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 3 : if( LED3 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ }
+ }
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.c
new file mode 100644
index 000000000..4a87dbce8
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.c
@@ -0,0 +1,252 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lcd.c
+* Device(s) : RX
+* H/W Platform : RSKRX111
+* Description : Provides variable and function declarations for lcd.c file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Standard string manipulation & formatting functions */
+#include
+#include
+/* Defines standard variable types used in this function */
+#include
+/* Bring in board includes. */
+#include "platform.h"
+/* Following header file provides function prototypes for LCD controlling functions & macro defines */
+#include "lcd.h"
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+static void lcd_delay(volatile int32_t nsecs);
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value);
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value);
+
+/***********************************************************************************************************************
+* Function name : lcd_initialize
+* Description : Initializes the LCD display.
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_initialize(void)
+{
+ /* Set LCD data pins as outputs. */
+ PORT4.PDR.BYTE |= 0x0F;
+
+ /* Set LCD control pins as outputs. */
+ RS_PIN_DDR = 1;
+ E_PIN_DDR = 1;
+
+ /* Power Up Delay for the LCD Module */
+ lcd_delay(50000000);
+
+ /* Display initialises in 8 bit mode - so send one write (seen as 8 bit) to set to 4 bit mode. */
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+
+ /* Function Set */
+ lcd_nibble_write(CTRL_WR, 0x02);
+ lcd_delay(39000);
+ lcd_nibble_write(CTRL_WR, 0x02);
+ lcd_nibble_write(CTRL_WR, (LCD_DISPLAY_ON | LCD_TWO_LINE ));
+ lcd_delay(39000);
+
+ /* Display ON/OFF control */
+ lcd_write(CTRL_WR, LCD_CURSOR_OFF);
+ lcd_delay(39000);
+
+ /* Display Clear */
+ lcd_write(CTRL_WR, LCD_CLEAR);
+ lcd_delay(2000000);
+
+ /* Entry Mode Set */
+ lcd_write(CTRL_WR, 0x06);
+ lcd_delay(39000);
+
+ /* Home the cursor */
+ lcd_write(CTRL_WR, LCD_HOME_L1);
+ lcd_delay(5000000);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_clear
+* Description : Clears the LCD
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_clear(void)
+{
+ /* Display Clear */
+ lcd_write(CTRL_WR, LCD_CLEAR);
+ lcd_delay(2000000);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_display
+* Description : This function controls LCD writes to line 1 or 2 of the LCD.
+* You need to use the defines LCD_LINE1 and LCD_LINE2 in order to specify the starting position.
+* For example, to start at the 2nd position on line 1...
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : position -
+* Line number of display
+* string -
+* Pointer to null terminated string
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_display(uint8_t position, uint8_t const * string)
+{
+ /* Declare next position variable */
+ static uint8_t next_pos = 0xFF;
+
+ /* Set line position if needed. We don't want to if we don't need to because LCD control operations take longer
+ than LCD data operations. */
+ if (next_pos != position)
+ {
+ if(position < LCD_LINE2)
+ {
+ /* Display on Line 1 */
+ lcd_write(CTRL_WR, ((uint8_t)(LCD_HOME_L1 + position)));
+ }
+ else
+ {
+ /* Display on Line 2 */
+ lcd_write(CTRL_WR, ((uint8_t)((LCD_HOME_L2 + position) - LCD_LINE2)));
+ }
+
+ lcd_delay(39000);
+
+ /* set position index to known value */
+ next_pos = position;
+ }
+
+ do
+ {
+ /* Write character to LCD. */
+ lcd_write(DATA_WR,*string++);
+
+ lcd_delay(43000);
+
+ /* Increment position index */
+ next_pos++;
+ }
+ while(*string);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_delay
+* Description : Implements LCD required delays.
+* Arguments : nsecs -
+* Number of nanoseconds to delay. RX111 has max clock of 32MHz which gives a cycle time of 31.3ns.
+* This means that nothing under 313ns should be input. 313ns would be 10 cycles which is still
+* being optimistic for getting in and out of this function.
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_delay(volatile int32_t nsecs)
+{
+ while (0 < nsecs)
+ {
+ /* Subtract off 10 cycles per iteration. This number was obtained when using the Renesas toolchain at
+ optimization level 2. The number to nanoseconds to subtract off below is calculated off of the ICLK speed. */
+ nsecs -= (int32_t)((313.0)*(32000000.0/(float)ICLK_HZ));
+ }
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_nibble_write
+* Description : Writes data to display. Sends command to display.
+* Arguments : value -
+* The value to write
+* data_or_ctrl -
+* Whether to write data or control.
+* 1 = DATA
+* 0 = CONTROL
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value)
+{
+ /* Set Register Select pin high for Data */
+ if (data_or_ctrl == DATA_WR)
+ {
+ /* Data write. */
+ RS_PIN = 1;
+ }
+ else
+ {
+ /* Control write. */
+ RS_PIN = 0;
+ }
+
+ /* tsu1 delay */
+ lcd_delay(60);
+
+ /* EN enable chip (HIGH) */
+ E_PIN = 1;
+
+ /* Output the data */
+ PORT4.PODR.BYTE = (value & 0x0F);
+
+ /* tw delay */
+ lcd_delay(450);
+
+ /* Latch data by dropping E */
+ E_PIN = 0;
+
+ /* th2 delay */
+ lcd_delay(10);
+
+ /* tc delay */
+ lcd_delay(480);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_write
+* Description : This function controls LCD writes to line 1 or 2 of the LCD. You need to use the defines LCD_LINE1 and
+* LCD_LINE2 in order to specify the starting position.
+* For example, to start at the 2nd position on line 1...
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : value -
+* The value to write
+* data_or_ctrl -
+* Whether to write data or control.
+* 1 = DATA
+* 0 = CONTROL
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value)
+{
+ /* Write upper nibble first */
+ lcd_nibble_write(data_or_ctrl, (uint8_t)((value & 0xF0) >> 4));
+
+ /* Write lower nibble second */
+ lcd_nibble_write(data_or_ctrl, (uint8_t)(value & 0x0F));
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.h
new file mode 100644
index 000000000..294dd2e4b
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.h
@@ -0,0 +1,101 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lcd.h
+* Device(s) : RX
+* H/W Platform : RSKRX111
+* Description : Provides variable and function declarations for lcd.c file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/* Multiple inclusion prevention macro */
+#ifndef LCD_H
+#define LCD_H
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Defines standard integer variable types used in this file */
+#include
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* RS register select pin */
+#define RS_PIN PORTC.PODR.BIT.B5
+#define RS_PIN_DDR PORTC.PDR.BIT.B5
+/* Display enable pin */
+#define E_PIN PORTB.PODR.BIT.B1
+#define E_PIN_DDR PORTB.PDR.BIT.B1
+/* Data write/read definition */
+#define DATA_WR 1
+/* Control write/read definition */
+#define CTRL_WR 0
+/* Maximum characters per line of LCD display. */
+#define NUMB_CHARS_PER_LINE 8
+/* Number of lines on the LCD display */
+#define MAXIMUM_LINES 2
+/* Character position of LCD line 1 */
+#define LCD_LINE1 0
+/* Character position of LCD line 2 */
+#define LCD_LINE2 16
+/* Clear LCD display and home cursor */
+#define LCD_CLEAR 0x01
+/* Move cursor to line 1 */
+#define LCD_HOME_L1 0x80
+/* Move cursor to line 2 */
+#define LCD_HOME_L2 0xC0
+/* Cursor auto decrement after R/W */
+#define CURSOR_MODE_DEC 0x04
+/* Cursor auto increment after R/W */
+#define CURSOR_MODE_INC 0x06
+/* Setup, 4 bits,2 lines, 5X7 */
+#define FUNCTION_SET 0x28
+/* Display ON with Cursor */
+#define LCD_CURSOR_ON 0x0E
+/* Display ON with Cursor off */
+#define LCD_CURSOR_OFF 0x0C
+/* Display on with blinking cursor */
+#define LCD_CURSOR_BLINK 0x0D
+/* Move Cursor Left One Position */
+#define LCD_CURSOR_LEFT 0x10
+/* Move Cursor Right One Position */
+#define LCD_CURSOR_RIGHT 0x14
+/* Enable LCD display */
+#define LCD_DISPLAY_ON 0x04
+/* Enable both LCD lines */
+#define LCD_TWO_LINE 0x08
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+/* LCD initialisation function declaration */
+void lcd_initialize (void);
+
+/* Update display function declaration */
+void lcd_display(uint8_t position, uint8_t const * string);
+
+/* Clear LCD function delcaration */
+void lcd_clear (void);
+
+/* End of multiple inclusion prevention macro */
+#endif
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h
new file mode 100644
index 000000000..456688981
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp.h
+* H/W Platform : RSKRX111
+* Description : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef PLATFORM_BOARD_RSKRX111
+#define PLATFORM_BOARD_RSKRX111
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef PLATFORM_DEFINED
+#error "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+#include "r_bsp_config.h"
+#include ".\mcu\rx111\iodefine.h"
+#include ".\mcu\rx111\mcu_info.h"
+#include ".\board\rskrx111\rskrx111.h"
+#include ".\board\rskrx111\lcd.h"
+
+#endif /* PLATFORM_BOARD_RSKRX111 */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h
new file mode 100644
index 000000000..da6dc9d1e
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h
@@ -0,0 +1,250 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.c
+* Device(s) : RX111
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 51 11 5 A D FM
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)
+ | | | | | | |______not used = Blank
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________MCU_PART_GROUP = Group name
+ | | | |______________MCU_PART_SERIES = Series name
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FM = 0x0 = LFQFP/64/0.50
+ FK = 0x1 = LQFP/64/0.80
+ LF = 0x2 = TFLGA/64/0.50
+ FL = 0x3 = LFQFP/48/0.50
+ NE = 0x4 = VQFN/48/0.50
+ NC = 0x5 = HWQFN/36/0.50
+ LM = 0x6 = WFLGA/36/0.50
+ SB = 0x7 = SSOP/36/0.80
+*/
+#define MCU_PART_PACKAGE (0x0)
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 5 = 0x5 = 128KB/16KB/8KB
+ 4 = 0x4 = 96KB/16KB/8KB
+ 3 = 0x3 = 64KB/10KB/8KB
+ 1 = 0x1 = 32KB/10KB/8KB
+ J = 0x0 = 16KB/8KB/8KB
+*/
+#define MCU_PART_MEMORY_SIZE (0x5)
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 10 = 0x0 = RX110 Group
+ 11 = 0x1 = RX111 Group
+*/
+#define MCU_PART_GROUP (0x1)
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 51 = 0x0 = RX100 Series
+*/
+#define MCU_PART_SERIES (0x0)
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define MCU_PART_MEMORY_TYPE (0x0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize su=0x400
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize si=0x100
+#endif
+
+/* Heap size in bytes. */
+#define HEAP_BYTES (0x400)
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define RUN_IN_USER_MODE (0)
+
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = RTOS is used.
+*/
+#define RTOS_USED (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define CLOCK_SOURCE (4)
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the
+ settings would be:
+
+ XTAL_HZ = 16000000
+ PLL_DIV = 2
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz
+*/
+/* XTAL - Input clock frequency in Hz */
+#define XTAL_HZ (16000000)
+/* PLL Input Frequency Divider Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /4
+*/
+#define PLL_DIV (2)
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x6, x8
+*/
+#define PLL_MUL (6)
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define ICK_DIV (2)
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKB_DIV (2)
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKD_DIV (2)
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define FCK_DIV (2)
+
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a
+ function to be called when the event occurs. For example, if the user wanted the function
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would
+ do the following:
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+ If the user does not wish to be alerted of these events then they should comment out the macros.
+
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it
+ is executing. For this reason, it is recommended to keep these callback functions short as to not
+ decrease the real-time response of your system.
+*/
+/* Callback for Supervisor Instruction Violation Exception. */
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb
+
+/* Callback for Undefined Instruction Exception. */
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb
+
+/* Callback for Non-maskable Interrupt. */
+//#define NMI_ISR_CALLBACK nmi_cb
+
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source
+ is creating unwanted interrupts. */
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+
+/* Callback for Bus Error Interrupt. */
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb
+
+/* The user has the option of separately choosing little or big endian for the User Application Area */
+
+/* Endian mode for User Application.
+ 0 = Big Endian
+ Else = Little Endian (Default)
+*/
+#define USER_APP_ENDIAN (1)
+
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ OFS0 - Option Function Select Register 0
+ b31:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1) */
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select
+ 0 1 0 0: 3.10 V
+ 0 1 0 1: 3.00 V
+ 0 1 1 0: 2.90 V
+ 0 1 1 1: 2.79 V
+ 1 0 0 0: 2.68 V
+ 1 0 0 1: 2.58 V
+ 1 0 1 0: 2.48 V
+ 1 0 1 1: 2.06 V
+ 1 1 0 0: 1.96 V
+ 1 1 0 1: 1.86 V
+ b3:b2 Reserved (set to 1)
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define IO_LIB_ENABLE (1)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h
new file mode 100644
index 000000000..af3a40058
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : rskrx111.h
+* H/W Platform : RSKRX111
+* Description : Board specific definitions for the RSKRX111.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef RSKRX111_H
+#define RSKRX111_H
+
+/* Local defines */
+#define LED_ON (0)
+#define LED_OFF (1)
+#define SET_BIT_HIGH (1)
+#define SET_BIT_LOW (0)
+#define SET_BYTE_HIGH (0xFF)
+#define SET_BYTE_LOW (0x00)
+
+/* Switches */
+#define SW_ACTIVE 0
+#define SW1 PORT3.PIDR.BIT.B0
+#define SW2 PORT3.PIDR.BIT.B1
+#define SW3 PORTE.PIDR.BIT.B4
+#define SW1_PDR PORT3.PDR.BIT.B0
+#define SW2_PDR PORT3.PDR.BIT.B1
+#define SW3_PDR PORTE.PDR.BIT.B4
+#define SW1_PMR PORT3.PMR.BIT.B0
+#define SW2_PMR PORT3.PMR.BIT.B1
+#define SW3_PMR PORTE.PMR.BIT.B4
+
+/* LEDs */
+#define LED0 PORTB.PODR.BIT.B7
+#define LED1 PORTA.PODR.BIT.B0
+#define LED2 PORT5.PODR.BIT.B4
+#define LED3 PORT1.PODR.BIT.B7
+#define LED0_PDR PORTB.PDR.BIT.B7
+#define LED1_PDR PORTA.PDR.BIT.B0
+#define LED2_PDR PORT5.PDR.BIT.B4
+#define LED3_PDR PORT1.PDR.BIT.B7
+
+
+#endif /* RSKRX111_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/hardware_setup.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/hardware_setup.c
new file mode 100644
index 000000000..61ec9ab2a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/hardware_setup.c
@@ -0,0 +1,367 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : hwsetup.c
+* Device(s) : RX
+* H/W Platform : RSKRX210
+* Description : Defines the initialization routines used each time the MCU is restarted.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* I/O Register and board definitions */
+#include "platform.h"
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* MCU I/O port configuration function delcaration */
+static void output_ports_configure(void);
+
+/* Interrupt configuration function delcaration */
+static void interrupts_configure(void);
+
+/* MCU peripheral module configuration function declaration */
+static void peripheral_modules_enable(void);
+
+/* Configure MCU clocks. */
+static void clock_source_select (void);
+void operating_frequency_set(void);
+
+/***********************************************************************************************************************
+* Function name: hardware_setup
+* Description : Contains setup functions called at device restart
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void HardwareSetup(void)
+{
+ operating_frequency_set();
+ output_ports_configure();
+ interrupts_configure();
+ peripheral_modules_enable();
+}
+
+/***********************************************************************************************************************
+* Function name: output_ports_configure
+* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void output_ports_configure(void)
+{
+ /* Enable LEDs. */
+ /* Start with LEDs off. */
+ LED0 = LED_OFF;
+ LED1 = LED_OFF;
+ LED2 = LED_OFF;
+ LED3 = LED_OFF;
+
+ /* Set LED pins as outputs. */
+ LED0_PDR = 1;
+ LED1_PDR = 1;
+ LED2_PDR = 1;
+ LED3_PDR = 1;
+
+ /* Enable switches. */
+ /* Set pins as inputs. */
+ SW1_PDR = 0;
+ SW2_PDR = 0;
+ SW3_PDR = 0;
+
+ /* Set port mode registers for switches. */
+ SW1_PMR = 0;
+ SW2_PMR = 0;
+ SW3_PMR = 0;
+
+ /* Unlock MPC registers to enable writing to them. */
+ MPC.PWPR.BIT.B0WI = 0 ; /* Unlock protection register */
+ MPC.PWPR.BIT.PFSWE = 1 ; /* Unlock MPC registers */
+
+ /* TXD1 is output. */
+ PORT1.PDR.BIT.B6 = 1;
+ PORT1.PMR.BIT.B6 = 1;
+ MPC.P16PFS.BYTE = 0x0A;
+ /* RXD1 is input. */
+ PORT1.PDR.BIT.B5 = 0;
+ PORT1.PMR.BIT.B5 = 1;
+ MPC.P15PFS.BYTE = 0x0A;
+
+ /* Configure the pin connected to the ADC Pot as an input */
+ PORT4.PDR.BIT.B4 = 0;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Turn off module stop for the A2D converter. */
+ SYSTEM.MSTPCRA.BIT.MSTPA17 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Initialise the first button to generate an interrupt. */
+ R_SWITCHES_Init();
+}
+
+/***********************************************************************************************************************
+* Function name: interrupts_configure
+* Description : Configures interrupts used
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void interrupts_configure(void)
+{
+ /* Add code here to setup additional interrupts */
+}
+
+/***********************************************************************************************************************
+* Function name: peripheral_modules_enable
+* Description : Enables and configures peripheral devices on the MCU
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void peripheral_modules_enable(void)
+{
+ /* Enable triggers to start an ADC conversion. */
+ S12AD.ADCSR.BIT.TRGE = 1;
+
+ /* Only channel 4 is going to be used. */
+ S12AD.ADANSA.BIT.ANSA4 = 1;
+}
+
+/***********************************************************************************************************************
+* Function name: operating_frequency_set
+* Description : Configures the clock settings for each of the device clocks
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void operating_frequency_set(void)
+{
+ /* Used for constructing value to write to SCKCR and CKOCR registers. */
+ uint32_t temp_clock = 0;
+
+ /*
+ Clock Description Frequency
+ ----------------------------------------
+ Input Clock Frequency............ 16 MHz
+ PLL frequency (x3)............... 48 MHz
+ Internal Clock Frequency......... 24 MHz
+ Peripheral Clock Frequency....... 24 MHz
+ Clock Out Frequency.............. 1 MHz */
+
+ volatile unsigned int i;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Select the clock based upon user's choice. */
+ clock_source_select();
+
+
+ /* Figure out setting for FCK bits. */
+#if FCK_DIV == 1
+ /* Do nothing since FCK bits should be 0. */
+#elif FCK_DIV == 2
+ temp_clock |= 0x10000000;
+#elif FCK_DIV == 4
+ temp_clock |= 0x20000000;
+#elif FCK_DIV == 8
+ temp_clock |= 0x30000000;
+#elif FCK_DIV == 16
+ temp_clock |= 0x40000000;
+#elif FCK_DIV == 32
+ temp_clock |= 0x50000000;
+#elif FCK_DIV == 64
+ temp_clock |= 0x60000000;
+#else
+ #error "Error! Invalid setting for FCK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for ICK bits. */
+#if ICK_DIV == 1
+ /* Do nothing since ICK bits should be 0. */
+#elif ICK_DIV == 2
+ temp_clock |= 0x01000000;
+#elif ICK_DIV == 4
+ temp_clock |= 0x02000000;
+#elif ICK_DIV == 8
+ temp_clock |= 0x03000000;
+#elif ICK_DIV == 16
+ temp_clock |= 0x04000000;
+#elif ICK_DIV == 32
+ temp_clock |= 0x05000000;
+#elif ICK_DIV == 64
+ temp_clock |= 0x06000000;
+#else
+ #error "Error! Invalid setting for ICK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKB bits. */
+#if PCKB_DIV == 1
+ /* Do nothing since PCKB bits should be 0. */
+#elif PCKB_DIV == 2
+ temp_clock |= 0x00000100;
+#elif PCKB_DIV == 4
+ temp_clock |= 0x00000200;
+#elif PCKB_DIV == 8
+ temp_clock |= 0x00000300;
+#elif PCKB_DIV == 16
+ temp_clock |= 0x00000400;
+#elif PCKB_DIV == 32
+ temp_clock |= 0x00000500;
+#elif PCKB_DIV == 64
+ temp_clock |= 0x00000600;
+#else
+ #error "Error! Invalid setting for PCKB_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKD bits. */
+#if PCKD_DIV == 1
+ /* Do nothing since PCKD bits should be 0. */
+#elif PCKD_DIV == 2
+ temp_clock |= 0x00000001;
+#elif PCKD_DIV == 4
+ temp_clock |= 0x00000002;
+#elif PCKD_DIV == 8
+ temp_clock |= 0x00000003;
+#elif PCKD_DIV == 16
+ temp_clock |= 0x00000004;
+#elif PCKD_DIV == 32
+ temp_clock |= 0x00000005;
+#elif PCKD_DIV == 64
+ temp_clock |= 0x00000006;
+#else
+ #error "Error! Invalid setting for PCKD_DIV in r_bsp_config.h"
+#endif
+
+ /* Set SCKCR register. */
+ SYSTEM.SCKCR.LONG = temp_clock;
+
+ /* Choose clock source. Default for r_bsp_config.h is PLL. */
+ SYSTEM.SCKCR3.WORD = ((uint16_t)CLOCK_SOURCE) << 8;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+}
+
+/***********************************************************************************************************************
+* Function name: clock_source_select
+* Description : Enables and disables clocks as chosen by the user. This function also implements the software delays
+* needed for the clocks to stabilize.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+static void clock_source_select (void)
+{
+ /* Declared volatile for software delay purposes. */
+ volatile unsigned int i;
+
+ /* NOTE: AS OF VERSION 0.50 OF THE RX111 HARDWARE MANUAL, ALL OF THE CLOCK
+ * STABILIZATION TIMES ARE TBD. FOR NOW, WHERE EVER A WAIT COUNT REGISTER
+ * IS AVAILABLE, THE DELAY IS SET TO THE MAX NUMBER OF CYCLES. WHERE EVER
+ * DELAY LOOPS ARE PRESENT, THE VALUES FROM THE 63N ARE RE-USED. KEEP IN
+ * MIND THAT THE 63N RUNS ON A FASTER CRYSTAL.
+ */
+
+#if (CLOCK_SOURCE == 1)
+ /* HOCO is chosen. Start it operating. */
+ SYSTEM.HOCOCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the HOCO has stabilized.*/
+ for(i = 0; i< 28; i++) // tHOCOWT2 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#else
+ /* HOCO is not chosen. Stop the HOCO. */
+ SYSTEM.HOCOCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 2)
+ /* Main clock oscillator is chosen. Start it operating. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock has stabilized. */
+ for(i = 0; i< 140; i++) // tMAINOSCWT is TBD
+ {
+ __asm volatile( "NOT" );
+ }
+#endif
+
+#if (CLOCK_SOURCE == 3)
+ /* Sub-clock oscillator is chosen. Start it operating. */
+ /* In section 9.8.4, there is a reference to a SOSCWTCR register, but there is no
+ * description for this register in the manual nor reference for it in iodefine.h. */
+
+ /* Set the sub-clock to operating. */
+ SYSTEM.SOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the sub-clock has stabilized. */
+ for(i = 0; i< 30233; i++) // tSUBOSCWT0 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#else
+ /* Set the sub-clock to stopped. */
+ SYSTEM.SOSCCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 4)
+ /* PLL is chosen. Start it operating. Must start main clock as well since PLL uses it. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+
+ /* Set PLL Input Divisor. */
+ SYSTEM.PLLCR.BIT.PLIDIV = PLL_DIV >> 1;
+
+ /* Set PLL Multiplier. */
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL * 2) - 1;
+
+ /* Set the PLL to operating. */
+ SYSTEM.PLLCR2.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock and PLL have stabilized. */
+ for(i = 0; i< 140; i++) // tPLLWT2 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#endif
+
+ /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn
+ it off until another clock has been enabled and is ready to use. */
+#if (CLOCK_SOURCE == 0)
+ /* LOCO is chosen. This is the default out of reset. */
+ SYSTEM.LOCOCR.BYTE = 0x00;
+#else
+ /* LOCO is not chosen and another clock has already been setup. Turn off the LOCO. */
+ SYSTEM.LOCOCR.BYTE = 0x01;
+#endif
+
+ /* Make sure a valid clock was chosen. */
+#if (CLOCK_SOURCE > 4) || (CLOCK_SOURCE < 0)
+ #error "ERROR - Valid clock source must be chosen in r_bsp_config.h using CLOCK_SOURCE macro."
+#endif
+}
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/r_bsp.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/r_bsp.h
new file mode 100644
index 000000000..bd8881cd6
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/r_bsp.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp.h
+* Description : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 13.01.2012 1.00 First Release
+* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure.
+***********************************************************************************************************************/
+
+#ifndef PLATFORM_BOARD_USER
+#define PLATFORM_BOARD_USER
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef PLATFORM_DEFINED
+#error "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+/* This is a user defined board. Start off by:
+ 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).
+ 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.
+ 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.
+ 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.
+ 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.
+ You can also add your own include files here as well. */
+#include "r_bsp_config.h"
+#include ".\mcu\*MCU Group*\mcu_info.h"
+
+#endif /* PLATFORM_BOARD_USER */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/interrupt_handlers.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/interrupt_handlers.c
new file mode 100644
index 000000000..702dcaea4
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/interrupt_handlers.c
@@ -0,0 +1,283 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : interrupt_handlers.c */
+/* DESCRIPTION : Interrupt Handler */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+
+#include "interrupt_handlers.h"
+
+// INT_Exception(Supervisor Instruction)
+void INT_Excep_SuperVisorInst(void){/* brk(); */}
+
+// Exception(Undefined Instruction)
+void INT_Excep_UndefinedInst(void){/* brk(); */}
+
+// Exception(Floating Point)
+void INT_Excep_FloatingPoint(void){/* brk(); */}
+
+// NMI
+void INT_NonMaskableInterrupt(void){/* brk(); */}
+
+// Dummy
+void Dummy(void)
+{
+ for( ;; );
+}
+
+// BRK
+void INT_Excep_BRK(void){/* wait(); */}
+//;0x0000 Reserved
+
+void INT_Excep_BUSERR(void){ }
+
+// ICU SWINT
+void INT_Excep_ICU_SWINT(void){ }
+
+// CMT0 CMI0
+void INT_Excep_CMT0_CMI0(void){ }
+
+// CMT1 CMI1
+void INT_Excep_CMT1_CMI1(void){ }
+
+// CAC FERRF
+void INT_Excep_CAC_FERRF(void){ }
+
+// CAC MENDF
+void INT_Excep_CAC_MENDF(void){ }
+
+// CAC OVFF
+void INT_Excep_CAC_OVFF(void){ }
+
+// USB0 D0FIFO0
+void INT_Excep_USB0_D0FIFO0(void){ }
+
+// USB0 D1FIFO0
+void INT_Excep_USB0_D1FIFO0(void){ }
+
+// USB0 USBI0
+void INT_Excep_USB0_USBI0(void){ }
+
+// RSPI0 SPEI0
+void INT_Excep_RSPI0_SPEI0(void){ }
+
+// RSPI0 SPRI0
+void INT_Excep_RSPI0_SPRI0(void){ }
+
+// RSPI0 SPTI0
+void INT_Excep_RSPI0_SPTI0(void){ }
+
+// RSPI0 SPII0
+void INT_Excep_RSPI0_SPII0(void){ }
+
+// DOC DOPCF
+void INT_Excep_DOC_DOPCF(void){ }
+
+// RTC CUP
+void INT_Excep_RTC_CUP(void){ }
+
+// ICU IRQ0
+void INT_Excep_ICU_IRQ0(void){ }
+
+// ICU IRQ1
+void INT_Excep_ICU_IRQ1(void){ }
+
+// ICU IRQ2
+void INT_Excep_ICU_IRQ2(void){ }
+
+// ICU IRQ3
+void INT_Excep_ICU_IRQ3(void){ }
+
+// ICU IRQ4
+void INT_Excep_ICU_IRQ4(void){ }
+
+// ICU IRQ5
+void INT_Excep_ICU_IRQ5(void){ }
+
+// ICU IRQ6
+void INT_Excep_ICU_IRQ6(void){ }
+
+// ICU IRQ7
+void INT_Excep_ICU_IRQ7(void){ }
+
+// LVD LVD1
+void INT_Excep_LVD_LVD1(void){ }
+
+// LVD LVD2
+void INT_Excep_LVD_LVD2(void){ }
+
+// USB0 USBR0
+void INT_Excep_USB0_USBR0(void){ }
+
+// RTC ALM
+void INT_Excep_RTC_ALM(void){ }
+
+// RTC PRD
+void INT_Excep_RTC_PRD(void){ }
+
+// S12AD S12ADI0
+void INT_Excep_S12AD_S12ADI0(void){ }
+
+// S12AD GBADI
+void INT_Excep_S12AD_GBADI(void){ }
+
+// ELC ELSR18I
+void INT_Excep_ELC_ELSR18I(void){ }
+
+// MTU0 TGIA0
+void INT_Excep_MTU0_TGIA0(void){ }
+
+// MTU0 TGIB0
+void INT_Excep_MTU0_TGIB0(void){ }
+
+// MTU0 TGIC0
+void INT_Excep_MTU0_TGIC0(void){ }
+
+// MTU0 TGID0
+void INT_Excep_MTU0_TGID0(void){ }
+
+// MTU0 TCIV0
+void INT_Excep_MTU0_TCIV0(void){ }
+
+// MTU0 TGIE0
+void INT_Excep_MTU0_TGIE0(void){ }
+
+// MTU0 TGIF0
+void INT_Excep_MTU0_TGIF0(void){ }
+
+// MTU1 TGIA1
+void INT_Excep_MTU1_TGIA1(void){ }
+
+// MTU1 TGIB1
+void INT_Excep_MTU1_TGIB1(void){ }
+
+// MTU1 TCIV1
+void INT_Excep_MTU1_TCIV1(void){ }
+
+// MTU1 TCIU1
+void INT_Excep_MTU1_TCIU1(void){ }
+
+// MTU2 TGIA2
+void INT_Excep_MTU2_TGIA2(void){ }
+
+// MTU2 TGIB2
+void INT_Excep_MTU2_TGIB2(void){ }
+
+// MTU2 TCIV2
+void INT_Excep_MTU2_TCIV2(void){ }
+
+// MTU2 TCIU2
+void INT_Excep_MTU2_TCIU2(void){ }
+
+// MTU3 TGIA3
+void INT_Excep_MTU3_TGIA3(void){ }
+
+// MTU3 TGIB3
+void INT_Excep_MTU3_TGIB3(void){ }
+
+// MTU3 TGIC3
+void INT_Excep_MTU3_TGIC3(void){ }
+
+// MTU3 TGID3
+void INT_Excep_MTU3_TGID3(void){ }
+
+// MTU3 TCIV3
+void INT_Excep_MTU3_TCIV3(void){ }
+
+// MTU4 TGIA4
+void INT_Excep_MTU4_TGIA4(void){ }
+
+// MTU4 TGIB4
+void INT_Excep_MTU4_TGIB4(void){ }
+
+// MTU4 TGIC4
+void INT_Excep_MTU4_TGIC4(void){ }
+
+// MTU4 TGID4
+void INT_Excep_MTU4_TGID4(void){ }
+
+// MTU4 TCIV4
+void INT_Excep_MTU4_TCIV4(void){ }
+
+// MTU5 TGIU5
+void INT_Excep_MTU5_TGIU5(void){ }
+
+// MTU5 TGIV5
+void INT_Excep_MTU5_TGIV5(void){ }
+
+// MTU5 TGIW5
+void INT_Excep_MTU5_TGIW5(void){ }
+
+// POE OEI1
+void INT_Excep_POE_OEI1(void){ }
+
+// POE OEI2
+void INT_Excep_POE_OEI2(void){ }
+
+// SCI1 ERI1
+void INT_Excep_SCI1_ERI1(void){ }
+
+// SCI1 RXI1
+void INT_Excep_SCI1_RXI1(void){ }
+
+// SCI1 TXI1
+void INT_Excep_SCI1_TXI1(void){ }
+
+// SCI1 TEI1
+void INT_Excep_SCI1_TEI1(void){ }
+
+// SCI5 ERI5
+void INT_Excep_SCI5_ERI5(void){ }
+
+// SCI5 RXI5
+void INT_Excep_SCI5_RXI5(void){ }
+
+// SCI5 TXI5
+void INT_Excep_SCI5_TXI5(void){ }
+
+// SCI5 TEI5
+void INT_Excep_SCI5_TEI5(void){ }
+
+// SCI12 ERI12
+void INT_Excep_SCI12_ERI12(void){ }
+
+// SCI12 RXI12
+void INT_Excep_SCI12_RXI12(void){ }
+
+// SCI12 TXI12
+void INT_Excep_SCI12_TXI12(void){ }
+
+// SCI12 TEI12
+void INT_Excep_SCI12_TEI12(void){ }
+
+// SCI12 SCIX0
+void INT_Excep_SCI12_SCIX0(void){ }
+
+// SCI12 SCIX1
+void INT_Excep_SCI12_SCIX1(void){ }
+
+// SCI12 SCIX2
+void INT_Excep_SCI12_SCIX2(void){ }
+
+// SCI12 SCIX3
+void INT_Excep_SCI12_SCIX3(void){ }
+
+// RIIC0 EEI0
+void INT_Excep_RIIC0_EEI0(void){ }
+
+// RIIC0 RXI0
+void INT_Excep_RIIC0_RXI0(void){ }
+
+// RIIC0 TXI0
+void INT_Excep_RIIC0_TXI0(void){ }
+
+// RIIC0 TEI0
+void INT_Excep_RIIC0_TEI0(void){ }
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/interrupt_handlers.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/interrupt_handlers.h
new file mode 100644
index 000000000..5cff1bb76
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/interrupt_handlers.h
@@ -0,0 +1,371 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : interrupt_handlers.h */
+/* DESCRIPTION : Interrupt Handler Declarations */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+
+
+
+#ifndef INTERRUPT_HANDLERS_H
+#define INTERRUPT_HANDLERS_H
+
+// Exception(Supervisor Instruction)
+// Exception(Supervisor Instruction)
+void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt));
+
+// Exception(Undefined Instruction)
+void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt));
+
+// Exception(Floating Point)
+void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt));
+
+// NMI
+void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt));
+
+// Dummy
+void Dummy (void) __attribute__ ((interrupt));
+
+// BRK
+void INT_Excep_BRK(void) __attribute__ ((interrupt));
+//;0x0000 Reserved
+
+void INT_Excep_BUSERR(void) __attribute__ ((interrupt));
+//;0x0044 Reserved
+
+void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt));
+
+// CMT0 CMI0
+
+void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt));
+
+// CMT1 CMI1
+
+void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt));
+
+// CAC FERRF
+
+void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt));
+
+// CAC MENDF
+
+
+void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt));
+
+// CAC OVFF
+
+void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt));
+
+// USB0 D0FIFO0
+
+void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt));
+
+// USB0 D1FIFO0
+
+void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt));
+
+// USB0 USBI0
+
+void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt));
+
+// RSPI0 SPEI0
+
+void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt));
+
+// RSPI0 SPRI0
+
+void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt));
+
+// RSPI0 SPTI0
+
+void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt));
+
+// RSPI0 SPII0
+
+void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt));
+
+// DOC DOPCF
+
+void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt));
+
+// RTC CUP
+
+void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt));
+
+// ICU IRQ0
+
+void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt));
+
+// ICU IRQ1
+
+void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt));
+
+// ICU IRQ2
+
+void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt));
+
+// ICU IRQ3
+
+void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt));
+
+// ICU IRQ4
+
+void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt));
+
+// ICU IRQ5
+
+void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt));
+
+// ICU IRQ6
+
+void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt));
+
+// ICU IRQ7
+
+void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt));
+
+// LVD LVD1
+
+void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt));
+
+// LVD LVD2
+
+void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt));
+
+// USB0 USBR0
+
+void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt));
+
+// RTC ALM
+
+void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt));
+
+// RTC PRD
+
+void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt));
+
+// S12AD S12ADI0
+
+void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt));
+
+// S12AD GBADI
+
+void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt));
+
+// ELC ELSR18I
+
+void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt));
+
+// MTU0 TGIA0
+
+void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt));
+
+// MTU0 TGIB0
+
+void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt));
+
+// MTU0 TGIC0
+
+void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt));
+
+// MTU0 TGID0
+
+void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt));
+
+// MTU0 TCIV0
+
+void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt));
+
+// MTU0 TGIE0
+
+void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt));
+
+// MTU0 TGIF0
+
+void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt));
+
+// MTU1 TGIA1
+
+void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt));
+
+// MTU1 TGIB1
+
+void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt));
+
+// MTU1 TCIV1
+
+void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt));
+
+// MTU1 TCIU1
+
+void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt));
+
+// MTU2 TGIA2
+
+void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt));
+
+// MTU2 TGIB2
+
+void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt));
+
+// MTU2 TCIV2
+
+void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt));
+
+// MTU2 TCIU2
+
+void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt));
+
+// MTU3 TGIA3
+
+void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt));
+
+// MTU3 TGIB3
+
+void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt));
+
+// MTU3 TGIC3
+
+void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt));
+
+// MTU3 TGID3
+
+void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt));
+
+// MTU3 TCIV3
+
+void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt));
+
+// MTU4 TGIA4
+
+void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt));
+
+// MTU4 TGIB4
+
+void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt));
+
+// MTU4 TGIC4
+
+void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt));
+
+// MTU4 TGID4
+
+void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt));
+
+// MTU4 TCIV4
+
+void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt));
+
+// MTU5 TGIU5
+
+void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt));
+
+// MTU5 TGIV5
+
+void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt));
+
+// MTU5 TGIW5
+
+void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt));
+
+// POE OEI1
+
+void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt));
+
+// POE OEI2
+
+void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt));
+
+// SCI1 ERI1
+
+void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt));
+
+// SCI1 RXI1
+
+void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt));
+
+// SCI1 TXI1
+
+void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt));
+
+// SCI1 TEI1
+
+void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt));
+
+// SCI5 ERI5
+
+void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt));
+
+// SCI5 RXI5
+
+void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt));
+
+// SCI5 TXI5
+
+void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt));
+
+// SCI5 TEI5
+
+void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt));
+
+// SCI12 ERI12
+
+void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt));
+
+// SCI12 RXI12
+
+void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt));
+
+// SCI12 TXI12
+
+void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt));
+
+// SCI12 TEI12
+
+void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt));
+
+// SCI12 SCIX0
+
+void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt));
+
+// SCI12 SCIX1
+
+void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt));
+
+// SCI12 SCIX2
+
+void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt));
+
+// SCI12 SCIX3
+
+void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt));
+
+// RIIC0 EEI0
+
+void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt));
+
+// RIIC0 RXI0
+
+void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt));
+
+// RIIC0 TXI0
+
+void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt));
+
+// RIIC0 TEI0
+
+void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt));
+
+//;<>
+//;Power On Reset PC
+extern void PowerON_Reset(void);
+//;<>
+#endif
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/iodefine.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/iodefine.h
new file mode 100644
index 000000000..accd3e12e
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/iodefine.h
@@ -0,0 +1,9922 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : iodefine.h */
+/* DESCRIPTION : Definition of I/O Registers */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+
+/* Generated by GNURX IO Header File Converter */
+
+/********************************************************************************/
+/* */
+/* Note : This is a typical example. */
+/* History : V0.5 (2012-09-25) [Hardware Manual Revision : 0.50] */
+/* Abstract : Definition of I/O Register. */
+/* File Name : iodefine.h */
+/* Device : RX/RX100/RX111 */
+/* */
+/* Copyright(c) 2012 Renesas Electronics Corp. */
+/* And Renesas Solutions Corp. ,All Rights Reserved. */
+/* */
+/********************************************************************************/
+/* */
+/* CPU TYPE : RX111 */
+/* DESCRIPTION : Definition of ICU Register */
+/* */
+/* Usage : IR,DTCER,IER,IPR of ICU Register */
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */
+/* The bit access operation is "Bit_Name(interrupt source,name)". */
+/* A part of the name can be omitted. */
+/* IR(MTU0,TGIA0) = 0; expands to : */
+/* for example : */
+/* ICU.IR[114].BIT.IR = 0; */
+/* */
+/* DTCE(ICU,IRQ0) = 1; expands to : */
+/* ICU.DTCER[64].BIT.DTCE = 1; */
+/* */
+/* IEN(CMT0,CMI0) = 1; expands to : */
+/* ICU.IER[0x03].BIT.IEN4 = 1; */
+/* */
+/* IPR(MTU1,TGIA1) = 2; expands to : */
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */
+/* ICU.IPR[121].BIT.IPR = 2; */
+/* */
+/* IPR(SCI1,ERI1) = 3; expands to : */
+/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */
+/* ICU.IPR[218].BIT.IPR = 3; */
+/* */
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */
+/* The number of vector is "(interrupt source, name)". */
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */
+/* for example : */
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */
+/* */
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */
+/* The bit access operation is "MSTP(name)". */
+/* The name that can be used is a macro name defined with "iodefine.h". */
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */
+/* for example : */
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */
+/* */
+/* */
+/********************************************************************************/
+#ifndef __RX111IODEFINE_HEADER__
+#define __RX111IODEFINE_HEADER__
+
+#ifdef __RX_LITTLE_ENDIAN__
+
+struct st_bsc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char STSCLR:1;
+ unsigned char :7;
+ } BIT;
+ } BERCLR;
+ char wk0[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IGAEN:1;
+ unsigned char :7;
+ } BIT;
+ } BEREN;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IA:1;
+ unsigned char :3;
+ unsigned char MST:3;
+ unsigned char :1;
+ } BIT;
+ } BERSR1;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADDR:13;
+ } BIT;
+ } BERSR2;
+ char wk3[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BPRA:2;
+ unsigned short BPRO:2;
+ unsigned short BPIB:2;
+ unsigned short BPGB:2;
+ unsigned short :2;
+ unsigned short BPFB:2;
+ unsigned short :4;
+ } BIT;
+ } BUSPRI;
+};
+
+struct st_cac {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CFME:1;
+ unsigned char :7;
+ } BIT;
+ } CACR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CACREFE:1;
+ unsigned char FMCS:3;
+ unsigned char TCSS:2;
+ unsigned char EDGES:2;
+ } BIT;
+ } CACR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RPS:1;
+ unsigned char RSCS:3;
+ unsigned char RCDS:2;
+ unsigned char DFS:2;
+ } BIT;
+ } CACR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FERRIE:1;
+ unsigned char MENDIE:1;
+ unsigned char OVFIE:1;
+ unsigned char :1;
+ unsigned char FERRFCL:1;
+ unsigned char MENDFCL:1;
+ unsigned char OVFFCL:1;
+ unsigned char :1;
+ } BIT;
+ } CAICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FERRF:1;
+ unsigned char MENDF:1;
+ unsigned char OVFF:1;
+ unsigned char :5;
+ } BIT;
+ } CASTR;
+ char wk0[1];
+ unsigned short CAULVR;
+ unsigned short CALLVR;
+ unsigned short CACNTBR;
+};
+
+struct st_cmt {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short STR0:1;
+ unsigned short STR1:1;
+ unsigned short :14;
+ } BIT;
+ } CMSTR0;
+};
+
+struct st_cmt0 {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CKS:2;
+ unsigned short :4;
+ unsigned short CMIE:1;
+ unsigned short :9;
+ } BIT;
+ } CMCR;
+ unsigned short CMCNT;
+ unsigned short CMCOR;
+};
+
+struct st_crc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char GPS:2;
+ unsigned char LMS:1;
+ unsigned char :4;
+ unsigned char DORCLR:1;
+ } BIT;
+ } CRCCR;
+ unsigned char CRCDIR;
+ unsigned short CRCDOR;
+};
+
+struct st_da {
+ unsigned short DADR0;
+ unsigned short DADR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DAOE0:1;
+ unsigned char DAOE1:1;
+ } BIT;
+ } DACR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DPSEL:1;
+ } BIT;
+ } DADPR;
+};
+
+struct st_doc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OMS:2;
+ unsigned char DCSEL:1;
+ unsigned char :1;
+ unsigned char DOPCIE:1;
+ unsigned char DOPCF:1;
+ unsigned char DOPCFCL:1;
+ unsigned char :1;
+ } BIT;
+ } DOCR;
+ char wk0[1];
+ unsigned short DODIR;
+ unsigned short DODSR;
+};
+
+struct st_dtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char RRS:1;
+ unsigned char :3;
+ } BIT;
+ } DTCCR;
+ char wk0[3];
+ void *DTCVBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SHORT:1;
+ unsigned char :7;
+ } BIT;
+ } DTCADMOD;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DTCST:1;
+ unsigned char :7;
+ } BIT;
+ } DTCST;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VECN:8;
+ unsigned short :7;
+ unsigned short ACT:1;
+ } BIT;
+ } DTCSTS;
+};
+
+struct st_elc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ELCON:1;
+ } BIT;
+ } ELCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELS:8;
+ } BIT;
+ } ELSR[26];
+ char wk0[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char MTU1MD:2;
+ unsigned char MTU2MD:2;
+ unsigned char MTU3MD:2;
+ } BIT;
+ } ELOPA;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTU4MD:2;
+ unsigned char :6;
+ } BIT;
+ } ELOPB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char CMT1MD:2;
+ unsigned char :4;
+ } BIT;
+ } ELOPC;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PGR0:1;
+ unsigned char PGR1:1;
+ unsigned char PGR2:1;
+ unsigned char PGR3:1;
+ unsigned char PGR4:1;
+ unsigned char PGR5:1;
+ unsigned char PGR6:1;
+ unsigned char PGR7:1;
+ } BIT;
+ } PGR1;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PGCI:2;
+ unsigned char PGCOVE:1;
+ unsigned char :1;
+ unsigned char PGCO:3;
+ unsigned char :1;
+ } BIT;
+ } PGC1;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PDBF0:1;
+ unsigned char PDBF1:1;
+ unsigned char PDBF2:1;
+ unsigned char PDBF3:1;
+ unsigned char PDBF4:1;
+ unsigned char PDBF5:1;
+ unsigned char PDBF6:1;
+ unsigned char PDBF7:1;
+ } BIT;
+ } PDBF1;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSB:3;
+ unsigned char PSP:2;
+ unsigned char PSM:2;
+ unsigned char :1;
+ } BIT;
+ } PEL0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSB:3;
+ unsigned char PSP:2;
+ unsigned char PSM:2;
+ unsigned char :1;
+ } BIT;
+ } PEL1;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SEG:1;
+ unsigned char :5;
+ unsigned char WE:1;
+ unsigned char WI:1;
+ } BIT;
+ } ELSEGR;
+};
+
+struct st_flash {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DFLEN:1;
+ unsigned char :7;
+ } BIT;
+ } DFLCTL;
+};
+
+struct st_icu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IR:1;
+ unsigned char :7;
+ } BIT;
+ } IR[250];
+ char wk0[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DTCE:1;
+ unsigned char :7;
+ } BIT;
+ } DTCER[249];
+ char wk1[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IEN0:1;
+ unsigned char IEN1:1;
+ unsigned char IEN2:1;
+ unsigned char IEN3:1;
+ unsigned char IEN4:1;
+ unsigned char IEN5:1;
+ unsigned char IEN6:1;
+ unsigned char IEN7:1;
+ } BIT;
+ } IER[32];
+ char wk2[192];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SWINT:1;
+ unsigned char :7;
+ } BIT;
+ } SWINTR;
+ char wk3[15];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FVCT:8;
+ unsigned short :7;
+ unsigned short FIEN:1;
+ } BIT;
+ } FIR;
+ char wk4[14];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IPR:4;
+ unsigned char :4;
+ } BIT;
+ } IPR[250];
+ char wk5[262];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :2;
+ unsigned char IRQMD:2;
+ unsigned char :4;
+ } BIT;
+ } IRQCR[8];
+ char wk6[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FLTEN0:1;
+ unsigned char FLTEN1:1;
+ unsigned char FLTEN2:1;
+ unsigned char FLTEN3:1;
+ unsigned char FLTEN4:1;
+ unsigned char FLTEN5:1;
+ unsigned char FLTEN6:1;
+ unsigned char FLTEN7:1;
+ } BIT;
+ } IRQFLTE0;
+ char wk7[3];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FCLKSEL0:2;
+ unsigned short FCLKSEL1:2;
+ unsigned short FCLKSEL2:2;
+ unsigned short FCLKSEL3:2;
+ unsigned short FCLKSEL4:2;
+ unsigned short FCLKSEL5:2;
+ unsigned short FCLKSEL6:2;
+ unsigned short FCLKSEL7:2;
+ } BIT;
+ } IRQFLTC0;
+ char wk8[106];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NMIST:1;
+ unsigned char OSTST:1;
+ unsigned char :1;
+ unsigned char IWDTST:1;
+ unsigned char LVD1ST:1;
+ unsigned char LVD2ST:1;
+ unsigned char :2;
+ } BIT;
+ } NMISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NMIEN:1;
+ unsigned char OSTEN:1;
+ unsigned char :1;
+ unsigned char IWDTEN:1;
+ unsigned char LVD1EN:1;
+ unsigned char LVD2EN:1;
+ unsigned char :2;
+ } BIT;
+ } NMIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NMICLR:1;
+ unsigned char OSTCLR:1;
+ unsigned char :1;
+ unsigned char IWDTCLR:1;
+ unsigned char LVD1CLR:1;
+ unsigned char LVD2CLR:1;
+ unsigned char :2;
+ } BIT;
+ } NMICLR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char NMIMD:1;
+ unsigned char :4;
+ } BIT;
+ } NMICR;
+ char wk9[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFLTEN:1;
+ unsigned char :7;
+ } BIT;
+ } NMIFLTE;
+ char wk10[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFCLKSEL:2;
+ unsigned char :6;
+ } BIT;
+ } NMIFLTC;
+};
+
+struct st_iwdt {
+ unsigned char IWDTRR;
+ char wk0[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TOPS:2;
+ unsigned short :2;
+ unsigned short CKS:4;
+ unsigned short RPES:2;
+ unsigned short :2;
+ unsigned short RPSS:2;
+ unsigned short :2;
+ } BIT;
+ } IWDTCR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CNTVAL:14;
+ unsigned short UNDFF:1;
+ unsigned short REFEF:1;
+ } BIT;
+ } IWDTSR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char RSTIRQS:1;
+ } BIT;
+ } IWDTRCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char SLCSTP:1;
+ } BIT;
+ } IWDTCSTPR;
+};
+
+struct st_mpc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :6;
+ unsigned char PFSWE:1;
+ unsigned char B0WI:1;
+ } BIT;
+ } PWPR;
+ char wk0[35];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P03PFS;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P05PFS;
+ char wk2[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P14PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P15PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P16PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P17PFS;
+ char wk3[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } P26PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } P27PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P30PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P31PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P32PFS;
+ char wk4[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :6;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } P35PFS;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P40PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P41PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P42PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P43PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P44PFS;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned short :7;
+ unsigned char ASEL:1;
+ } BIT;
+ } P46PFS;
+ char wk7[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } P54PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } P55PFS;
+ char wk8[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PA0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PA1PFS;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } PA3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } PA4PFS;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } PA6PFS;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } PB0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } PB1PFS;
+ char wk12[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PB3PFS;
+ char wk13[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PB5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PB6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PB7PFS;
+ char wk14[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PC2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PC3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ } BIT;
+ } PC4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PC5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PC6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :3;
+ } BIT;
+ } PC7PFS;
+ char wk15[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE1PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL:5;
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char ASEL:1;
+ } BIT;
+ } PE7PFS;
+ char wk16[30];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ7PFS;
+};
+
+struct st_mtu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OE3B:1;
+ unsigned char OE4A:1;
+ unsigned char OE4B:1;
+ unsigned char OE3D:1;
+ unsigned char OE4C:1;
+ unsigned char OE4D:1;
+ unsigned char :2;
+ } BIT;
+ } TOER;
+ char wk0[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char UF:1;
+ unsigned char VF:1;
+ unsigned char WF:1;
+ unsigned char FB:1;
+ unsigned char P:1;
+ unsigned char N:1;
+ unsigned char BDC:1;
+ unsigned char :1;
+ } BIT;
+ } TGCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OLSP:1;
+ unsigned char OLSN:1;
+ unsigned char TOCS:1;
+ unsigned char TOCL:1;
+ unsigned char :2;
+ unsigned char PSYE:1;
+ unsigned char :1;
+ } BIT;
+ } TOCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OLS1P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS3N:1;
+ unsigned char BF:2;
+ } BIT;
+ } TOCR2;
+ char wk1[4];
+ unsigned short TCDR;
+ unsigned short TDDR;
+ char wk2[8];
+ unsigned short TCNTS;
+ unsigned short TCBR;
+ char wk3[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char T4VCOR:3;
+ unsigned char T4VEN:1;
+ unsigned char T3ACOR:3;
+ unsigned char T3AEN:1;
+ } BIT;
+ } TITCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char T4VCNT:3;
+ unsigned char :1;
+ unsigned char T3ACNT:3;
+ unsigned char :1;
+ } BIT;
+ } TITCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BTE:2;
+ unsigned char :6;
+ } BIT;
+ } TBTER;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TDER:1;
+ unsigned char :7;
+ } BIT;
+ } TDER;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OLS1P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS3N:1;
+ unsigned char :2;
+ } BIT;
+ } TOLBR;
+ char wk6[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char WRE:1;
+ unsigned char :6;
+ unsigned char CCE:1;
+ } BIT;
+ } TWCR;
+ char wk7[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CST0:1;
+ unsigned char CST1:1;
+ unsigned char CST2:1;
+ unsigned char :3;
+ unsigned char CST3:1;
+ unsigned char CST4:1;
+ } BIT;
+ } TSTR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SYNC0:1;
+ unsigned char SYNC1:1;
+ unsigned char SYNC2:1;
+ unsigned char :3;
+ unsigned char SYNC3:1;
+ unsigned char SYNC4:1;
+ } BIT;
+ } TSYR;
+ char wk8[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RWE:1;
+ unsigned char :7;
+ } BIT;
+ } TRWER;
+};
+
+struct st_mtu0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFAEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFDEN:1;
+ unsigned char NFCS:2;
+ unsigned char :2;
+ } BIT;
+ } NFCR;
+ char wk0[111];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:3;
+ unsigned char CKEG:2;
+ unsigned char CCLR:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MD:4;
+ unsigned char BFA:1;
+ unsigned char BFB:1;
+ unsigned char BFE:1;
+ unsigned char :1;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOA:4;
+ unsigned char IOB:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOC:4;
+ unsigned char IOD:4;
+ } BIT;
+ } TIORL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIEA:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIED:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TTGE:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk1[16];
+ unsigned short TGRE;
+ unsigned short TGRF;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIEE:1;
+ unsigned char TGIEF:1;
+ unsigned char :6;
+ } BIT;
+ } TIER2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTSA:1;
+ unsigned char TTSB:1;
+ unsigned char TTSE:1;
+ unsigned char :5;
+ } BIT;
+ } TBTM;
+};
+
+struct st_mtu1 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFAEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFDEN:1;
+ unsigned char NFCS:2;
+ unsigned char :2;
+ } BIT;
+ } NFCR;
+ char wk1[238];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:3;
+ unsigned char CKEG:2;
+ unsigned char CCLR:2;
+ unsigned char :1;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MD:4;
+ unsigned char :4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOA:4;
+ unsigned char IOB:4;
+ } BIT;
+ } TIOR;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIEA:1;
+ unsigned char TGIEB:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TCIEU:1;
+ unsigned char :1;
+ unsigned char TTGE:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk3[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char I1AE:1;
+ unsigned char I1BE:1;
+ unsigned char I2AE:1;
+ unsigned char I2BE:1;
+ unsigned char :4;
+ } BIT;
+ } TICCR;
+};
+
+struct st_mtu2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFAEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFDEN:1;
+ unsigned char NFCS:2;
+ unsigned char :2;
+ } BIT;
+ } NFCR;
+ char wk0[365];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:3;
+ unsigned char CKEG:2;
+ unsigned char CCLR:2;
+ unsigned char :1;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MD:4;
+ unsigned char :4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOA:4;
+ unsigned char IOB:4;
+ } BIT;
+ } TIOR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIEA:1;
+ unsigned char TGIEB:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TCIEU:1;
+ unsigned char :1;
+ unsigned char TTGE:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+};
+
+struct st_mtu3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:3;
+ unsigned char CKEG:2;
+ unsigned char CCLR:3;
+ } BIT;
+ } TCR;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MD:4;
+ unsigned char BFA:1;
+ unsigned char BFB:1;
+ unsigned char :2;
+ } BIT;
+ } TMDR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOA:4;
+ unsigned char IOB:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOC:4;
+ unsigned char IOD:4;
+ } BIT;
+ } TIORL;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIEA:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIED:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TTGE:1;
+ } BIT;
+ } TIER;
+ char wk3[7];
+ unsigned short TCNT;
+ char wk4[6];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk5[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk6[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTSA:1;
+ unsigned char TTSB:1;
+ unsigned char TTSE:1;
+ unsigned char :5;
+ } BIT;
+ } TBTM;
+ char wk8[90];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFAEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFDEN:1;
+ unsigned char NFCS:2;
+ unsigned char :2;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu4 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:3;
+ unsigned char CKEG:2;
+ unsigned char CCLR:3;
+ } BIT;
+ } TCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MD:4;
+ unsigned char BFA:1;
+ unsigned char BFB:1;
+ unsigned char :2;
+ } BIT;
+ } TMDR;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOA:4;
+ unsigned char IOB:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOC:4;
+ unsigned char IOD:4;
+ } BIT;
+ } TIORL;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIEA:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIED:1;
+ unsigned char TCIEV:1;
+ unsigned char :1;
+ unsigned char TTGE2:1;
+ unsigned char TTGE:1;
+ } BIT;
+ } TIER;
+ char wk4[8];
+ unsigned short TCNT;
+ char wk5[8];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk6[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk8[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTSA:1;
+ unsigned char TTSB:1;
+ unsigned char TTSE:1;
+ unsigned char :5;
+ } BIT;
+ } TBTM;
+ char wk9[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ITB4VE:1;
+ unsigned short ITB3AE:1;
+ unsigned short ITA4VE:1;
+ unsigned short ITA3AE:1;
+ unsigned short DT4BE:1;
+ unsigned short UT4BE:1;
+ unsigned short DT4AE:1;
+ unsigned short UT4AE:1;
+ unsigned short :6;
+ unsigned short BF:2;
+ } BIT;
+ } TADCR;
+ char wk10[2];
+ unsigned short TADCORA;
+ unsigned short TADCORB;
+ unsigned short TADCOBRA;
+ unsigned short TADCOBRB;
+ char wk11[72];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFAEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFDEN:1;
+ unsigned char NFCS:2;
+ unsigned char :2;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu5 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFUEN:1;
+ unsigned char NFVEN:1;
+ unsigned char NFWEN:1;
+ unsigned char :1;
+ unsigned char NFCS:2;
+ unsigned char :2;
+ } BIT;
+ } NFCR;
+ char wk1[490];
+ unsigned short TCNTU;
+ unsigned short TGRU;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:2;
+ unsigned char :6;
+ } BIT;
+ } TCRU;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOC:5;
+ unsigned char :3;
+ } BIT;
+ } TIORU;
+ char wk3[9];
+ unsigned short TCNTV;
+ unsigned short TGRV;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:2;
+ unsigned char :6;
+ } BIT;
+ } TCRV;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOC:5;
+ unsigned char :3;
+ } BIT;
+ } TIORV;
+ char wk5[9];
+ unsigned short TCNTW;
+ unsigned short TGRW;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TPSC:2;
+ unsigned char :6;
+ } BIT;
+ } TCRW;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOC:5;
+ unsigned char :3;
+ } BIT;
+ } TIORW;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TGIE5W:1;
+ unsigned char TGIE5V:1;
+ unsigned char TGIE5U:1;
+ unsigned char :5;
+ } BIT;
+ } TIER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CSTW5:1;
+ unsigned char CSTV5:1;
+ unsigned char CSTU5:1;
+ unsigned char :5;
+ } BIT;
+ } TSTR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CMPCLR5W:1;
+ unsigned char CMPCLR5V:1;
+ unsigned char CMPCLR5U:1;
+ unsigned char :5;
+ } BIT;
+ } TCNTCMPCLR;
+};
+
+struct st_poe {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char POE0M:2;
+ unsigned char POE1M:2;
+ unsigned char POE2M:2;
+ unsigned char POE3M:2;
+ unsigned char PIE1:1;
+ unsigned char :3;
+ unsigned char POE0F:1;
+ unsigned char POE1F:1;
+ unsigned char POE2F:1;
+ unsigned char POE3F:1;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char OIE1:1;
+ unsigned char OCE1:1;
+ unsigned char :5;
+ unsigned char OSF1:1;
+ } BIT;
+ } OCSR1;
+ char wk0[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char POE8M:2;
+ unsigned char :6;
+ unsigned char PIE2:1;
+ unsigned char POE8E:1;
+ unsigned char :2;
+ unsigned char POE8F:1;
+ unsigned char :3;
+ } BIT;
+ } ICSR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CH34HIZ:1;
+ unsigned char CH0HIZ:1;
+ unsigned char :6;
+ } BIT;
+ } SPOER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PE0ZE:1;
+ unsigned char PE1ZE:1;
+ unsigned char PE2ZE:1;
+ unsigned char PE3ZE:1;
+ unsigned char :4;
+ } BIT;
+ } POECR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char P3CZEA:1;
+ unsigned char P2CZEA:1;
+ unsigned char P1CZEA:1;
+ unsigned char :1;
+ } BIT;
+ } POECR2;
+ char wk1[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char OSTSTE:1;
+ unsigned char :2;
+ unsigned char OSTSTF:1;
+ unsigned char :3;
+ } BIT;
+ } ICSR3;
+};
+
+struct st_port {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL0:1;
+ unsigned char PSEL1:1;
+ unsigned char :1;
+ unsigned char PSEL3:1;
+ unsigned char :1;
+ unsigned char PSEL5:1;
+ unsigned char :2;
+ } BIT;
+ } PSRB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char PSEL6:1;
+ unsigned char PSEL7:1;
+ } BIT;
+ } PSRA;
+};
+
+struct st_port0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PCR;
+};
+
+struct st_port1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PMR;
+ char wk3[33];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR1;
+ char wk4[61];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR1;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char :5;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char :5;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char :5;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :3;
+ } BIT;
+ } ODR0;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char :5;
+ } BIT;
+ } PCR;
+};
+
+struct st_port4 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PMR;
+};
+
+struct st_port5 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char :2;
+ } BIT;
+ } PCR;
+};
+
+struct st_porta {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PMR;
+ char wk3[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :3;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :3;
+ } BIT;
+ } ODR1;
+ char wk4[52];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PMR;
+ char wk3[42];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :3;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR1;
+ char wk4[51];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PMR;
+ char wk3[43];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR1;
+ char wk4[50];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porte {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PMR;
+ char wk3[45];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ } BIT;
+ } ODR1;
+ char wk4[48];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0:1;
+ unsigned char B1:1;
+ unsigned char B2:1;
+ unsigned char B3:1;
+ unsigned char B4:1;
+ unsigned char B5:1;
+ unsigned char B6:1;
+ unsigned char B7:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_riic {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SDAI:1;
+ unsigned char SCLI:1;
+ unsigned char SDAO:1;
+ unsigned char SCLO:1;
+ unsigned char SOWP:1;
+ unsigned char CLO:1;
+ unsigned char IICRST:1;
+ unsigned char ICE:1;
+ } BIT;
+ } ICCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ST:1;
+ unsigned char RS:1;
+ unsigned char SP:1;
+ unsigned char :1;
+ unsigned char TRS:1;
+ unsigned char MST:1;
+ unsigned char BBSY:1;
+ } BIT;
+ } ICCR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BC:3;
+ unsigned char BCWP:1;
+ unsigned char CKS:3;
+ unsigned char MTWP:1;
+ } BIT;
+ } ICMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TMOS:1;
+ unsigned char TMOL:1;
+ unsigned char TMOH:1;
+ unsigned char TMWE:1;
+ unsigned char SDDL:3;
+ unsigned char DLCS:1;
+ } BIT;
+ } ICMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NF:2;
+ unsigned char ACKBR:1;
+ unsigned char ACKBT:1;
+ unsigned char ACKWP:1;
+ unsigned char RDRFS:1;
+ unsigned char WAIT:1;
+ unsigned char SMBS:1;
+ } BIT;
+ } ICMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TMOE:1;
+ unsigned char MALE:1;
+ unsigned char NALE:1;
+ unsigned char SALE:1;
+ unsigned char NACKE:1;
+ unsigned char NFE:1;
+ unsigned char SCLE:1;
+ unsigned char :1;
+ } BIT;
+ } ICFER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SAR0E:1;
+ unsigned char SAR1E:1;
+ unsigned char SAR2E:1;
+ unsigned char GCAE:1;
+ unsigned char :1;
+ unsigned char DIDE:1;
+ unsigned char :1;
+ unsigned char HOAE:1;
+ } BIT;
+ } ICSER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TMOIE:1;
+ unsigned char ALIE:1;
+ unsigned char STIE:1;
+ unsigned char SPIE:1;
+ unsigned char NAKIE:1;
+ unsigned char RIE:1;
+ unsigned char TEIE:1;
+ unsigned char TIE:1;
+ } BIT;
+ } ICIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char AAS0:1;
+ unsigned char AAS1:1;
+ unsigned char AAS2:1;
+ unsigned char GCA:1;
+ unsigned char :1;
+ unsigned char DID:1;
+ unsigned char :1;
+ unsigned char HOA:1;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TMOF:1;
+ unsigned char AL:1;
+ unsigned char START:1;
+ unsigned char STOP:1;
+ unsigned char NACKF:1;
+ unsigned char RDRF:1;
+ unsigned char TEND:1;
+ unsigned char TDRE:1;
+ } BIT;
+ } ICSR2;
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA0:1;
+ unsigned char SVA:7;
+ } BIT;
+ } SARL0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTL;
+ };
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FS:1;
+ unsigned char SVA:2;
+ unsigned char :5;
+ } BIT;
+ } SARU0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTH;
+ };
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA0:1;
+ unsigned char SVA:7;
+ } BIT;
+ } SARL1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FS:1;
+ unsigned char SVA:2;
+ unsigned char :5;
+ } BIT;
+ } SARU1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA0:1;
+ unsigned char SVA:7;
+ } BIT;
+ } SARL2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FS:1;
+ unsigned char SVA:2;
+ unsigned char :5;
+ } BIT;
+ } SARU2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BRL:5;
+ unsigned char :3;
+ } BIT;
+ } ICBRL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BRH:5;
+ unsigned char :3;
+ } BIT;
+ } ICBRH;
+ unsigned char ICDRT;
+ unsigned char ICDRR;
+};
+
+struct st_rspi {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPMS:1;
+ unsigned char TXMD:1;
+ unsigned char MODFEN:1;
+ unsigned char MSTR:1;
+ unsigned char SPEIE:1;
+ unsigned char SPTIE:1;
+ unsigned char SPE:1;
+ unsigned char SPRIE:1;
+ } BIT;
+ } SPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SSL0P:1;
+ unsigned char SSL1P:1;
+ unsigned char SSL2P:1;
+ unsigned char SSL3P:1;
+ unsigned char :4;
+ } BIT;
+ } SSLP;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPLP:1;
+ unsigned char SPLP2:1;
+ unsigned char :2;
+ unsigned char MOIFV:1;
+ unsigned char MOIFE:1;
+ unsigned char :2;
+ } BIT;
+ } SPPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OVRF:1;
+ unsigned char IDLNF:1;
+ unsigned char MODF:1;
+ unsigned char PERF:1;
+ unsigned char :4;
+ } BIT;
+ } SPSR;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned short H;
+ } WORD;
+ } SPDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPSLN:3;
+ unsigned char :5;
+ } BIT;
+ } SPSCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPCP:3;
+ unsigned char :1;
+ unsigned char SPECM:3;
+ unsigned char :1;
+ } BIT;
+ } SPSSR;
+ unsigned char SPBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPFC:2;
+ unsigned char :2;
+ unsigned char SPRDTD:1;
+ unsigned char SPLW:1;
+ unsigned char :2;
+ } BIT;
+ } SPDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SCKDL:3;
+ unsigned char :5;
+ } BIT;
+ } SPCKD;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SLNDL:3;
+ unsigned char :5;
+ } BIT;
+ } SSLND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPNDL:3;
+ unsigned char :5;
+ } BIT;
+ } SPND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPPE:1;
+ unsigned char SPOE:1;
+ unsigned char SPIIE:1;
+ unsigned char PTE:1;
+ unsigned char :4;
+ } BIT;
+ } SPCR2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD5;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD6;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CPHA:1;
+ unsigned short CPOL:1;
+ unsigned short BRDV:2;
+ unsigned short SSLA:3;
+ unsigned short SSLKP:1;
+ unsigned short SPB:4;
+ unsigned short LSBF:1;
+ unsigned short SPNDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SCKDEN:1;
+ } BIT;
+ } SPCMD7;
+};
+
+struct st_rtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char F64HZ:1;
+ unsigned char F32HZ:1;
+ unsigned char F16HZ:1;
+ unsigned char F8HZ:1;
+ unsigned char F4HZ:1;
+ unsigned char F2HZ:1;
+ unsigned char F1HZ:1;
+ unsigned char :1;
+ } BIT;
+ } R64CNT;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SEC1:4;
+ unsigned char SEC10:3;
+ unsigned char :1;
+ } BIT;
+ } RSECCNT;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MIN1:4;
+ unsigned char MIN10:3;
+ unsigned char :1;
+ } BIT;
+ } RMINCNT;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HR1:4;
+ unsigned char HR10:2;
+ unsigned char PM:1;
+ unsigned char :1;
+ } BIT;
+ } RHRCNT;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DAYW:3;
+ unsigned char :5;
+ } BIT;
+ } RWKCNT;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DATE1:4;
+ unsigned char DATE10:2;
+ unsigned char :2;
+ } BIT;
+ } RDAYCNT;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MON1:4;
+ unsigned char MON10:1;
+ unsigned char :3;
+ } BIT;
+ } RMONCNT;
+ char wk6[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short YR1:4;
+ unsigned short YR10:4;
+ unsigned short :8;
+ } BIT;
+ } RYRCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SEC1:4;
+ unsigned char SEC10:3;
+ unsigned char ENB:1;
+ } BIT;
+ } RSECAR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MIN1:4;
+ unsigned char MIN10:3;
+ unsigned char ENB:1;
+ } BIT;
+ } RMINAR;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HR1:4;
+ unsigned char HR10:2;
+ unsigned char PM:1;
+ unsigned char ENB:1;
+ } BIT;
+ } RHRAR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DAYW:3;
+ unsigned char :4;
+ unsigned char ENB:1;
+ } BIT;
+ } RWKAR;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DATE1:4;
+ unsigned char DATE10:2;
+ unsigned char :1;
+ unsigned char ENB:1;
+ } BIT;
+ } RDAYAR;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MON1:4;
+ unsigned char MON10:1;
+ unsigned char :2;
+ unsigned char ENB:1;
+ } BIT;
+ } RMONAR;
+ char wk12[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short YR1:4;
+ unsigned short YR10:4;
+ unsigned short :8;
+ } BIT;
+ } RYRAR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ENB:1;
+ } BIT;
+ } RYRAREN;
+ char wk13[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char AIE:1;
+ unsigned char CIE:1;
+ unsigned char PIE:1;
+ unsigned char RTCOS:1;
+ unsigned char PES:4;
+ } BIT;
+ } RCR1;
+ char wk14[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char START:1;
+ unsigned char RESET:1;
+ unsigned char ADJ30:1;
+ unsigned char RTCOE:1;
+ unsigned char AADJE:1;
+ unsigned char AADJP:1;
+ unsigned char HR24:1;
+ unsigned char CNTMD:1;
+ } BIT;
+ } RCR2;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RTCEN:1;
+ unsigned char RTCDV:2;
+ unsigned char :5;
+ } BIT;
+ } RCR3;
+ char wk16[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ADJ:6;
+ unsigned char PMADJ:2;
+ } BIT;
+ } RADJ;
+};
+
+struct st_rtcb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT0;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT1;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT3;
+ char wk3[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT0AR;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT1AR;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT2AR;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT3AR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT0AER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT1AER;
+ char wk9[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ENB:8;
+ unsigned short :8;
+ } BIT;
+ } BCNT2AER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT3AER;
+};
+
+struct st_s12ad {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DBLANS:5;
+ unsigned short :1;
+ unsigned short GBADIE:1;
+ unsigned short DBLE:1;
+ unsigned short EXTRG:1;
+ unsigned short TRGE:1;
+ unsigned short ADHSC:1;
+ unsigned short :1;
+ unsigned short ADIE:1;
+ unsigned short ADCS:2;
+ unsigned short ADST:1;
+ } BIT;
+ } ADCSR;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSA0:1;
+ unsigned short ANSA1:1;
+ unsigned short ANSA2:1;
+ unsigned short ANSA3:1;
+ unsigned short ANSA4:1;
+ unsigned short :1;
+ unsigned short ANSA6:1;
+ unsigned short :1;
+ unsigned short ANSA8:1;
+ unsigned short ANSA9:1;
+ unsigned short ANSA10:1;
+ unsigned short ANSA11:1;
+ unsigned short ANSA12:1;
+ unsigned short ANSA13:1;
+ unsigned short ANSA14:1;
+ unsigned short ANSA15:1;
+ } BIT;
+ } ADANSA;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADS0:1;
+ unsigned short ADS1:1;
+ unsigned short ADS2:1;
+ unsigned short ADS3:1;
+ unsigned short ADS4:1;
+ unsigned short :1;
+ unsigned short ADS6:1;
+ unsigned short :1;
+ unsigned short ADS8:1;
+ unsigned short ADS9:1;
+ unsigned short ADS10:1;
+ unsigned short ADS11:1;
+ unsigned short ADS12:1;
+ unsigned short ADS13:1;
+ unsigned short ADS14:1;
+ unsigned short ADS15:1;
+ } BIT;
+ } ADADS;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ADC:2;
+ unsigned char :6;
+ } BIT;
+ } ADADC;
+ char wk3[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ACE:1;
+ unsigned short :9;
+ unsigned short ADRFMT:1;
+ } BIT;
+ } ADCER;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TRSB:4;
+ unsigned short :4;
+ unsigned short TRSA:4;
+ unsigned short :4;
+ } BIT;
+ } ADSTRGR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :1;
+ unsigned short OCSAD:1;
+ unsigned short :6;
+ unsigned short TSS:1;
+ unsigned short OCS:1;
+ unsigned short :6;
+ } BIT;
+ } ADEXICR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSB0:1;
+ unsigned short ANSB1:1;
+ unsigned short ANSB2:1;
+ unsigned short ANSB3:1;
+ unsigned short ANSB4:1;
+ unsigned short :1;
+ unsigned short ANSB6:1;
+ unsigned short :1;
+ unsigned short ANSB8:1;
+ unsigned short ANSB9:1;
+ unsigned short ANSB10:1;
+ unsigned short ANSB11:1;
+ unsigned short ANSB12:1;
+ unsigned short ANSB13:1;
+ unsigned short ANSB14:1;
+ unsigned short ANSB15:1;
+ } BIT;
+ } ADANSB;
+ char wk4[2];
+ unsigned short ADDBLDR;
+ unsigned short ADTSDR;
+ unsigned short ADOCDR;
+ char wk5[2];
+ unsigned short ADDR0;
+ unsigned short ADDR1;
+ unsigned short ADDR2;
+ unsigned short ADDR3;
+ unsigned short ADDR4;
+ char wk6[2];
+ unsigned short ADDR6;
+ char wk7[2];
+ unsigned short ADDR8;
+ unsigned short ADDR9;
+ unsigned short ADDR10;
+ unsigned short ADDR11;
+ unsigned short ADDR12;
+ unsigned short ADDR13;
+ unsigned short ADDR14;
+ unsigned short ADDR15;
+ char wk8[32];
+ unsigned char ADSSTR0;
+ unsigned char ADSSTRL;
+ char wk9[14];
+ unsigned char ADSSTRT;
+ unsigned char ADSSTRO;
+ char wk10[1];
+ unsigned char ADSSTR1;
+ unsigned char ADSSTR2;
+ unsigned char ADSSTR3;
+ unsigned char ADSSTR4;
+ char wk11[1];
+ unsigned char ADSSTR6;
+};
+
+struct st_sci1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKS:2;
+ unsigned char MP:1;
+ unsigned char STOP:1;
+ unsigned char PM:1;
+ unsigned char PE:1;
+ unsigned char CHR:1;
+ unsigned char CM:1;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKE:2;
+ unsigned char TEIE:1;
+ unsigned char MPIE:1;
+ unsigned char RE:1;
+ unsigned char TE:1;
+ unsigned char RIE:1;
+ unsigned char TIE:1;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MPBT:1;
+ unsigned char MPB:1;
+ unsigned char TEND:1;
+ unsigned char PER:1;
+ unsigned char FER:1;
+ unsigned char ORER:1;
+ unsigned char :2;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SMIF:1;
+ unsigned char :1;
+ unsigned char SINV:1;
+ unsigned char SDIR:1;
+ unsigned char :3;
+ unsigned char BCP2:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char ABCS:1;
+ unsigned char NFEN:1;
+ unsigned char :1;
+ unsigned char RXDESEL:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFCS:3;
+ unsigned char :5;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICM:1;
+ unsigned char :2;
+ unsigned char IICDL:5;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICINTM:1;
+ unsigned char IICCSC:1;
+ unsigned char :3;
+ unsigned char IICACKT:1;
+ unsigned char :2;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSTAREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICSTIF:1;
+ unsigned char IICSDAS:2;
+ unsigned char IICSCLS:2;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICACKR:1;
+ unsigned char :7;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SSE:1;
+ unsigned char CTSE:1;
+ unsigned char MSS:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char CKPOL:1;
+ unsigned char CKPH:1;
+ } BIT;
+ } SPMR;
+};
+
+struct st_sci12 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKS:2;
+ unsigned char MP:1;
+ unsigned char STOP:1;
+ unsigned char PM:1;
+ unsigned char PE:1;
+ unsigned char CHR:1;
+ unsigned char CM:1;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKE:2;
+ unsigned char TEIE:1;
+ unsigned char MPIE:1;
+ unsigned char RE:1;
+ unsigned char TE:1;
+ unsigned char RIE:1;
+ unsigned char TIE:1;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MPBT:1;
+ unsigned char MPB:1;
+ unsigned char TEND:1;
+ unsigned char PER:1;
+ unsigned char FER:1;
+ unsigned char ORER:1;
+ unsigned char :2;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SMIF:1;
+ unsigned char :1;
+ unsigned char SINV:1;
+ unsigned char SDIR:1;
+ unsigned char :3;
+ unsigned char BCP2:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char ABCS:1;
+ unsigned char NFEN:1;
+ unsigned char :1;
+ unsigned char RXDESEL:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char NFCS:3;
+ unsigned char :5;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICM:1;
+ unsigned char :2;
+ unsigned char IICDL:5;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICINTM:1;
+ unsigned char IICCSC:1;
+ unsigned char :3;
+ unsigned char IICACKT:1;
+ unsigned char :2;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSTAREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICSTIF:1;
+ unsigned char IICSDAS:2;
+ unsigned char IICSCLS:2;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICACKR:1;
+ unsigned char :7;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SSE:1;
+ unsigned char CTSE:1;
+ unsigned char MSS:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char CKPOL:1;
+ unsigned char CKPH:1;
+ } BIT;
+ } SPMR;
+ char wk0[18];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ESME:1;
+ unsigned char :7;
+ } BIT;
+ } ESMER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SFSF:1;
+ unsigned char RXDSF:1;
+ unsigned char BRME:1;
+ unsigned char :4;
+ } BIT;
+ } CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BFE:1;
+ unsigned char CF0RE:1;
+ unsigned char CF1DS:2;
+ unsigned char PIBE:1;
+ unsigned char PIBS:3;
+ } BIT;
+ } CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DFCS:3;
+ unsigned char :1;
+ unsigned char BCCS:2;
+ unsigned char RTS:2;
+ } BIT;
+ } CR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SDST:1;
+ unsigned char :7;
+ } BIT;
+ } CR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TXDXPS:1;
+ unsigned char RXDXPS:1;
+ unsigned char :2;
+ unsigned char SHARPS:1;
+ unsigned char :3;
+ } BIT;
+ } PCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BFDIE:1;
+ unsigned char CF0MIE:1;
+ unsigned char CF1MIE:1;
+ unsigned char PIBDIE:1;
+ unsigned char BCDIE:1;
+ unsigned char AEDIE:1;
+ unsigned char :2;
+ } BIT;
+ } ICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BFDF:1;
+ unsigned char CF0MF:1;
+ unsigned char CF1MF:1;
+ unsigned char PIBDF:1;
+ unsigned char BCDF:1;
+ unsigned char AEDF:1;
+ unsigned char :2;
+ } BIT;
+ } STR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BFDCL:1;
+ unsigned char CF0MCL:1;
+ unsigned char CF1MCL:1;
+ unsigned char PIBDCL:1;
+ unsigned char BCDCL:1;
+ unsigned char AEDCL:1;
+ unsigned char :2;
+ } BIT;
+ } STCR;
+ unsigned char CF0DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF0CE0:1;
+ unsigned char CF0CE1:1;
+ unsigned char CF0CE2:1;
+ unsigned char CF0CE3:1;
+ unsigned char CF0CE4:1;
+ unsigned char CF0CE5:1;
+ unsigned char CF0CE6:1;
+ unsigned char CF0CE7:1;
+ } BIT;
+ } CF0CR;
+ unsigned char CF0RR;
+ unsigned char PCF1DR;
+ unsigned char SCF1DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF1CE0:1;
+ unsigned char CF1CE1:1;
+ unsigned char CF1CE2:1;
+ unsigned char CF1CE3:1;
+ unsigned char CF1CE4:1;
+ unsigned char CF1CE5:1;
+ unsigned char CF1CE6:1;
+ unsigned char CF1CE7:1;
+ } BIT;
+ } CF1CR;
+ unsigned char CF1RR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCST:1;
+ unsigned char :7;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TOMS:2;
+ unsigned char :1;
+ unsigned char TWRC:1;
+ unsigned char TCSS:3;
+ unsigned char :1;
+ } BIT;
+ } TMR;
+ unsigned char TPRE;
+ unsigned char TCNT;
+};
+
+struct st_smci {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKS:2;
+ unsigned char BCP:2;
+ unsigned char PM:1;
+ unsigned char PE:1;
+ unsigned char BLK:1;
+ unsigned char GM:1;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKE:2;
+ unsigned char TEIE:1;
+ unsigned char MPIE:1;
+ unsigned char RE:1;
+ unsigned char TE:1;
+ unsigned char RIE:1;
+ unsigned char TIE:1;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MPBT:1;
+ unsigned char MPB:1;
+ unsigned char TEND:1;
+ unsigned char PER:1;
+ unsigned char ERS:1;
+ unsigned char ORER:1;
+ unsigned char :2;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SMIF:1;
+ unsigned char :1;
+ unsigned char SINV:1;
+ unsigned char SDIR:1;
+ unsigned char :3;
+ unsigned char BCP2:1;
+ } BIT;
+ } SCMR;
+};
+
+struct st_system {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short MD:1;
+ unsigned short :15;
+ } BIT;
+ } MDMONR;
+ char wk0[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RAME:1;
+ unsigned short :15;
+ } BIT;
+ } SYSCR1;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short SSBY:1;
+ } BIT;
+ } SBYCR;
+ char wk2[2];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :9;
+ unsigned long MSTPA9:1;
+ unsigned long :5;
+ unsigned long MSTPA15:1;
+ unsigned long :1;
+ unsigned long MSTPA17:1;
+ unsigned long :1;
+ unsigned long MSTPA19:1;
+ unsigned long :8;
+ unsigned long MSTPA28:1;
+ unsigned long :3;
+ } BIT;
+ } MSTPCRA;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :4;
+ unsigned long MSTPB4:1;
+ unsigned long :1;
+ unsigned long MSTPB6:1;
+ unsigned long :2;
+ unsigned long MSTPB9:1;
+ unsigned long :7;
+ unsigned long MSTPB17:1;
+ unsigned long :1;
+ unsigned long MSTPB19:1;
+ unsigned long :1;
+ unsigned long MSTPB21:1;
+ unsigned long :1;
+ unsigned long MSTPB23:1;
+ unsigned long :2;
+ unsigned long MSTPB26:1;
+ unsigned long :3;
+ unsigned long MSTPB30:1;
+ unsigned long :1;
+ } BIT;
+ } MSTPCRB;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long MSTPC0:1;
+ unsigned long :18;
+ unsigned long MSTPC19:1;
+ unsigned long :11;
+ unsigned long DSLPE:1;
+ } BIT;
+ } MSTPCRC;
+ char wk3[4];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long PCKD:4;
+ unsigned long :4;
+ unsigned long PCKB:4;
+ unsigned long :12;
+ unsigned long ICK:4;
+ unsigned long FCK:4;
+ } BIT;
+ } SCKCR;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CKSEL:3;
+ unsigned short :5;
+ } BIT;
+ } SCKCR3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PLIDIV:2;
+ unsigned short :6;
+ unsigned short STC:6;
+ unsigned short :2;
+ } BIT;
+ } PLLCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PLLEN:1;
+ unsigned char :7;
+ } BIT;
+ } PLLCR2;
+ char wk5[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MOSTP:1;
+ unsigned char :7;
+ } BIT;
+ } MOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SOSTP:1;
+ unsigned char :7;
+ } BIT;
+ } SOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LCSTP:1;
+ unsigned char :7;
+ } BIT;
+ } LOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ILCSTP:1;
+ unsigned char :7;
+ } BIT;
+ } ILOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HCSTP:1;
+ unsigned char :7;
+ } BIT;
+ } HOCOCR;
+ char wk6[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MOOVF:1;
+ unsigned char :1;
+ unsigned char PLOVF:1;
+ unsigned char HCOVF:1;
+ unsigned char :4;
+ } BIT;
+ } OSCOVFSR;
+ char wk7[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CKOSEL:3;
+ unsigned short :1;
+ unsigned short CKODIV:3;
+ unsigned short CKOSTP:1;
+ } BIT;
+ } CKOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OSTDIE:1;
+ unsigned char :6;
+ unsigned char OSTDE:1;
+ } BIT;
+ } OSTDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OSTDF:1;
+ unsigned char :7;
+ } BIT;
+ } OSTDSR;
+ char wk8[94];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OPCM:3;
+ unsigned char :1;
+ unsigned char OPCMTSF:1;
+ unsigned char :3;
+ } BIT;
+ } OPCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTCKSEL:3;
+ unsigned char :4;
+ unsigned char RSTCKEN:1;
+ } BIT;
+ } RSTCKCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MSTS:5;
+ unsigned char :3;
+ } BIT;
+ } MOSCWTCR;
+ char wk9[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SOPCM:1;
+ unsigned char :3;
+ unsigned char SOPCMTSF:1;
+ unsigned char :3;
+ } BIT;
+ } SOPCCR;
+ char wk10[21];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IWDTRF:1;
+ unsigned char :1;
+ unsigned char SWRF:1;
+ unsigned char :5;
+ } BIT;
+ } RSTSR2;
+ char wk11[1];
+ unsigned short SWRR;
+ char wk12[28];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1IDTSEL:2;
+ unsigned char LVD1IRQSEL:1;
+ unsigned char :5;
+ } BIT;
+ } LVD1CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1DET:1;
+ unsigned char LVD1MON:1;
+ unsigned char :6;
+ } BIT;
+ } LVD1SR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD2IDTSEL:2;
+ unsigned char LVD2IRQSEL:1;
+ unsigned char :5;
+ } BIT;
+ } LVD2CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD2DET:1;
+ unsigned char LVD2MON:1;
+ unsigned char :6;
+ } BIT;
+ } LVD2SR;
+ char wk13[794];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PRC0:1;
+ unsigned short PRC1:1;
+ unsigned short :1;
+ unsigned short PRC3:1;
+ unsigned short :4;
+ unsigned short PRKEY:8;
+ } BIT;
+ } PRCR;
+ char wk14[48784];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PORF:1;
+ unsigned char :1;
+ unsigned char LVD1RF:1;
+ unsigned char LVD2RF:1;
+ unsigned char :4;
+ } BIT;
+ } RSTSR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CWSF:1;
+ unsigned char :7;
+ } BIT;
+ } RSTSR1;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MODRV21:1;
+ unsigned char MOSEL:1;
+ unsigned char :1;
+ } BIT;
+ } MOFCR;
+ char wk16[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char EXVCCINP2:1;
+ unsigned char :1;
+ unsigned char LVD1E:1;
+ unsigned char LVD2E:1;
+ unsigned char :1;
+ } BIT;
+ } LVCMPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1LVL:4;
+ unsigned char LVD2LVL:2;
+ unsigned char :2;
+ } BIT;
+ } LVDLVLR;
+ char wk17[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1RIE:1;
+ unsigned char :1;
+ unsigned char LVD1CMPE:1;
+ unsigned char :3;
+ unsigned char LVD1RI:1;
+ unsigned char LVD1RN:1;
+ } BIT;
+ } LVD1CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD2RIE:1;
+ unsigned char :1;
+ unsigned char LVD2CMPE:1;
+ unsigned char :3;
+ unsigned char LVD2RI:1;
+ unsigned char LVD2RN:1;
+ } BIT;
+ } LVD2CR0;
+};
+
+struct st_usb {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short USBE:1;
+ unsigned short :3;
+ unsigned short DPRPU:1;
+ unsigned short DRPD:1;
+ unsigned short DCFM:1;
+ unsigned short :1;
+ unsigned short CNEN:1;
+ unsigned short :1;
+ unsigned short SCKE:1;
+ unsigned short :5;
+ } BIT;
+ } SYSCFG;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short LNST:2;
+ unsigned short IDMON:1;
+ unsigned short :3;
+ unsigned short HTACT:1;
+ unsigned short :7;
+ unsigned short OVCMON:2;
+ } BIT;
+ } SYSSTS0;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RHST:3;
+ unsigned short :1;
+ unsigned short UACT:1;
+ unsigned short RESUME:1;
+ unsigned short USBRST:1;
+ unsigned short RWUPE:1;
+ unsigned short WKUP:1;
+ unsigned short VBUSEN:1;
+ unsigned short EXICEN:1;
+ unsigned short HNPBTOA:1;
+ unsigned short :4;
+ } BIT;
+ } DVSTCTR0;
+ char wk2[10];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } CFIFO;
+ char wk3[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D0FIFO;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D1FIFO;
+ char wk5[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CURPIPE:4;
+ unsigned short :1;
+ unsigned short ISEL:1;
+ unsigned short :2;
+ unsigned short BIGEND:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :3;
+ unsigned short REW:1;
+ unsigned short RCNT:1;
+ } BIT;
+ } CFIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DTLN:9;
+ unsigned short :4;
+ unsigned short FRDY:1;
+ unsigned short BCLR:1;
+ unsigned short BVAL:1;
+ } BIT;
+ } CFIFOCTR;
+ char wk6[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CURPIPE:4;
+ unsigned short :4;
+ unsigned short BIGEND:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short DREQE:1;
+ unsigned short DCLRM:1;
+ unsigned short REW:1;
+ unsigned short RCNT:1;
+ } BIT;
+ } D0FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DTLN:9;
+ unsigned short :4;
+ unsigned short FRDY:1;
+ unsigned short BCLR:1;
+ unsigned short BVAL:1;
+ } BIT;
+ } D0FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CURPIPE:4;
+ unsigned short :4;
+ unsigned short BIGEND:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short DREQE:1;
+ unsigned short DCLRM:1;
+ unsigned short REW:1;
+ unsigned short RCNT:1;
+ } BIT;
+ } D1FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DTLN:9;
+ unsigned short :4;
+ unsigned short FRDY:1;
+ unsigned short BCLR:1;
+ unsigned short BVAL:1;
+ } BIT;
+ } D1FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BRDYE:1;
+ unsigned short NRDYE:1;
+ unsigned short BEMPE:1;
+ unsigned short CTRE:1;
+ unsigned short DVSE:1;
+ unsigned short SOFE:1;
+ unsigned short RSME:1;
+ unsigned short VBSE:1;
+ } BIT;
+ } INTENB0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PDDETINTE0:1;
+ unsigned short :3;
+ unsigned short SACKE:1;
+ unsigned short SIGNE:1;
+ unsigned short EOFERRE:1;
+ unsigned short :4;
+ unsigned short ATTCHE:1;
+ unsigned short DTCHE:1;
+ unsigned short :1;
+ unsigned short BCHGE:1;
+ unsigned short OVRCRE:1;
+ } BIT;
+ } INTENB1;
+ char wk7[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPE0BRDYE:1;
+ unsigned short PIPE1BRDYE:1;
+ unsigned short PIPE2BRDYE:1;
+ unsigned short PIPE3BRDYE:1;
+ unsigned short PIPE4BRDYE:1;
+ unsigned short PIPE5BRDYE:1;
+ unsigned short PIPE6BRDYE:1;
+ unsigned short PIPE7BRDYE:1;
+ unsigned short PIPE8BRDYE:1;
+ unsigned short PIPE9BRDYE:1;
+ unsigned short :6;
+ } BIT;
+ } BRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPE0NRDYE:1;
+ unsigned short PIPE1NRDYE:1;
+ unsigned short PIPE2NRDYE:1;
+ unsigned short PIPE3NRDYE:1;
+ unsigned short PIPE4NRDYE:1;
+ unsigned short PIPE5NRDYE:1;
+ unsigned short PIPE6NRDYE:1;
+ unsigned short PIPE7NRDYE:1;
+ unsigned short PIPE8NRDYE:1;
+ unsigned short PIPE9NRDYE:1;
+ unsigned short :6;
+ } BIT;
+ } NRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPE0BEMPE:1;
+ unsigned short PIPE1BEMPE:1;
+ unsigned short PIPE2BEMPE:1;
+ unsigned short PIPE3BEMPE:1;
+ unsigned short PIPE4BEMPE:1;
+ unsigned short PIPE5BEMPE:1;
+ unsigned short PIPE6BEMPE:1;
+ unsigned short PIPE7BEMPE:1;
+ unsigned short PIPE8BEMPE:1;
+ unsigned short PIPE9BEMPE:1;
+ unsigned short :6;
+ } BIT;
+ } BEMPENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4; /* FIXME: Double check pad bits here*/
+ unsigned short EDGESTS:1;
+ unsigned short :1;
+ unsigned short BRDYM:1;
+ unsigned short :1;
+ unsigned short TRNENSEL:1;
+ unsigned short :7;
+ } BIT;
+ } SOFCFG;
+ char wk8[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CTSQ:3;
+ unsigned short VALID:1;
+ unsigned short DVSQ:3;
+ unsigned short VBSTS:1;
+ unsigned short BRDY:1;
+ unsigned short NRDY:1;
+ unsigned short BEMP:1;
+ unsigned short CTRT:1;
+ unsigned short DVST:1;
+ unsigned short SOFR:1;
+ unsigned short RESM:1;
+ unsigned short VBINT:1;
+ } BIT;
+ } INTSTS0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PDDETINT0:1;
+ unsigned short :3;
+ unsigned short SACK:1;
+ unsigned short SIGN:1;
+ unsigned short EOFERR:1;
+ unsigned short :4;
+ unsigned short ATTCH:1;
+ unsigned short DTCH:1;
+ unsigned short :1;
+ unsigned short BCHG:1;
+ unsigned short OVRCR:1;
+ } BIT;
+ } INTSTS1;
+ char wk9[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPE0BRDY:1;
+ unsigned short PIPE1BRDY:1;
+ unsigned short PIPE2BRDY:1;
+ unsigned short PIPE3BRDY:1;
+ unsigned short PIPE4BRDY:1;
+ unsigned short PIPE5BRDY:1;
+ unsigned short PIPE6BRDY:1;
+ unsigned short PIPE7BRDY:1;
+ unsigned short PIPE8BRDY:1;
+ unsigned short PIPE9BRDY:1;
+ unsigned short :6;
+ } BIT;
+ } BRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPE0NRDY:1;
+ unsigned short PIPE1NRDY:1;
+ unsigned short PIPE2NRDY:1;
+ unsigned short PIPE3NRDY:1;
+ unsigned short PIPE4NRDY:1;
+ unsigned short PIPE5NRDY:1;
+ unsigned short PIPE6NRDY:1;
+ unsigned short PIPE7NRDY:1;
+ unsigned short PIPE8NRDY:1;
+ unsigned short PIPE9NRDY:1;
+ unsigned short :6;
+ } BIT;
+ } NRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPE0BEMP:1;
+ unsigned short PIPE1BEMP:1;
+ unsigned short PIPE2BEMP:1;
+ unsigned short PIPE3BEMP:1;
+ unsigned short PIPE4BEMP:1;
+ unsigned short PIPE5BEMP:1;
+ unsigned short PIPE6BEMP:1;
+ unsigned short PIPE7BEMP:1;
+ unsigned short PIPE8BEMP:1;
+ unsigned short PIPE9BEMP:1;
+ unsigned short :6;
+ } BIT;
+ } BEMPSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FRNM:11;
+ unsigned short :3;
+ unsigned short CRCE:1;
+ unsigned short OVRN:1;
+ } BIT;
+ } FRMNUM;
+ char wk10[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BMREQUESTTYPE:8;
+ unsigned short BREQUEST:8;
+ } BIT;
+ } USBREQ;
+ unsigned short USBVAL;
+ unsigned short USBINDX;
+ unsigned short USBLENG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4; /* FIXME: Double check pad bits here. */
+ unsigned short DIR:1;
+ unsigned short :2;
+ unsigned short SHTNAK:1;
+ unsigned short :8;
+ } BIT;
+ } DCPCFG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short MXPS:7;
+ unsigned short :5;
+ unsigned short DEVSEL:4;
+ } BIT;
+ } DCPMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short CCPL:1;
+ unsigned short :2;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short :2;
+ unsigned short SUREQCLR:1;
+ unsigned short :2;
+ unsigned short SUREQ:1;
+ unsigned short BSTS:1;
+ } BIT;
+ } DCPCTR;
+ char wk11[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PIPESEL:4;
+ unsigned short :12;
+ } BIT;
+ } PIPESEL;
+ char wk12[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short EPNUM:4;
+ unsigned short DIR:1;
+ unsigned short :2;
+ unsigned short SHTNAK:1;
+ unsigned short :1;
+ unsigned short DBLB:1;
+ unsigned short BFRE:1;
+ unsigned short :3;
+ unsigned short TYPE:2;
+ } BIT;
+ } PIPECFG;
+ char wk13[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short MXPS:9;
+ unsigned short :3;
+ unsigned short DEVSEL:4;
+ } BIT;
+ } PIPEMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short IITV:3;
+ unsigned short :9;
+ unsigned short IFIS:1;
+ unsigned short :3;
+ } BIT;
+ } PIPEPERI;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short ATREPM:1;
+ unsigned short :3;
+ unsigned short INBUFM:1;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE1CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short ATREPM:1;
+ unsigned short :3;
+ unsigned short INBUFM:1;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE2CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short ATREPM:1;
+ unsigned short :3;
+ unsigned short INBUFM:1;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE3CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short ATREPM:1;
+ unsigned short :3;
+ unsigned short INBUFM:1;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE4CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short ATREPM:1;
+ unsigned short :3;
+ unsigned short INBUFM:1;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE5CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short :5;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE6CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short :5;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE7CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short :5;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE8CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PID:2;
+ unsigned short :3;
+ unsigned short PBUSY:1;
+ unsigned short SQMON:1;
+ unsigned short SQSET:1;
+ unsigned short SQCLR:1;
+ unsigned short ACLRM:1;
+ unsigned short :5;
+ unsigned short BSTS:1;
+ } BIT;
+ } PIPE9CTR;
+ char wk14[14];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TRCLR:1;
+ unsigned short TRENB:1;
+ unsigned short :6;
+ } BIT;
+ } PIPE1TRE;
+ unsigned short PIPE1TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TRCLR:1;
+ unsigned short TRENB:1;
+ unsigned short :6;
+ } BIT;
+ } PIPE2TRE;
+ unsigned short PIPE2TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TRCLR:1;
+ unsigned short TRENB:1;
+ unsigned short :6;
+ } BIT;
+ } PIPE3TRE;
+ unsigned short PIPE3TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TRCLR:1;
+ unsigned short TRENB:1;
+ unsigned short :6;
+ } BIT;
+ } PIPE4TRE;
+ unsigned short PIPE4TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TRCLR:1;
+ unsigned short TRENB:1;
+ unsigned short :6;
+ } BIT;
+ } PIPE5TRE;
+ unsigned short PIPE5TRN;
+ char wk15[12];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RPDME0:1;
+ unsigned short IDPSRCE0:1;
+ unsigned short IDMSINKE0:1;
+ unsigned short VDPSRCE0:1;
+ unsigned short IDPSINKE0:1;
+ unsigned short VDMSRCE0:1;
+ unsigned short DCPMODE0:1;
+ unsigned short BATCHGE0:1;
+ unsigned short CHGDETSTS0:1;
+ unsigned short PDDETSTS0:1;
+ unsigned short :6;
+ } BIT;
+ } USBBCCTRL0;
+ char wk16[26];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VDDUSBE:1;
+ unsigned short :6;
+ unsigned short VBRPDCUT:1;
+ unsigned short :8;
+ } BIT;
+ } USBMC;
+ char wk17[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6; /* FIXME: Double check pad bits here. */
+ unsigned short USBSPD:2;
+ unsigned short :8;
+ } BIT;
+ } DEVADD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6; /* FIXME: Double check pad bits here. */
+ unsigned short USBSPD:2;
+ unsigned short :8;
+ } BIT;
+ } DEVADD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6; /* FIXME: Double check pad bits here. */
+ unsigned short USBSPD:2;
+ unsigned short :8;
+ } BIT;
+ } DEVADD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6; /* FIXME: Double check pad bits here. */
+ unsigned short USBSPD:2;
+ unsigned short :8;
+ } BIT;
+ } DEVADD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6; /* FIXME: Double check pad bits here. */
+ unsigned short USBSPD:2;
+ unsigned short :8;
+ } BIT;
+ } DEVADD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6; /* FIXME: Double check pad bits here. */
+ unsigned short USBSPD:2;
+ unsigned short :8;
+ } BIT;
+ } DEVADD5;
+};
+
+#elif __RX_BIG_ENDIAN__ /*Big endian*/
+
+struct st_bsc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char STSCLR:1;
+ } BIT;
+ } BERCLR;
+ char wk0[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IGAEN:1;
+ } BIT;
+ } BEREN;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MST:3;
+ unsigned char :3;
+ unsigned char IA:1;
+ } BIT;
+ } BERSR1;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADDR:13;
+ } BIT;
+ } BERSR2;
+ char wk3[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short BPFB:2;
+ unsigned short :2;
+ unsigned short BPGB:2;
+ unsigned short BPIB:2;
+ unsigned short BPRO:2;
+ unsigned short BPRA:2;
+ } BIT;
+ } BUSPRI;
+};
+
+struct st_cac {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char CFME:1;
+ } BIT;
+ } CACR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char EDGES:2;
+ unsigned char TCSS:2;
+ unsigned char FMCS:3;
+ unsigned char CACREFE:1;
+ } BIT;
+ } CACR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DFS:2;
+ unsigned char RCDS:2;
+ unsigned char RSCS:3;
+ unsigned char RPS:1;
+ } BIT;
+ } CACR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char OVFFCL:1;
+ unsigned char MENDFCL:1;
+ unsigned char FERRFCL:1;
+ unsigned char :1;
+ unsigned char OVFIE:1;
+ unsigned char MENDIE:1;
+ unsigned char FERRIE:1;
+ } BIT;
+ } CAICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char OVFF:1;
+ unsigned char MENDF:1;
+ unsigned char FERRF:1;
+ } BIT;
+ } CASTR;
+ char wk0[1];
+ unsigned short CAULVR;
+ unsigned short CALLVR;
+ unsigned short CACNTBR;
+};
+
+struct st_cmt {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :14;
+ unsigned short STR1:1;
+ unsigned short STR0:1;
+ } BIT;
+ } CMSTR0;
+};
+
+struct st_cmt0 {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :9;
+ unsigned short CMIE:1;
+ unsigned short :4;
+ unsigned short CKS:2;
+ } BIT;
+ } CMCR;
+ unsigned short CMCNT;
+ unsigned short CMCOR;
+};
+
+struct st_crc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DORCLR:1;
+ unsigned char :4;
+ unsigned char LMS:1;
+ unsigned char GPS:2;
+ } BIT;
+ } CRCCR;
+ unsigned char CRCDIR;
+ unsigned short CRCDOR;
+};
+
+struct st_da {
+ unsigned short DADR0;
+ unsigned short DADR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DAOE1:1;
+ unsigned char DAOE0:1;
+ } BIT;
+ } DACR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DPSEL:1;
+ } BIT;
+ } DADPR;
+};
+
+struct st_doc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char DOPCFCL:1;
+ unsigned char DOPCF:1;
+ unsigned char DOPCIE:1;
+ unsigned char :1;
+ unsigned char DCSEL:1;
+ unsigned char OMS:2;
+ } BIT;
+ } DOCR;
+ char wk0[1];
+ unsigned short DODIR;
+ unsigned short DODSR;
+};
+
+struct st_dtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char RRS:1;
+ } BIT;
+ } DTCCR;
+ char wk0[3];
+ void *DTCVBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SHORT:1;
+ } BIT;
+ } DTCADMOD;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DTCST:1;
+ } BIT;
+ } DTCST;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ACT:1;
+ unsigned short :7;
+ unsigned short VECN:8;
+ } BIT;
+ } DTCSTS;
+};
+
+struct st_elc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELCON:1;
+ } BIT;
+ } ELCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELS:8;
+ } BIT;
+ } ELSR[26];
+ char wk0[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTU3MD:2;
+ unsigned char MTU2MD:2;
+ unsigned char MTU1MD:2;
+ } BIT;
+ } ELOPA;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char MTU4MD:2;
+ } BIT;
+ } ELOPB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char CMT1MD:2;
+ } BIT;
+ } ELOPC;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PGR7:1;
+ unsigned char PGR6:1;
+ unsigned char PGR5:1;
+ unsigned char PGR4:1;
+ unsigned char PGR3:1;
+ unsigned char PGR2:1;
+ unsigned char PGR1:1;
+ unsigned char PGR0:1;
+ } BIT;
+ } PGR1;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PGCO:3;
+ unsigned char :1;
+ unsigned char PGCOVE:1;
+ unsigned char PGCI:2;
+ } BIT;
+ } PGC1;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PDBF7:1;
+ unsigned char PDBF6:1;
+ unsigned char PDBF5:1;
+ unsigned char PDBF4:1;
+ unsigned char PDBF3:1;
+ unsigned char PDBF2:1;
+ unsigned char PDBF1:1;
+ unsigned char PDBF0:1;
+ } BIT;
+ } PDBF1;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSM:2;
+ unsigned char PSP:2;
+ unsigned char PSB:3;
+ } BIT;
+ } PEL0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSM:2;
+ unsigned char PSP:2;
+ unsigned char PSB:3;
+ } BIT;
+ } PEL1;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char WI:1;
+ unsigned char WE:1;
+ unsigned char :5;
+ unsigned char SEG:1;
+ } BIT;
+ } ELSEGR;
+};
+
+struct st_flash {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DFLEN:1;
+ } BIT;
+ } DFLCTL;
+};
+
+struct st_icu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IR:1;
+ } BIT;
+ } IR[250];
+ char wk0[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DTCE:1;
+ } BIT;
+ } DTCER[249];
+ char wk1[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IEN7:1;
+ unsigned char IEN6:1;
+ unsigned char IEN5:1;
+ unsigned char IEN4:1;
+ unsigned char IEN3:1;
+ unsigned char IEN2:1;
+ unsigned char IEN1:1;
+ unsigned char IEN0:1;
+ } BIT;
+ } IER[32];
+ char wk2[192];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SWINT:1;
+ } BIT;
+ } SWINTR;
+ char wk3[15];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FIEN:1;
+ unsigned short :7;
+ unsigned short FVCT:8;
+ } BIT;
+ } FIR;
+ char wk4[14];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char IPR:4;
+ } BIT;
+ } IPR[250];
+ char wk5[262];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char IRQMD:2;
+ } BIT;
+ } IRQCR[8];
+ char wk6[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FLTEN7:1;
+ unsigned char FLTEN6:1;
+ unsigned char FLTEN5:1;
+ unsigned char FLTEN4:1;
+ unsigned char FLTEN3:1;
+ unsigned char FLTEN2:1;
+ unsigned char FLTEN1:1;
+ unsigned char FLTEN0:1;
+ } BIT;
+ } IRQFLTE0;
+ char wk7[3];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FCLKSEL7:2;
+ unsigned short FCLKSEL6:2;
+ unsigned short FCLKSEL5:2;
+ unsigned short FCLKSEL4:2;
+ unsigned short FCLKSEL3:2;
+ unsigned short FCLKSEL2:2;
+ unsigned short FCLKSEL1:2;
+ unsigned short FCLKSEL0:2;
+ } BIT;
+ } IRQFLTC0;
+ char wk8[106];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2ST:1;
+ unsigned char LVD1ST:1;
+ unsigned char IWDTST:1;
+ unsigned char :1;
+ unsigned char OSTST:1;
+ unsigned char NMIST:1;
+ } BIT;
+ } NMISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2EN:1;
+ unsigned char LVD1EN:1;
+ unsigned char IWDTEN:1;
+ unsigned char :1;
+ unsigned char OSTEN:1;
+ unsigned char NMIEN:1;
+ } BIT;
+ } NMIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2CLR:1;
+ unsigned char LVD1CLR:1;
+ unsigned char IWDTCLR:1;
+ unsigned char :1;
+ unsigned char OSTCLR:1;
+ unsigned char NMICLR:1;
+ } BIT;
+ } NMICLR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char NMIMD:1;
+ } BIT;
+ } NMICR;
+ char wk9[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char NFLTEN:1;
+ } BIT;
+ } NMIFLTE;
+ char wk10[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char NFCLKSEL:2;
+ } BIT;
+ } NMIFLTC;
+};
+
+struct st_iwdt {
+ unsigned char IWDTRR;
+ char wk0[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :2;
+ unsigned short RPSS:2;
+ unsigned short :2;
+ unsigned short RPES:2;
+ unsigned short CKS:4;
+ unsigned short :2;
+ unsigned short TOPS:2;
+ } BIT;
+ } IWDTCR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short REFEF:1;
+ unsigned short UNDFF:1;
+ unsigned short CNTVAL:14;
+ } BIT;
+ } IWDTSR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTIRQS:1;
+ } BIT;
+ } IWDTRCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SLCSTP:1;
+ } BIT;
+ } IWDTCSTPR;
+};
+
+struct st_mpc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0WI:1;
+ unsigned char PFSWE:1;
+ } BIT;
+ } PWPR;
+ char wk0[35];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P03PFS;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P05PFS;
+ char wk2[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P14PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P15PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P16PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P17PFS;
+ char wk3[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P26PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P27PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P30PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P31PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P32PFS;
+ char wk4[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ } BIT;
+ } P35PFS;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P40PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P41PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P42PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P43PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P44PFS;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P46PFS;
+ char wk7[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P54PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P55PFS;
+ char wk8[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA1PFS;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA4PFS;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA6PFS;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB1PFS;
+ char wk12[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB3PFS;
+ char wk13[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB7PFS;
+ char wk14[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC7PFS;
+ char wk15[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE1PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE7PFS;
+ char wk16[30];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ7PFS;
+};
+
+struct st_mtu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char OE4D:1;
+ unsigned char OE4C:1;
+ unsigned char OE3D:1;
+ unsigned char OE4B:1;
+ unsigned char OE4A:1;
+ unsigned char OE3B:1;
+ } BIT;
+ } TOER;
+ char wk0[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char BDC:1;
+ unsigned char N:1;
+ unsigned char P:1;
+ unsigned char FB:1;
+ unsigned char WF:1;
+ unsigned char VF:1;
+ unsigned char UF:1;
+ } BIT;
+ } TGCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSYE:1;
+ unsigned char :2;
+ unsigned char TOCL:1;
+ unsigned char TOCS:1;
+ unsigned char OLSN:1;
+ unsigned char OLSP:1;
+ } BIT;
+ } TOCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BF:2;
+ unsigned char OLS3N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS1P:1;
+ } BIT;
+ } TOCR2;
+ char wk1[4];
+ unsigned short TCDR;
+ unsigned short TDDR;
+ char wk2[8];
+ unsigned short TCNTS;
+ unsigned short TCBR;
+ char wk3[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char T3AEN:1;
+ unsigned char T3ACOR:3;
+ unsigned char T4VEN:1;
+ unsigned char T4VCOR:3;
+ } BIT;
+ } TITCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char T3ACNT:3;
+ unsigned char :1;
+ unsigned char T4VCNT:3;
+ } BIT;
+ } TITCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char BTE:2;
+ } BIT;
+ } TBTER;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char TDER:1;
+ } BIT;
+ } TDER;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char OLS3N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS1P:1;
+ } BIT;
+ } TOLBR;
+ char wk6[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCE:1;
+ unsigned char :6;
+ unsigned char WRE:1;
+ } BIT;
+ } TWCR;
+ char wk7[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CST4:1;
+ unsigned char CST3:1;
+ unsigned char :3;
+ unsigned char CST2:1;
+ unsigned char CST1:1;
+ unsigned char CST0:1;
+ } BIT;
+ } TSTR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SYNC4:1;
+ unsigned char SYNC3:1;
+ unsigned char :3;
+ unsigned char SYNC2:1;
+ unsigned char SYNC1:1;
+ unsigned char SYNC0:1;
+ } BIT;
+ } TSYR;
+ char wk8[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char RWE:1;
+ } BIT;
+ } TRWER;
+};
+
+struct st_mtu0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk0[111];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char BFE:1;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk1[16];
+ unsigned short TGRE;
+ unsigned short TGRF;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TGIEF:1;
+ unsigned char TGIEE:1;
+ } BIT;
+ } TIER2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+};
+
+struct st_mtu1 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk1[238];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char CCLR:2;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIOR;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :1;
+ unsigned char TCIEU:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk3[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char I2BE:1;
+ unsigned char I2AE:1;
+ unsigned char I1BE:1;
+ unsigned char I1AE:1;
+ } BIT;
+ } TICCR;
+};
+
+struct st_mtu2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk0[365];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char CCLR:2;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIOR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :1;
+ unsigned char TCIEU:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+};
+
+struct st_mtu3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ char wk3[7];
+ unsigned short TCNT;
+ char wk4[6];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk5[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk6[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+ char wk8[90];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu4 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char TTGE2:1;
+ unsigned char :1;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ char wk4[8];
+ unsigned short TCNT;
+ char wk5[8];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk6[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk8[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+ char wk9[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BF:2;
+ unsigned short :6;
+ unsigned short UT4AE:1;
+ unsigned short DT4AE:1;
+ unsigned short UT4BE:1;
+ unsigned short DT4BE:1;
+ unsigned short ITA3AE:1;
+ unsigned short ITA4VE:1;
+ unsigned short ITB3AE:1;
+ unsigned short ITB4VE:1;
+ } BIT;
+ } TADCR;
+ char wk10[2];
+ unsigned short TADCORA;
+ unsigned short TADCORB;
+ unsigned short TADCOBRA;
+ unsigned short TADCOBRB;
+ char wk11[72];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu5 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char :1;
+ unsigned char NFWEN:1;
+ unsigned char NFVEN:1;
+ unsigned char NFUEN:1;
+ } BIT;
+ } NFCR;
+ char wk1[490];
+ unsigned short TCNTU;
+ unsigned short TGRU;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRU;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORU;
+ char wk3[9];
+ unsigned short TCNTV;
+ unsigned short TGRV;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRV;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORV;
+ char wk5[9];
+ unsigned short TCNTW;
+ unsigned short TGRW;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRW;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORW;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TGIE5U:1;
+ unsigned char TGIE5V:1;
+ unsigned char TGIE5W:1;
+ } BIT;
+ } TIER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char CSTU5:1;
+ unsigned char CSTV5:1;
+ unsigned char CSTW5:1;
+ } BIT;
+ } TSTR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char CMPCLR5U:1;
+ unsigned char CMPCLR5V:1;
+ unsigned char CMPCLR5W:1;
+ } BIT;
+ } TCNTCMPCLR;
+};
+
+struct st_poe {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char POE3F:1;
+ unsigned char POE2F:1;
+ unsigned char POE1F:1;
+ unsigned char POE0F:1;
+ unsigned char :3;
+ unsigned char PIE1:1;
+ unsigned char POE3M:2;
+ unsigned char POE2M:2;
+ unsigned char POE1M:2;
+ unsigned char POE0M:2;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char OSF1:1;
+ unsigned char :5;
+ unsigned char OCE1:1;
+ unsigned char OIE1:1;
+ } BIT;
+ } OCSR1;
+ char wk0[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char POE8F:1;
+ unsigned char :2;
+ unsigned char POE8E:1;
+ unsigned char PIE2:1;
+ unsigned char :6;
+ unsigned char POE8M:2;
+ } BIT;
+ } ICSR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char CH0HIZ:1;
+ unsigned char CH34HIZ:1;
+ } BIT;
+ } SPOER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PE3ZE:1;
+ unsigned char PE2ZE:1;
+ unsigned char PE1ZE:1;
+ unsigned char PE0ZE:1;
+ } BIT;
+ } POECR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char P1CZEA:1;
+ unsigned char P2CZEA:1;
+ unsigned char P3CZEA:1;
+ } BIT;
+ } POECR2;
+ char wk1[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char OSTSTF:1;
+ unsigned char :2;
+ unsigned char OSTSTE:1;
+ } BIT;
+ } ICSR3;
+};
+
+struct st_port {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char PSEL5:1;
+ unsigned char :1;
+ unsigned char PSEL3:1;
+ unsigned char :1;
+ unsigned char PSEL1:1;
+ unsigned char PSEL0:1;
+ } BIT;
+ } PSRB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL7:1;
+ unsigned char PSEL6:1;
+ } BIT;
+ } PSRA;
+};
+
+struct st_port0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PMR;
+ char wk3[33];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[61];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ } BIT;
+ } ODR1;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port4 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+};
+
+struct st_port5 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porta {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :3;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :3;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[52];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[42];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :3;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ } BIT;
+ } ODR1;
+ char wk4[51];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PMR;
+ char wk3[43];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[50];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porte {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[45];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[48];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_riic {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ICE:1;
+ unsigned char IICRST:1;
+ unsigned char CLO:1;
+ unsigned char SOWP:1;
+ unsigned char SCLO:1;
+ unsigned char SDAO:1;
+ unsigned char SCLI:1;
+ unsigned char SDAI:1;
+ } BIT;
+ } ICCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BBSY:1;
+ unsigned char MST:1;
+ unsigned char TRS:1;
+ unsigned char :1;
+ unsigned char SP:1;
+ unsigned char RS:1;
+ unsigned char ST:1;
+ } BIT;
+ } ICCR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTWP:1;
+ unsigned char CKS:3;
+ unsigned char BCWP:1;
+ unsigned char BC:3;
+ } BIT;
+ } ICMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DLCS:1;
+ unsigned char SDDL:3;
+ unsigned char TMWE:1;
+ unsigned char TMOH:1;
+ unsigned char TMOL:1;
+ unsigned char TMOS:1;
+ } BIT;
+ } ICMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SMBS:1;
+ unsigned char WAIT:1;
+ unsigned char RDRFS:1;
+ unsigned char ACKWP:1;
+ unsigned char ACKBT:1;
+ unsigned char ACKBR:1;
+ unsigned char NF:2;
+ } BIT;
+ } ICMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SCLE:1;
+ unsigned char NFE:1;
+ unsigned char NACKE:1;
+ unsigned char SALE:1;
+ unsigned char NALE:1;
+ unsigned char MALE:1;
+ unsigned char TMOE:1;
+ } BIT;
+ } ICFER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HOAE:1;
+ unsigned char :1;
+ unsigned char DIDE:1;
+ unsigned char :1;
+ unsigned char GCAE:1;
+ unsigned char SAR2E:1;
+ unsigned char SAR1E:1;
+ unsigned char SAR0E:1;
+ } BIT;
+ } ICSER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char TEIE:1;
+ unsigned char RIE:1;
+ unsigned char NAKIE:1;
+ unsigned char SPIE:1;
+ unsigned char STIE:1;
+ unsigned char ALIE:1;
+ unsigned char TMOIE:1;
+ } BIT;
+ } ICIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HOA:1;
+ unsigned char :1;
+ unsigned char DID:1;
+ unsigned char :1;
+ unsigned char GCA:1;
+ unsigned char AAS2:1;
+ unsigned char AAS1:1;
+ unsigned char AAS0:1;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TDRE:1;
+ unsigned char TEND:1;
+ unsigned char RDRF:1;
+ unsigned char NACKF:1;
+ unsigned char STOP:1;
+ unsigned char START:1;
+ unsigned char AL:1;
+ unsigned char TMOF:1;
+ } BIT;
+ } ICSR2;
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTL;
+ };
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTH;
+ };
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char BRL:5;
+ } BIT;
+ } ICBRL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char BRH:5;
+ } BIT;
+ } ICBRH;
+ unsigned char ICDRT;
+ unsigned char ICDRR;
+};
+
+struct st_rspi {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPRIE:1;
+ unsigned char SPE:1;
+ unsigned char SPTIE:1;
+ unsigned char SPEIE:1;
+ unsigned char MSTR:1;
+ unsigned char MODFEN:1;
+ unsigned char TXMD:1;
+ unsigned char SPMS:1;
+ } BIT;
+ } SPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char SSL3P:1;
+ unsigned char SSL2P:1;
+ unsigned char SSL1P:1;
+ unsigned char SSL0P:1;
+ } BIT;
+ } SSLP;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char MOIFE:1;
+ unsigned char MOIFV:1;
+ unsigned char :2;
+ unsigned char SPLP2:1;
+ unsigned char SPLP:1;
+ } BIT;
+ } SPPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PERF:1;
+ unsigned char MODF:1;
+ unsigned char IDLNF:1;
+ unsigned char OVRF:1;
+ } BIT;
+ } SPSR;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned short H;
+ } WORD;
+ } SPDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SPSLN:3;
+ } BIT;
+ } SPSCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SPECM:3;
+ unsigned char :1;
+ unsigned char SPCP:3;
+ } BIT;
+ } SPSSR;
+ unsigned char SPBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char SPLW:1;
+ unsigned char SPRDTD:1;
+ unsigned char :2;
+ unsigned char SPFC:2;
+ } BIT;
+ } SPDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SCKDL:3;
+ } BIT;
+ } SPCKD;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SLNDL:3;
+ } BIT;
+ } SSLND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SPNDL:3;
+ } BIT;
+ } SPND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PTE:1;
+ unsigned char SPIIE:1;
+ unsigned char SPOE:1;
+ unsigned char SPPE:1;
+ } BIT;
+ } SPCR2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD5;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD6;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD7;
+};
+
+struct st_rtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char F1HZ:1;
+ unsigned char F2HZ:1;
+ unsigned char F4HZ:1;
+ unsigned char F8HZ:1;
+ unsigned char F16HZ:1;
+ unsigned char F32HZ:1;
+ unsigned char F64HZ:1;
+ } BIT;
+ } R64CNT;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SEC10:3;
+ unsigned char SEC1:4;
+ } BIT;
+ } RSECCNT;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MIN10:3;
+ unsigned char MIN1:4;
+ } BIT;
+ } RMINCNT;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PM:1;
+ unsigned char HR10:2;
+ unsigned char HR1:4;
+ } BIT;
+ } RHRCNT;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char DAYW:3;
+ } BIT;
+ } RWKCNT;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char DATE10:2;
+ unsigned char DATE1:4;
+ } BIT;
+ } RDAYCNT;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char MON10:1;
+ unsigned char MON1:4;
+ } BIT;
+ } RMONCNT;
+ char wk6[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short YR10:4;
+ unsigned short YR1:4;
+ } BIT;
+ } RYRCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char SEC10:3;
+ unsigned char SEC1:4;
+ } BIT;
+ } RSECAR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char MIN10:3;
+ unsigned char MIN1:4;
+ } BIT;
+ } RMINAR;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char PM:1;
+ unsigned char HR10:2;
+ unsigned char HR1:4;
+ } BIT;
+ } RHRAR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :4;
+ unsigned char DAYW:3;
+ } BIT;
+ } RWKAR;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :1;
+ unsigned char DATE10:2;
+ unsigned char DATE1:4;
+ } BIT;
+ } RDAYAR;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :2;
+ unsigned char MON10:1;
+ unsigned char MON1:4;
+ } BIT;
+ } RMONAR;
+ char wk12[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short YR10:4;
+ unsigned short YR1:4;
+ } BIT;
+ } RYRAR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ } BIT;
+ } RYRAREN;
+ char wk13[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PES:4;
+ unsigned char RTCOS:1;
+ unsigned char PIE:1;
+ unsigned char CIE:1;
+ unsigned char AIE:1;
+ } BIT;
+ } RCR1;
+ char wk14[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CNTMD:1;
+ unsigned char HR24:1;
+ unsigned char AADJP:1;
+ unsigned char AADJE:1;
+ unsigned char RTCOE:1;
+ unsigned char ADJ30:1;
+ unsigned char RESET:1;
+ unsigned char START:1;
+ } BIT;
+ } RCR2;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char RTCDV:2;
+ unsigned char RTCEN:1;
+ } BIT;
+ } RCR3;
+ char wk16[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PMADJ:2;
+ unsigned char ADJ:6;
+ } BIT;
+ } RADJ;
+};
+
+struct st_rtcb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT0;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT1;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT3;
+ char wk3[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT0AR;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT1AR;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT2AR;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT3AR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT0AER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT1AER;
+ char wk9[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short ENB:8;
+ } BIT;
+ } BCNT2AER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT3AER;
+};
+
+struct st_s12ad {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADST:1;
+ unsigned short ADCS:2;
+ unsigned short ADIE:1;
+ unsigned short :1;
+ unsigned short ADHSC:1;
+ unsigned short TRGE:1;
+ unsigned short EXTRG:1;
+ unsigned short DBLE:1;
+ unsigned short GBADIE:1;
+ unsigned short :1;
+ unsigned short DBLANS:5;
+ } BIT;
+ } ADCSR;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSA15:1;
+ unsigned short ANSA14:1;
+ unsigned short ANSA13:1;
+ unsigned short ANSA12:1;
+ unsigned short ANSA11:1;
+ unsigned short ANSA10:1;
+ unsigned short ANSA9:1;
+ unsigned short ANSA8:1;
+ unsigned short :1;
+ unsigned short ANSA6:1;
+ unsigned short :1;
+ unsigned short ANSA4:1;
+ unsigned short ANSA3:1;
+ unsigned short ANSA2:1;
+ unsigned short ANSA1:1;
+ unsigned short ANSA0:1;
+ } BIT;
+ } ADANSA;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADS15:1;
+ unsigned short ADS14:1;
+ unsigned short ADS13:1;
+ unsigned short ADS12:1;
+ unsigned short ADS11:1;
+ unsigned short ADS10:1;
+ unsigned short ADS9:1;
+ unsigned short ADS8:1;
+ unsigned short :1;
+ unsigned short ADS6:1;
+ unsigned short :1;
+ unsigned short ADS4:1;
+ unsigned short ADS3:1;
+ unsigned short ADS2:1;
+ unsigned short ADS1:1;
+ unsigned short ADS0:1;
+ } BIT;
+ } ADADS;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char ADC:2;
+ } BIT;
+ } ADADC;
+ char wk3[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADRFMT:1;
+ unsigned short :9;
+ unsigned short ACE:1;
+ } BIT;
+ } ADCER;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short TRSA:4;
+ unsigned short :4;
+ unsigned short TRSB:4;
+ } BIT;
+ } ADSTRGR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short OCS:1;
+ unsigned short TSS:1;
+ unsigned short :6;
+ unsigned short OCSAD:1;
+ } BIT;
+ } ADEXICR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSB15:1;
+ unsigned short ANSB14:1;
+ unsigned short ANSB13:1;
+ unsigned short ANSB12:1;
+ unsigned short ANSB11:1;
+ unsigned short ANSB10:1;
+ unsigned short ANSB9:1;
+ unsigned short ANSB8:1;
+ unsigned short :1;
+ unsigned short ANSB6:1;
+ unsigned short :1;
+ unsigned short ANSB4:1;
+ unsigned short ANSB3:1;
+ unsigned short ANSB2:1;
+ unsigned short ANSB1:1;
+ unsigned short ANSB0:1;
+ } BIT;
+ } ADANSB;
+ char wk4[2];
+ unsigned short ADDBLDR;
+ unsigned short ADTSDR;
+ unsigned short ADOCDR;
+ char wk5[2];
+ unsigned short ADDR0;
+ unsigned short ADDR1;
+ unsigned short ADDR2;
+ unsigned short ADDR3;
+ unsigned short ADDR4;
+ char wk6[2];
+ unsigned short ADDR6;
+ char wk7[2];
+ unsigned short ADDR8;
+ unsigned short ADDR9;
+ unsigned short ADDR10;
+ unsigned short ADDR11;
+ unsigned short ADDR12;
+ unsigned short ADDR13;
+ unsigned short ADDR14;
+ unsigned short ADDR15;
+ char wk8[32];
+ unsigned char ADSSTR0;
+ unsigned char ADSSTRL;
+ char wk9[14];
+ unsigned char ADSSTRT;
+ unsigned char ADSSTRO;
+ char wk10[1];
+ unsigned char ADSSTR1;
+ unsigned char ADSSTR2;
+ unsigned char ADSSTR3;
+ unsigned char ADSSTR4;
+ char wk11[1];
+ unsigned char ADSSTR6;
+};
+
+struct st_sci1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CM:1;
+ unsigned char CHR:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char STOP:1;
+ unsigned char MP:1;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char FER:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RXDESEL:1;
+ unsigned char :1;
+ unsigned char NFEN:1;
+ unsigned char ABCS:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char NFCS:3;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICDL:5;
+ unsigned char :2;
+ unsigned char IICM:1;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char IICACKT:1;
+ unsigned char :3;
+ unsigned char IICCSC:1;
+ unsigned char IICINTM:1;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSCLS:2;
+ unsigned char IICSDAS:2;
+ unsigned char IICSTIF:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTAREQ:1;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IICACKR:1;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKPH:1;
+ unsigned char CKPOL:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char MSS:1;
+ unsigned char CTSE:1;
+ unsigned char SSE:1;
+ } BIT;
+ } SPMR;
+};
+
+struct st_sci12 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CM:1;
+ unsigned char CHR:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char STOP:1;
+ unsigned char MP:1;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char FER:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RXDESEL:1;
+ unsigned char :1;
+ unsigned char NFEN:1;
+ unsigned char ABCS:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char NFCS:3;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICDL:5;
+ unsigned char :2;
+ unsigned char IICM:1;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char IICACKT:1;
+ unsigned char :3;
+ unsigned char IICCSC:1;
+ unsigned char IICINTM:1;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSCLS:2;
+ unsigned char IICSDAS:2;
+ unsigned char IICSTIF:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTAREQ:1;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IICACKR:1;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKPH:1;
+ unsigned char CKPOL:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char MSS:1;
+ unsigned char CTSE:1;
+ unsigned char SSE:1;
+ } BIT;
+ } SPMR;
+ char wk0[18];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ESME:1;
+ } BIT;
+ } ESMER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char BRME:1;
+ unsigned char RXDSF:1;
+ unsigned char SFSF:1;
+ } BIT;
+ } CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PIBS:3;
+ unsigned char PIBE:1;
+ unsigned char CF1DS:2;
+ unsigned char CF0RE:1;
+ unsigned char BFE:1;
+ } BIT;
+ } CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RTS:2;
+ unsigned char BCCS:2;
+ unsigned char :1;
+ unsigned char DFCS:3;
+ } BIT;
+ } CR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SDST:1;
+ } BIT;
+ } CR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char SHARPS:1;
+ unsigned char :2;
+ unsigned char RXDXPS:1;
+ unsigned char TXDXPS:1;
+ } BIT;
+ } PCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDIE:1;
+ unsigned char BCDIE:1;
+ unsigned char PIBDIE:1;
+ unsigned char CF1MIE:1;
+ unsigned char CF0MIE:1;
+ unsigned char BFDIE:1;
+ } BIT;
+ } ICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDF:1;
+ unsigned char BCDF:1;
+ unsigned char PIBDF:1;
+ unsigned char CF1MF:1;
+ unsigned char CF0MF:1;
+ unsigned char BFDF:1;
+ } BIT;
+ } STR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDCL:1;
+ unsigned char BCDCL:1;
+ unsigned char PIBDCL:1;
+ unsigned char CF1MCL:1;
+ unsigned char CF0MCL:1;
+ unsigned char BFDCL:1;
+ } BIT;
+ } STCR;
+ unsigned char CF0DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF0CE7:1;
+ unsigned char CF0CE6:1;
+ unsigned char CF0CE5:1;
+ unsigned char CF0CE4:1;
+ unsigned char CF0CE3:1;
+ unsigned char CF0CE2:1;
+ unsigned char CF0CE1:1;
+ unsigned char CF0CE0:1;
+ } BIT;
+ } CF0CR;
+ unsigned char CF0RR;
+ unsigned char PCF1DR;
+ unsigned char SCF1DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF1CE7:1;
+ unsigned char CF1CE6:1;
+ unsigned char CF1CE5:1;
+ unsigned char CF1CE4:1;
+ unsigned char CF1CE3:1;
+ unsigned char CF1CE2:1;
+ unsigned char CF1CE1:1;
+ unsigned char CF1CE0:1;
+ } BIT;
+ } CF1CR;
+ unsigned char CF1RR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char TCST:1;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char TCSS:3;
+ unsigned char TWRC:1;
+ unsigned char :1;
+ unsigned char TOMS:2;
+ } BIT;
+ } TMR;
+ unsigned char TPRE;
+ unsigned char TCNT;
+};
+
+struct st_smci {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char GM:1;
+ unsigned char BLK:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char BCP:2;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char ERS:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+};
+
+struct st_system {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short MD:1;
+ } BIT;
+ } MDMONR;
+ char wk0[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short RAME:1;
+ } BIT;
+ } SYSCR1;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SSBY:1;
+ } BIT;
+ } SBYCR;
+ char wk2[2];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :3;
+ unsigned long MSTPA28:1;
+ unsigned long :8;
+ unsigned long MSTPA19:1;
+ unsigned long :1;
+ unsigned long MSTPA17:1;
+ unsigned long :1;
+ unsigned long MSTPA15:1;
+ unsigned long :5;
+ unsigned long MSTPA9:1;
+ } BIT;
+ } MSTPCRA;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :1;
+ unsigned long MSTPB30:1;
+ unsigned long :3;
+ unsigned long MSTPB26:1;
+ unsigned long :2;
+ unsigned long MSTPB23:1;
+ unsigned long :1;
+ unsigned long MSTPB21:1;
+ unsigned long :1;
+ unsigned long MSTPB19:1;
+ unsigned long :1;
+ unsigned long MSTPB17:1;
+ unsigned long :7;
+ unsigned long MSTPB9:1;
+ unsigned long :2;
+ unsigned long MSTPB6:1;
+ unsigned long :1;
+ unsigned long MSTPB4:1;
+ } BIT;
+ } MSTPCRB;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long DSLPE:1;
+ unsigned long :11;
+ unsigned long MSTPC19:1;
+ unsigned long :18;
+ unsigned long MSTPC0:1;
+ } BIT;
+ } MSTPCRC;
+ char wk3[4];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long FCK:4;
+ unsigned long ICK:4;
+ unsigned long :12;
+ unsigned long PCKB:4;
+ unsigned long :4;
+ unsigned long PCKD:4;
+ } BIT;
+ } SCKCR;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :5;
+ unsigned short CKSEL:3;
+ } BIT;
+ } SCKCR3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :2;
+ unsigned short STC:6;
+ unsigned short :6;
+ unsigned short PLIDIV:2;
+ } BIT;
+ } PLLCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char PLLEN:1;
+ } BIT;
+ } PLLCR2;
+ char wk5[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char MOSTP:1;
+ } BIT;
+ } MOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SOSTP:1;
+ } BIT;
+ } SOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char LCSTP:1;
+ } BIT;
+ } LOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ILCSTP:1;
+ } BIT;
+ } ILOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char HCSTP:1;
+ } BIT;
+ } HOCOCR;
+ char wk6[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char HCOVF:1;
+ unsigned char PLOVF:1;
+ unsigned char :1;
+ unsigned char MOOVF:1;
+ } BIT;
+ } OSCOVFSR;
+ char wk7[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CKOSTP:1;
+ unsigned short CKODIV:3;
+ unsigned short :1;
+ unsigned short CKOSEL:3;
+ } BIT;
+ } CKOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OSTDE:1;
+ unsigned char :6;
+ unsigned char OSTDIE:1;
+ } BIT;
+ } OSTDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char OSTDF:1;
+ } BIT;
+ } OSTDSR;
+ char wk8[94];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char OPCMTSF:1;
+ unsigned char :1;
+ unsigned char OPCM:3;
+ } BIT;
+ } OPCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTCKEN:1;
+ unsigned char :4;
+ unsigned char RSTCKSEL:3;
+ } BIT;
+ } RSTCKCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char MSTS:5;
+ } BIT;
+ } MOSCWTCR;
+ char wk9[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char SOPCMTSF:1;
+ unsigned char :3;
+ unsigned char SOPCM:1;
+ } BIT;
+ } SOPCCR;
+ char wk10[21];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SWRF:1;
+ unsigned char :1;
+ unsigned char IWDTRF:1;
+ } BIT;
+ } RSTSR2;
+ char wk11[1];
+ unsigned short SWRR;
+ char wk12[28];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char LVD1IRQSEL:1;
+ unsigned char LVD1IDTSEL:2;
+ } BIT;
+ } LVD1CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char LVD1MON:1;
+ unsigned char LVD1DET:1;
+ } BIT;
+ } LVD1SR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char LVD2IRQSEL:1;
+ unsigned char LVD2IDTSEL:2;
+ } BIT;
+ } LVD2CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char LVD2MON:1;
+ unsigned char LVD2DET:1;
+ } BIT;
+ } LVD2SR;
+ char wk13[794];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PRKEY:8;
+ unsigned short :4;
+ unsigned short PRC3:1;
+ unsigned short :1;
+ unsigned short PRC1:1;
+ unsigned short PRC0:1;
+ } BIT;
+ } PRCR;
+ char wk14[48784];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char LVD2RF:1;
+ unsigned char LVD1RF:1;
+ unsigned char :1;
+ unsigned char PORF:1;
+ } BIT;
+ } RSTSR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char CWSF:1;
+ } BIT;
+ } RSTSR1;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MOSEL:1;
+ unsigned char MODRV21:1;
+ } BIT;
+ } MOFCR;
+ char wk16[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char LVD2E:1;
+ unsigned char LVD1E:1;
+ unsigned char :1;
+ unsigned char EXVCCINP2:1;
+ } BIT;
+ } LVCMPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2LVL:2;
+ unsigned char LVD1LVL:4;
+ } BIT;
+ } LVDLVLR;
+ char wk17[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1RN:1;
+ unsigned char LVD1RI:1;
+ unsigned char :3;
+ unsigned char LVD1CMPE:1;
+ unsigned char :1;
+ unsigned char LVD1RIE:1;
+ } BIT;
+ } LVD1CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD2RN:1;
+ unsigned char LVD2RI:1;
+ unsigned char :3;
+ unsigned char LVD2CMPE:1;
+ unsigned char :1;
+ unsigned char LVD2RIE:1;
+ } BIT;
+ } LVD2CR0;
+};
+
+struct st_usb {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :5;
+ unsigned short SCKE:1;
+ unsigned short :1;
+ unsigned short CNEN:1;
+ unsigned short :1;
+ unsigned short DCFM:1;
+ unsigned short DRPD:1;
+ unsigned short DPRPU:1;
+ unsigned short :3;
+ unsigned short USBE:1;
+ } BIT;
+ } SYSCFG;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVCMON:2;
+ unsigned short :7;
+ unsigned short HTACT:1;
+ unsigned short :3;
+ unsigned short IDMON:1;
+ unsigned short LNST:2;
+ } BIT;
+ } SYSSTS0;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short HNPBTOA:1;
+ unsigned short EXICEN:1;
+ unsigned short VBUSEN:1;
+ unsigned short WKUP:1;
+ unsigned short RWUPE:1;
+ unsigned short USBRST:1;
+ unsigned short RESUME:1;
+ unsigned short UACT:1;
+ unsigned short :1;
+ unsigned short RHST:3;
+ } BIT;
+ } DVSTCTR0;
+ char wk2[10];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } CFIFO;
+ char wk3[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D0FIFO;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D1FIFO;
+ char wk5[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short :3;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :2;
+ unsigned short ISEL:1;
+ unsigned short :1;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } CFIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } CFIFOCTR;
+ char wk6[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short DCLRM:1;
+ unsigned short DREQE:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :4;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } D0FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } D0FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short DCLRM:1;
+ unsigned short DREQE:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :4;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } D1FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } D1FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VBSE:1;
+ unsigned short RSME:1;
+ unsigned short SOFE:1;
+ unsigned short DVSE:1;
+ unsigned short CTRE:1;
+ unsigned short BEMPE:1;
+ unsigned short NRDYE:1;
+ unsigned short BRDYE:1;
+ } BIT;
+ } INTENB0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRCRE:1;
+ unsigned short BCHGE:1;
+ unsigned short :1;
+ unsigned short DTCHE:1;
+ unsigned short ATTCHE:1;
+ unsigned short :4;
+ unsigned short EOFERRE:1;
+ unsigned short SIGNE:1;
+ unsigned short SACKE:1;
+ unsigned short :3;
+ unsigned short PDDETINTE0:1;
+ } BIT;
+ } INTENB1;
+ char wk7[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BRDYE:1;
+ unsigned short PIPE8BRDYE:1;
+ unsigned short PIPE7BRDYE:1;
+ unsigned short PIPE6BRDYE:1;
+ unsigned short PIPE5BRDYE:1;
+ unsigned short PIPE4BRDYE:1;
+ unsigned short PIPE3BRDYE:1;
+ unsigned short PIPE2BRDYE:1;
+ unsigned short PIPE1BRDYE:1;
+ unsigned short PIPE0BRDYE:1;
+ } BIT;
+ } BRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9NRDYE:1;
+ unsigned short PIPE8NRDYE:1;
+ unsigned short PIPE7NRDYE:1;
+ unsigned short PIPE6NRDYE:1;
+ unsigned short PIPE5NRDYE:1;
+ unsigned short PIPE4NRDYE:1;
+ unsigned short PIPE3NRDYE:1;
+ unsigned short PIPE2NRDYE:1;
+ unsigned short PIPE1NRDYE:1;
+ unsigned short PIPE0NRDYE:1;
+ } BIT;
+ } NRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BEMPE:1;
+ unsigned short PIPE8BEMPE:1;
+ unsigned short PIPE7BEMPE:1;
+ unsigned short PIPE6BEMPE:1;
+ unsigned short PIPE5BEMPE:1;
+ unsigned short PIPE4BEMPE:1;
+ unsigned short PIPE3BEMPE:1;
+ unsigned short PIPE2BEMPE:1;
+ unsigned short PIPE1BEMPE:1;
+ unsigned short PIPE0BEMPE:1;
+ } BIT;
+ } BEMPENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :7;
+ unsigned short TRNENSEL:1;
+ unsigned short :1;
+ unsigned short BRDYM:1;
+ unsigned short :1;
+ unsigned short EDGESTS:1;
+ } BIT;
+ } SOFCFG;
+ char wk8[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VBINT:1;
+ unsigned short RESM:1;
+ unsigned short SOFR:1;
+ unsigned short DVST:1;
+ unsigned short CTRT:1;
+ unsigned short BEMP:1;
+ unsigned short NRDY:1;
+ unsigned short BRDY:1;
+ unsigned short VBSTS:1;
+ unsigned short DVSQ:3;
+ unsigned short VALID:1;
+ unsigned short CTSQ:3;
+ } BIT;
+ } INTSTS0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRCR:1;
+ unsigned short BCHG:1;
+ unsigned short :1;
+ unsigned short DTCH:1;
+ unsigned short ATTCH:1;
+ unsigned short :4;
+ unsigned short EOFERR:1;
+ unsigned short SIGN:1;
+ unsigned short SACK:1;
+ unsigned short :3;
+ unsigned short PDDETINT0:1;
+ } BIT;
+ } INTSTS1;
+ char wk9[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BRDY:1;
+ unsigned short PIPE8BRDY:1;
+ unsigned short PIPE7BRDY:1;
+ unsigned short PIPE6BRDY:1;
+ unsigned short PIPE5BRDY:1;
+ unsigned short PIPE4BRDY:1;
+ unsigned short PIPE3BRDY:1;
+ unsigned short PIPE2BRDY:1;
+ unsigned short PIPE1BRDY:1;
+ unsigned short PIPE0BRDY:1;
+ } BIT;
+ } BRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9NRDY:1;
+ unsigned short PIPE8NRDY:1;
+ unsigned short PIPE7NRDY:1;
+ unsigned short PIPE6NRDY:1;
+ unsigned short PIPE5NRDY:1;
+ unsigned short PIPE4NRDY:1;
+ unsigned short PIPE3NRDY:1;
+ unsigned short PIPE2NRDY:1;
+ unsigned short PIPE1NRDY:1;
+ unsigned short PIPE0NRDY:1;
+ } BIT;
+ } NRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BEMP:1;
+ unsigned short PIPE8BEMP:1;
+ unsigned short PIPE7BEMP:1;
+ unsigned short PIPE6BEMP:1;
+ unsigned short PIPE5BEMP:1;
+ unsigned short PIPE4BEMP:1;
+ unsigned short PIPE3BEMP:1;
+ unsigned short PIPE2BEMP:1;
+ unsigned short PIPE1BEMP:1;
+ unsigned short PIPE0BEMP:1;
+ } BIT;
+ } BEMPSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRN:1;
+ unsigned short CRCE:1;
+ unsigned short :3;
+ unsigned short FRNM:11;
+ } BIT;
+ } FRMNUM;
+ char wk10[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BREQUEST:8;
+ unsigned short BMREQUESTTYPE:8;
+ } BIT;
+ } USBREQ;
+ unsigned short USBVAL;
+ unsigned short USBINDX;
+ unsigned short USBLENG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short SHTNAK:1;
+ unsigned short :2;
+ unsigned short DIR:1;
+ } BIT;
+ } DCPCFG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DEVSEL:4;
+ unsigned short :5;
+ unsigned short MXPS:7;
+ } BIT;
+ } DCPMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short SUREQ:1;
+ unsigned short :2;
+ unsigned short SUREQCLR:1;
+ unsigned short :2;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :2;
+ unsigned short CCPL:1;
+ unsigned short PID:2;
+ } BIT;
+ } DCPCTR;
+ char wk11[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :12;
+ unsigned short PIPESEL:4;
+ } BIT;
+ } PIPESEL;
+ char wk12[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TYPE:2;
+ unsigned short :3;
+ unsigned short BFRE:1;
+ unsigned short DBLB:1;
+ unsigned short :1;
+ unsigned short SHTNAK:1;
+ unsigned short :2;
+ unsigned short DIR:1;
+ unsigned short EPNUM:4;
+ } BIT;
+ } PIPECFG;
+ char wk13[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DEVSEL:4;
+ unsigned short :3;
+ unsigned short MXPS:9;
+ } BIT;
+ } PIPEMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :3;
+ unsigned short IFIS:1;
+ unsigned short :9;
+ unsigned short IITV:3;
+ } BIT;
+ } PIPEPERI;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE1CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE2CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE3CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE4CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE5CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE6CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE7CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE8CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE9CTR;
+ char wk14[14];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE1TRE;
+ unsigned short PIPE1TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE2TRE;
+ unsigned short PIPE2TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE3TRE;
+ unsigned short PIPE3TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE4TRE;
+ unsigned short PIPE4TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE5TRE;
+ unsigned short PIPE5TRN;
+ char wk15[12];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PDDETSTS0:1;
+ unsigned short CHGDETSTS0:1;
+ unsigned short BATCHGE0:1;
+ unsigned short DCPMODE0:1;
+ unsigned short VDMSRCE0:1;
+ unsigned short IDPSINKE0:1;
+ unsigned short VDPSRCE0:1;
+ unsigned short IDMSINKE0:1;
+ unsigned short IDPSRCE0:1;
+ unsigned short RPDME0:1;
+ } BIT;
+ } USBBCCTRL0;
+ char wk16[26];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short VBRPDCUT:1;
+ unsigned short :6;
+ unsigned short VDDUSBE:1;
+ } BIT;
+ } USBMC;
+ char wk17[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD5;
+};
+
+#endif /*endian */
+
+enum enum_ir {
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,
+IR_CMT0_CMI0,
+IR_CMT1_CMI1,
+IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF,
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,
+IR_DOC_DOPCF=57,
+IR_RTC_CUP=63,
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,
+IR_LVD_LVD1=88,IR_LVD_LVD2,
+IR_USB0_USBR0,
+IR_RTC_ALM=92,IR_RTC_PRD,
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,
+IR_ELC_ELSR18I=106,
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,
+IR_POE_OEI1=170,IR_POE_OEI2,
+IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,
+IR_SCI12_ERI12=238,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0
+};
+
+enum enum_dtce {
+DTCE_ICU_SWINT=27,
+DTCE_CMT0_CMI0,
+DTCE_CMT1_CMI1,
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,
+DTCE_ELC_ELSR18I=106,
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0
+};
+
+enum enum_ier {
+IER_BSC_BUSERR=0x02,
+IER_ICU_SWINT=0x03,
+IER_CMT0_CMI0=0x03,
+IER_CMT1_CMI1=0x03,
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,
+IER_DOC_DOPCF=0x07,
+IER_RTC_CUP=0x07,
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,
+IER_USB0_USBR0=0x0B,
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,
+IER_ELC_ELSR18I=0x0D,
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F
+};
+
+enum enum_ipr {
+IPR_BSC_BUSERR=0,
+IPR_ICU_SWINT=3,
+IPR_CMT0_CMI0=4,
+IPR_CMT1_CMI1=5,
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,
+IPR_DOC_DOPCF=57,
+IPR_RTC_CUP=63,
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,
+IPR_USB0_USBR0=90,
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,
+IPR_ELC_ELSR18I=106,
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249,
+IPR_BSC_=0,
+IPR_CMT0_=4,
+IPR_CMT1_=5,
+IPR_RSPI0_=44,
+IPR_DOC_=57,
+IPR_ELC_=106,
+IPR_MTU1_TGI=121,
+IPR_MTU1_TCI=123,
+IPR_MTU2_TGI=125,
+IPR_MTU2_TCI=127,
+IPR_MTU3_TGI=129,
+IPR_MTU4_TGI=134,
+IPR_MTU5_=139,
+IPR_MTU5_TGI=139,
+IPR_SCI1_=218,
+IPR_SCI5_=222
+};
+
+#define IEN_BSC_BUSERR IEN0
+#define IEN_ICU_SWINT IEN3
+#define IEN_CMT0_CMI0 IEN4
+#define IEN_CMT1_CMI1 IEN5
+#define IEN_CAC_FERRF IEN0
+#define IEN_CAC_MENDF IEN1
+#define IEN_CAC_OVFF IEN2
+#define IEN_USB0_D0FIFO0 IEN4
+#define IEN_USB0_D1FIFO0 IEN5
+#define IEN_USB0_USBI0 IEN6
+#define IEN_RSPI0_SPEI0 IEN4
+#define IEN_RSPI0_SPRI0 IEN5
+#define IEN_RSPI0_SPTI0 IEN6
+#define IEN_RSPI0_SPII0 IEN7
+#define IEN_DOC_DOPCF IEN1
+#define IEN_RTC_CUP IEN7
+#define IEN_ICU_IRQ0 IEN0
+#define IEN_ICU_IRQ1 IEN1
+#define IEN_ICU_IRQ2 IEN2
+#define IEN_ICU_IRQ3 IEN3
+#define IEN_ICU_IRQ4 IEN4
+#define IEN_ICU_IRQ5 IEN5
+#define IEN_ICU_IRQ6 IEN6
+#define IEN_ICU_IRQ7 IEN7
+#define IEN_LVD_LVD1 IEN0
+#define IEN_LVD_LVD2 IEN1
+#define IEN_USB0_USBR0 IEN2
+#define IEN_RTC_ALM IEN4
+#define IEN_RTC_PRD IEN5
+#define IEN_S12AD_S12ADI0 IEN6
+#define IEN_S12AD_GBADI IEN7
+#define IEN_ELC_ELSR18I IEN2
+#define IEN_MTU0_TGIA0 IEN2
+#define IEN_MTU0_TGIB0 IEN3
+#define IEN_MTU0_TGIC0 IEN4
+#define IEN_MTU0_TGID0 IEN5
+#define IEN_MTU0_TCIV0 IEN6
+#define IEN_MTU0_TGIE0 IEN7
+#define IEN_MTU0_TGIF0 IEN0
+#define IEN_MTU1_TGIA1 IEN1
+#define IEN_MTU1_TGIB1 IEN2
+#define IEN_MTU1_TCIV1 IEN3
+#define IEN_MTU1_TCIU1 IEN4
+#define IEN_MTU2_TGIA2 IEN5
+#define IEN_MTU2_TGIB2 IEN6
+#define IEN_MTU2_TCIV2 IEN7
+#define IEN_MTU2_TCIU2 IEN0
+#define IEN_MTU3_TGIA3 IEN1
+#define IEN_MTU3_TGIB3 IEN2
+#define IEN_MTU3_TGIC3 IEN3
+#define IEN_MTU3_TGID3 IEN4
+#define IEN_MTU3_TCIV3 IEN5
+#define IEN_MTU4_TGIA4 IEN6
+#define IEN_MTU4_TGIB4 IEN7
+#define IEN_MTU4_TGIC4 IEN0
+#define IEN_MTU4_TGID4 IEN1
+#define IEN_MTU4_TCIV4 IEN2
+#define IEN_MTU5_TGIU5 IEN3
+#define IEN_MTU5_TGIV5 IEN4
+#define IEN_MTU5_TGIW5 IEN5
+#define IEN_POE_OEI1 IEN2
+#define IEN_POE_OEI2 IEN3
+#define IEN_SCI1_ERI1 IEN2
+#define IEN_SCI1_RXI1 IEN3
+#define IEN_SCI1_TXI1 IEN4
+#define IEN_SCI1_TEI1 IEN5
+#define IEN_SCI5_ERI5 IEN6
+#define IEN_SCI5_RXI5 IEN7
+#define IEN_SCI5_TXI5 IEN0
+#define IEN_SCI5_TEI5 IEN1
+#define IEN_SCI12_ERI12 IEN6
+#define IEN_SCI12_RXI12 IEN7
+#define IEN_SCI12_TXI12 IEN0
+#define IEN_SCI12_TEI12 IEN1
+#define IEN_SCI12_SCIX0 IEN2
+#define IEN_SCI12_SCIX1 IEN3
+#define IEN_SCI12_SCIX2 IEN4
+#define IEN_SCI12_SCIX3 IEN5
+#define IEN_RIIC0_EEI0 IEN6
+#define IEN_RIIC0_RXI0 IEN7
+#define IEN_RIIC0_TXI0 IEN0
+#define IEN_RIIC0_TEI0 IEN1
+
+#define VECT_BSC_BUSERR 16
+#define VECT_ICU_SWINT 27
+#define VECT_CMT0_CMI0 28
+#define VECT_CMT1_CMI1 29
+#define VECT_CAC_FERRF 32
+#define VECT_CAC_MENDF 33
+#define VECT_CAC_OVFF 34
+#define VECT_USB0_D0FIFO0 36
+#define VECT_USB0_D1FIFO0 37
+#define VECT_USB0_USBI0 38
+#define VECT_RSPI0_SPEI0 44
+#define VECT_RSPI0_SPRI0 45
+#define VECT_RSPI0_SPTI0 46
+#define VECT_RSPI0_SPII0 47
+#define VECT_DOC_DOPCF 57
+#define VECT_RTC_CUP 63
+#define VECT_ICU_IRQ0 64
+#define VECT_ICU_IRQ1 65
+#define VECT_ICU_IRQ2 66
+#define VECT_ICU_IRQ3 67
+#define VECT_ICU_IRQ4 68
+#define VECT_ICU_IRQ5 69
+#define VECT_ICU_IRQ6 70
+#define VECT_ICU_IRQ7 71
+#define VECT_LVD_LVD1 88
+#define VECT_LVD_LVD2 89
+#define VECT_USB0_USBR0 90
+#define VECT_RTC_ALM 92
+#define VECT_RTC_PRD 93
+#define VECT_S12AD_S12ADI0 102
+#define VECT_S12AD_GBADI 103
+#define VECT_ELC_ELSR18I 106
+#define VECT_MTU0_TGIA0 114
+#define VECT_MTU0_TGIB0 115
+#define VECT_MTU0_TGIC0 116
+#define VECT_MTU0_TGID0 117
+#define VECT_MTU0_TCIV0 118
+#define VECT_MTU0_TGIE0 119
+#define VECT_MTU0_TGIF0 120
+#define VECT_MTU1_TGIA1 121
+#define VECT_MTU1_TGIB1 122
+#define VECT_MTU1_TCIV1 123
+#define VECT_MTU1_TCIU1 124
+#define VECT_MTU2_TGIA2 125
+#define VECT_MTU2_TGIB2 126
+#define VECT_MTU2_TCIV2 127
+#define VECT_MTU2_TCIU2 128
+#define VECT_MTU3_TGIA3 129
+#define VECT_MTU3_TGIB3 130
+#define VECT_MTU3_TGIC3 131
+#define VECT_MTU3_TGID3 132
+#define VECT_MTU3_TCIV3 133
+#define VECT_MTU4_TGIA4 134
+#define VECT_MTU4_TGIB4 135
+#define VECT_MTU4_TGIC4 136
+#define VECT_MTU4_TGID4 137
+#define VECT_MTU4_TCIV4 138
+#define VECT_MTU5_TGIU5 139
+#define VECT_MTU5_TGIV5 140
+#define VECT_MTU5_TGIW5 141
+#define VECT_POE_OEI1 170
+#define VECT_POE_OEI2 171
+#define VECT_SCI1_ERI1 218
+#define VECT_SCI1_RXI1 219
+#define VECT_SCI1_TXI1 220
+#define VECT_SCI1_TEI1 221
+#define VECT_SCI5_ERI5 222
+#define VECT_SCI5_RXI5 223
+#define VECT_SCI5_TXI5 224
+#define VECT_SCI5_TEI5 225
+#define VECT_SCI12_ERI12 238
+#define VECT_SCI12_RXI12 239
+#define VECT_SCI12_TXI12 240
+#define VECT_SCI12_TEI12 241
+#define VECT_SCI12_SCIX0 242
+#define VECT_SCI12_SCIX1 243
+#define VECT_SCI12_SCIX2 244
+#define VECT_SCI12_SCIX3 245
+#define VECT_RIIC0_EEI0 246
+#define VECT_RIIC0_RXI0 247
+#define VECT_RIIC0_TXI0 248
+#define VECT_RIIC0_TEI0 249
+
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17
+#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0
+
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR
+#define _IR( x ) __IR( x )
+#define IR( x , y ) _IR( _ ## x ## _ ## y )
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE
+#define _DTCE( x ) __DTCE( x )
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x
+#define _IEN( x ) __IEN( x )
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR
+#define _IPR( x ) __IPR( x )
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )
+#define __VECT( x ) VECT ## x
+#define _VECT( x ) __VECT( x )
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )
+#define __MSTP( x ) MSTP ## x
+#define _MSTP( x ) __MSTP( x )
+#define MSTP( x ) _MSTP( _ ## x )
+
+#define BSC (*(volatile struct st_bsc *)0x81300)
+#define CAC (*(volatile struct st_cac *)0x8B000)
+#define CMT (*(volatile struct st_cmt *)0x88000)
+#define CMT0 (*(volatile struct st_cmt0 *)0x88002)
+#define CMT1 (*(volatile struct st_cmt0 *)0x88008)
+#define CRC (*(volatile struct st_crc *)0x88280)
+#define DA (*(volatile struct st_da *)0x880C0)
+#define DOC (*(volatile struct st_doc *)0x8B080)
+#define DTC (*(volatile struct st_dtc *)0x82400)
+#define ELC (*(volatile struct st_elc *)0x8B100)
+#define FLASH (*(volatile struct st_flash *)0x7FC090)
+#define ICU (*(volatile struct st_icu *)0x87000)
+#define IWDT (*(volatile struct st_iwdt *)0x88030)
+#define MPC (*(volatile struct st_mpc *)0x8C11F)
+#define MTU (*(volatile struct st_mtu *)0x8860A)
+#define MTU0 (*(volatile struct st_mtu0 *)0x88690)
+#define MTU1 (*(volatile struct st_mtu1 *)0x88690)
+#define MTU2 (*(volatile struct st_mtu2 *)0x88692)
+#define MTU3 (*(volatile struct st_mtu3 *)0x88600)
+#define MTU4 (*(volatile struct st_mtu4 *)0x88600)
+#define MTU5 (*(volatile struct st_mtu5 *)0x88694)
+#define POE (*(volatile struct st_poe *)0x88900)
+#define PORT (*(volatile struct st_port *)0x8C120)
+#define PORT0 (*(volatile struct st_port0 *)0x8C000)
+#define PORT1 (*(volatile struct st_port1 *)0x8C001)
+#define PORT2 (*(volatile struct st_port2 *)0x8C002)
+#define PORT3 (*(volatile struct st_port3 *)0x8C003)
+#define PORT4 (*(volatile struct st_port4 *)0x8C004)
+#define PORT5 (*(volatile struct st_port5 *)0x8C005)
+#define PORTA (*(volatile struct st_porta *)0x8C00A)
+#define PORTB (*(volatile struct st_portb *)0x8C00B)
+#define PORTC (*(volatile struct st_portc *)0x8C00C)
+#define PORTE (*(volatile struct st_porte *)0x8C00E)
+#define RIIC0 (*(volatile struct st_riic *)0x88300)
+#define RSPI0 (*(volatile struct st_rspi *)0x88380)
+#define RTC (*(volatile struct st_rtc *)0x8C400)
+#define RTCB (*(volatile struct st_rtcb *)0x8C402)
+#define S12AD (*(volatile struct st_s12ad *)0x89000)
+#define SCI1 (*(volatile struct st_sci1 *)0x8A020)
+#define SCI5 (*(volatile struct st_sci1 *)0x8A0A0)
+#define SCI12 (*(volatile struct st_sci12 *)0x8B300)
+#define SMCI1 (*(volatile struct st_smci *)0x8A020)
+#define SMCI5 (*(volatile struct st_smci *)0x8A0A0)
+#define SMCI12 (*(volatile struct st_smci *)0x8B300)
+#define SYSTEM (*(volatile struct st_system *)0x80000)
+#define USB0 (*(volatile struct st_usb *)0xA0000)
+#endif /*__RX_LITTLE_ENDIAN__*/
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h
new file mode 100644
index 000000000..6ed672bf5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h
@@ -0,0 +1,112 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : mcu_info.h
+* Device(s) : RX111
+* Description : Information about the MCU on this board (RSKRX111).
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef _MCU_INFO
+#define _MCU_INFO
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Gets MCU configuration information. */
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* MCU Series. */
+#if MCU_PART_SERIES == 0x0
+ #define MCU_SERIES_RX100 (1)
+#else
+ #error "ERROR - MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"
+#endif
+
+/* MCU Group name. */
+#if MCU_PART_GROUP == 0x1
+ #define MCU_RX111 (1)
+ #define MCU_RX11x (1)
+#else
+ #error "ERROR - MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"
+#endif
+
+/* Package. */
+#if MCU_PART_PACKAGE == 0x0
+ #define PACKAGE_LFQFP64 (1)
+#elif MCU_PART_PACKAGE == 0x1
+ #define PACKAGE_LQFP64 (1)
+#elif MCU_PART_PACKAGE == 0x2
+ #define PACKAGE_TFLGA64 (1)
+#elif MCU_PART_PACKAGE == 0x3
+ #define PACKAGE_LFQFP48 (1)
+#elif MCU_PART_PACKAGE == 0x4
+ #define PACKAGE_VQFN48 (1)
+#elif MCU_PART_PACKAGE == 0x5
+ #define PACKAGE_HWQFN36 (1)
+#elif MCU_PART_PACKAGE == 0x6
+ #define PACKAGE_WFLGA36 (1)
+#elif MCU_PART_PACKAGE == 0x7
+ #define PACKAGE_SSOP36 (1)
+#else
+ #error "ERROR - MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"
+#endif
+
+/* Memory size of your MCU. */
+#if MCU_PART_MEMORY_SIZE == 0x0 // "J" parts
+ #define ROM_SIZE_BYTES (16384)
+ #define RAM_SIZE_BYTES (8192)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x1
+ #define ROM_SIZE_BYTES (32768)
+ #define RAM_SIZE_BYTES (10240)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x3
+ #define ROM_SIZE_BYTES (65536)
+ #define RAM_SIZE_BYTES (10240)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x4
+ #define ROM_SIZE_BYTES (98304)
+ #define RAM_SIZE_BYTES (16384)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x5
+ #define ROM_SIZE_BYTES (131072)
+ #define RAM_SIZE_BYTES (16384)
+ #define DF_SIZE_BYTES (8192)
+#else
+ #error "ERROR - MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"
+#endif
+
+/* System clock speed in Hz. */
+#define ICLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV)
+/* Peripheral Module Clock B speed in Hz. */
+#define PCLKB_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV)
+/* Peripheral Module Clock D speed in Hz. */
+#define PCLKD_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV)
+/* FlashIF clock speed in Hz. */
+#define FCLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV)
+
+#endif /* _MCU_INFO */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/reset_program.asm b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/reset_program.asm
new file mode 100644
index 000000000..4a1497cb0
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/reset_program.asm
@@ -0,0 +1,175 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : reset_program.asm */
+/* DESCRIPTION : Reset Program */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+ /*reset_program.asm*/
+
+ .list
+ .section .text
+ .global _PowerON_Reset /*global Start routine */
+
+ .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/
+ .extern _data
+ .extern _mdata
+ .extern _ebss
+ .extern _bss
+ .extern _edata
+ .extern _main
+ .extern _ustack
+ .extern _istack
+ .extern _rvectors
+ .extern _exit
+
+
+_PowerON_Reset :
+/* initialise user stack pointer */
+ mvtc #_ustack,USP
+
+/* initialise interrupt stack pointer */
+ mvtc #_istack,ISP
+
+/* setup intb */
+ mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */
+
+/* load data section from ROM to RAM */
+
+ mov #_mdata,r2 /* src ROM address of data section in R2 */
+ mov #_data,r1 /* dest start RAM address of data section in R1 */
+ mov #_edata,r3 /* end RAM address of data section in R3 */
+ sub r1,r3 /* size of data section in R3 (R3=R3-R1) */
+ smovf /* block copy R3 bytes from R2 to R1 */
+
+/* bss initialisation : zero out bss */
+
+ mov #00h,r2 /* load R2 reg with zero */
+ mov #_ebss, r3 /* store the end address of bss in R3 */
+ mov #_bss, r1 /* store the start address of bss in R1 */
+ sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */
+ sstr.b
+/* call the hardware initialiser */
+ bsr.a _HardwareSetup
+ nop
+
+#ifdef RUN_IN_USER_MODE
+/* setup PSW */
+ mvtc #10000h, psw /* Set Ubit & Ibit for PSW */
+
+/* change PSW PM to user-mode */
+ MVFC PSW,R1
+ OR #00100000h,R1
+ PUSH.L R1
+ MVFC PC,R1
+ ADD #10,R1
+ PUSH.L R1
+ RTE
+ NOP
+ NOP
+#endif
+#ifdef CPPAPP
+ bsr.a __rx_init
+#endif
+/* start user program */
+ bsr.a _main
+ bsr.a _exit
+
+#ifdef CPPAPP
+ .global _rx_run_preinit_array
+ .type _rx_run_preinit_array,@function
+_rx_run_preinit_array:
+ mov #__preinit_array_start,r1
+ mov #__preinit_array_end,r2
+ bra.a _rx_run_inilist
+
+ .global _rx_run_init_array
+ .type _rx_run_init_array,@function
+_rx_run_init_array:
+ mov #__init_array_start,r1
+ mov #__init_array_end,r2
+ mov #4, r3
+ bra.a _rx_run_inilist
+
+ .global _rx_run_fini_array
+ .type _rx_run_fini_array,@function
+_rx_run_fini_array:
+ mov #__fini_array_start,r2
+ mov #__fini_array_end,r1
+ mov #-4, r3
+ /* fall through */
+
+_rx_run_inilist:
+next_inilist:
+ cmp r1,r2
+ beq.b done_inilist
+ mov.l [r1],r4
+ cmp #-1, r4
+ beq.b skip_inilist
+ cmp #0, r4
+ beq.b skip_inilist
+ pushm r1-r3
+ jsr r4
+ popm r1-r3
+skip_inilist:
+ add r3,r1
+ bra.b next_inilist
+done_inilist:
+ rts
+
+ .section .init,"ax"
+ .balign 4
+
+ .global __rx_init
+__rx_init:
+
+ .section .fini,"ax"
+ .balign 4
+
+ .global __rx_fini
+__rx_fini:
+ bsr.a _rx_run_fini_array
+
+ .section .sdata
+ .balign 4
+ .global __gp
+ .weak __gp
+__gp:
+
+ .section .data
+ .global ___dso_handle
+ .weak ___dso_handle
+___dso_handle:
+ .long 0
+
+ .section .init,"ax"
+ bsr.a _rx_run_preinit_array
+ bsr.a _rx_run_init_array
+ rts
+
+ .global __rx_init_end
+__rx_init_end:
+
+ .section .fini,"ax"
+
+ rts
+ .global __rx_fini_end
+__rx_fini_end:
+
+#endif
+
+/* call to exit*/
+_exit:
+ bra _loop_here
+_loop_here:
+ bra _loop_here
+
+ .text
+ .end
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/typedefine.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/typedefine.h
new file mode 100644
index 000000000..a52e28687
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/typedefine.h
@@ -0,0 +1,25 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : typedefine.h */
+/* DESCRIPTION : Aliases of Integer Type */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+
+typedef signed char _SBYTE;
+typedef unsigned char _UBYTE;
+typedef signed short _SWORD;
+typedef unsigned short _UWORD;
+typedef signed int _SINT;
+typedef unsigned int _UINT;
+typedef signed long _SDWORD;
+typedef unsigned long _UDWORD;
+typedef signed long long _SQWORD;
+typedef unsigned long long _UQWORD;
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/vector_table.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/vector_table.c
new file mode 100644
index 000000000..aac394ee8
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/vector_table.c
@@ -0,0 +1,590 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : vector_table.c */
+/* DESCRIPTION : Vector Table */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+
+
+#include "interrupt_handlers.h"
+
+typedef void (*fp) (void);
+extern void PowerON_Reset (void);
+extern void stack (void);
+extern void vPortSoftwareInterruptISR( void );
+extern void vPortTickISR( void );
+extern void Dummy( void );
+extern void vButtonInterrupt( void );
+
+#ifdef __RX_LITTLE_ENDIAN__
+const unsigned char Endian_Select[] __attribute__ ((section (".endian_bytes"))) = {
+ 0xff, 0xff, 0xff, 0xff
+};
+#elif __RX_BIG_ENDIAN__
+const unsigned char Endian_Select[] __attribute__ ((section (".endian_bytes"))) = {
+ 0xff, 0xff, 0xff, 0xf8
+};
+#endif
+
+// Option bytes setting for OFS1:0xFFFFFF88 and OFS0:0xFFFFFF8C
+const unsigned char Security_Id[] __attribute__ ((section (".option_bytes"))) = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+};
+
+
+#define FVECT_SECT __attribute__ ((section (".fvectors")))
+
+const void *HardwareVectors[] FVECT_SECT = {
+//;0xffffffd0 Exception(Supervisor Instruction)
+ INT_Excep_SuperVisorInst,
+//;0xffffffd4 Reserved
+ (fp)0,
+//;0xffffffd8 Reserved
+ (fp)0,
+//;0xffffffdc Exception(Undefined Instruction)
+ INT_Excep_UndefinedInst,
+//;0xffffffe0 Reserved
+ (fp)0,
+//;0xffffffe4 Exception(Floating Point)
+ INT_Excep_FloatingPoint,
+//;0xffffffe8 Reserved
+ (fp)0,
+//;0xffffffec Reserved
+ (fp)0,
+//;0xfffffff0 Reserved
+ (fp)0,
+//;0xfffffff4 Reserved
+ (fp)0,
+//;0xfffffff8 NMI
+ INT_NonMaskableInterrupt,
+//;0xfffffffc RESET
+//;<>
+//;Power On Reset PC
+ PowerON_Reset
+//;<>
+};
+#define RVECT_SECT __attribute__ ((section (".rvectors")))
+
+const fp RelocatableVectors[] RVECT_SECT = {
+
+//;0x0000 Reserved
+ (fp)0,
+//;0x0004 Reserved
+ (fp)0,
+//;0x0008 Reserved
+ (fp)0,
+//;0x000C Reserved
+ (fp)0,
+//;0x0010 Reserved
+ (fp)0,
+//;0x0014 Reserved
+ (fp)0,
+//;0x0018 Reserved
+ (fp)0,
+//;0x001C Reserved
+ (fp)0,
+//;0x0020 Reserved
+ (fp)0,
+//;0x0024 Reserved
+ (fp)0,
+//;0x0028 Reserved
+ (fp)0,
+//;0x002C Reserved
+ (fp)0,
+//;0x0030 Reserved
+ (fp)0,
+//;0x0034 Reserved
+ (fp)0,
+//;0x0038 Reserved
+ (fp)0,
+//;0x003C Reserved
+ (fp)0,
+//;0x0040
+ (fp)Dummy,
+//;0x0044 Reserved
+ (fp)0,
+//;0x0048 Reserved
+ (fp)0,
+//;0x004C Reserved
+ (fp)0,
+//;0x0050 Reserved
+ (fp)0,
+//;0x0054
+ (fp)Dummy,
+//;0x0058 Reserved
+ (fp)0,
+//;0x005C
+ (fp)Dummy,
+//;0x0060 Reserved
+ (fp)0,
+//;0x0064 Reserved
+ (fp)0,
+//;0x0068 Reserved
+ (fp)0,
+//;0x006C Reserved
+ (fp)vPortSoftwareInterruptISR,
+//;0x0070 CMTU0_CMT0
+ (fp)vPortTickISR,
+//;0x0074
+ (fp)Dummy,
+//;0x0078
+ (fp)Dummy,
+//;0x007C
+ (fp)Dummy,
+//;0x0080
+ (fp)Dummy,
+//;0x0084 Reserved
+ (fp)0,
+//;0x0088 Reserved
+ (fp)0,
+//;0x008C Reserved
+ (fp)0,
+//;0x0090 Reserved
+ (fp)0,
+//;0x0094 Reserved
+ (fp)0,
+//;0x0098 Reserved
+ (fp)0,
+//;0x009C Reserved
+ (fp)0,
+//;0x00A0 Reserved
+ (fp)0,
+//;0x00A4 Reserved
+ (fp)0,
+//;0x00A8 Reserved
+ (fp)0,
+//;0x00AC Reserved
+ (fp)0,
+//;0x00B0 Reserved
+ (fp)0,
+//;0x00B4 Reserved
+ (fp)0,
+//;0x00B8 Reserved
+ (fp)0,
+//;0x00BC Reserved
+ (fp)0,
+//;0x00C0 Reserved
+ (fp)0,
+//;0x00C4 Reserved
+ (fp)0,
+//;0x00C8 Reserved
+ (fp)0,
+//;0x00CC Reserved
+ (fp)0,
+//;0x00D0 Reserved
+ (fp)0,
+//;0x00D4 Reserved
+ (fp)0,
+//;0x00D8 Reserved
+ (fp)0,
+//;0x00DC Reserved
+ (fp)0,
+//;0x00E0 Reserved
+ (fp)0,
+//;0x00E4 Reserved
+ (fp)0,
+//;0x00E8 Reserved
+ (fp)0,
+//;0x00EC Reserved
+ (fp)0,
+//;0x00F0 Reserved
+ (fp)0,
+//;0x00F4 Reserved
+ (fp)0,
+//;0x00F8 Reserved
+ (fp)0,
+//;0x00FC Reserved
+ (fp)0,
+//;0x0100 IRQ0
+ (fp)vButtonInterrupt,
+//;0x0104 IRQ1
+ (fp)vButtonInterrupt,
+//;0x0108 IRQ2
+ (fp)Dummy,
+//;0x010C IRQ3
+ (fp)Dummy,
+//;0x0110 IRQ4
+ (fp)vButtonInterrupt,
+//;0x0114 IRQ5
+ (fp)Dummy,
+//;0x0118 IRQ6
+ (fp)Dummy,
+//;0x011C IRQ7
+ (fp)Dummy,
+//;0x0120
+ (fp)Dummy,
+//;0x0124
+ (fp)Dummy,
+//;0x0128
+ (fp)Dummy,
+//;0x012C
+ (fp)Dummy,
+//;0x0130
+ (fp)Dummy,
+//;0x0134
+ (fp)Dummy,
+//;0x0138
+ (fp)Dummy,
+//;0x013C
+ (fp)Dummy,
+//;0x0140 Reserved
+ (fp)0,
+//;0x0144 Reserved
+ (fp)0,
+//;0x0148 Reserved
+ (fp)0,
+//;0x014C Reserved
+ (fp)0,
+//;0x0150 Reserved
+ (fp)0,
+//;0x0154 Reserved
+ (fp)0,
+//;0x0158 Reserved
+ (fp)0,
+//;0x015C Reserved
+ (fp)0,
+//;0x0160 Reserved
+ (fp)0,
+//;0x0164 Reserved
+ (fp)0,
+//;0x0168 Reserved
+ (fp)0,
+//;0x016C Reserved
+ (fp)0,
+//;0x0170 Reserved
+ (fp)0,
+//;0x0174 Reserved
+ (fp)0,
+//;0x0178 Reserved
+ (fp)0,
+//;0x017C Reserved
+ (fp)0,
+//;0x0180
+ (fp)Dummy,
+//;0x0184 Reserved
+ (fp)0,
+//;0x0188
+ (fp)Dummy,
+//;0x018C
+ (fp)Dummy,
+//;0x0190
+ (fp)Dummy,
+//;0x0194
+ (fp)Dummy,
+//;0x0198 Reserved
+ (fp)0,
+//;0x019C Reserved
+ (fp)0,
+//;0x01A0
+ (fp)Dummy,
+//;0x01A4
+ (fp)Dummy,
+//;0x01A8
+ (fp)Dummy,
+//;0x01AC
+ (fp)Dummy,
+//;0x01B0
+ (fp)Dummy,
+//;0x01B4 Reserved
+ (fp)0,
+//;0x01B8 Reserved
+ (fp)0,
+//;0x01BC
+ (fp)Dummy,
+//;0x01C0
+ (fp)Dummy,
+//;0x01C4 Reserved
+ (fp)Dummy,
+//;0x01C8 Reserved
+ (fp)Dummy,
+//;0x01CC
+ (fp)Dummy,
+//;0x01D0
+ (fp)Dummy,
+//;0x01D4
+ (fp)Dummy,
+//;0x01D8
+ (fp)Dummy,
+//;0x01DC Reserved
+ (fp)Dummy,
+//;0x01E0
+ (fp)Dummy,
+//;0x01E4
+ (fp)Dummy,
+//;0x01E8
+ (fp)Dummy,
+//;0x01EC
+ (fp)Dummy,
+//;0x01F0
+ (fp)Dummy,
+//;0x01F4
+ (fp)Dummy,
+//;0x01F8
+ (fp)Dummy,
+//;0x01FC
+ (fp)Dummy,
+//;0x0200
+ (fp)Dummy,
+//;0x0204 Reserved
+ (fp)Dummy,
+//;0x0208 Reserved
+ (fp)Dummy,
+//;0x020C
+ (fp)Dummy,
+//;0x0210
+ (fp)Dummy,
+//;0x0214
+ (fp)Dummy,
+//;0x0218
+ (fp)Dummy,
+//;0x021C Reserved
+ (fp)Dummy,
+//;0x0220
+ (fp)Dummy,
+//;0x0224
+ (fp)Dummy,
+//;0x0228
+ (fp)Dummy,
+//;0x022C
+ (fp)Dummy,
+//;0x0230
+ (fp)Dummy,
+//;0x0234
+ (fp)Dummy,
+//;0x0238
+ (fp)Dummy,
+//;0x023C Reserved
+ (fp)Dummy,
+//;0x0240 Reserved
+ (fp)Dummy,
+//;0x0244
+ (fp)Dummy,
+//;0x0248
+ (fp)Dummy,
+//;0x024C Reserved
+ (fp)Dummy,
+//;0x0250 Reserved
+ (fp)Dummy,
+//;0x0254
+ (fp)Dummy,
+//;0x0258
+ (fp)Dummy,
+//;0x025C
+ (fp)Dummy,
+//;0x0260
+ (fp)Dummy,
+//;0x0264 Reserved
+ (fp)Dummy,
+//;0x0268
+ (fp)Dummy,
+//;0x026C
+ (fp)Dummy,
+//;0x0270
+ (fp)Dummy,
+//;0x0274
+ (fp)Dummy,
+//;0x0278
+ (fp)Dummy,
+//;0x027C
+ (fp)Dummy,
+//;0x0280
+ (fp)Dummy,
+//;0x0284
+ (fp)Dummy,
+//;0x0288
+ (fp)Dummy,
+//;0x028C Reserved
+ (fp)Dummy,
+//;0x0290 Reserved
+ (fp)Dummy,
+//;0x0294
+ (fp)Dummy,
+//;0x0298
+ (fp)Dummy,
+//;0x029C
+ (fp)Dummy,
+//;0x02A0
+ (fp)Dummy,
+//;0x02A4 Reserved
+ (fp)Dummy,
+//;0x02A8
+ (fp)Dummy,
+//;0x02AC
+ (fp)Dummy,
+//;0x02B0 Reserved
+ (fp)Dummy,
+//;0x02B4 Reserved
+ (fp)Dummy,
+//;0x02B8
+ (fp)Dummy,
+//;0x02BC
+ (fp)Dummy,
+//;0x02C0
+ (fp)Dummy,
+//;0x02C4
+ (fp)Dummy,
+//;0x02C8
+ (fp)Dummy,
+//;0x02CC
+ (fp)Dummy,
+//;0x02D0
+ (fp)Dummy,
+//;0x02D4
+ (fp)Dummy,
+//;0x02D8
+ (fp)Dummy,
+//;0x02DC
+ (fp)Dummy,
+//;0x02E0
+ (fp)Dummy,
+//;0x02E4
+ (fp)Dummy,
+//;0x02E8 Reserved
+ (fp)Dummy,
+//;0x02EC Reserved
+ (fp)Dummy,
+//;0x02F0 Reserved
+ (fp)Dummy,
+//;0x02F4 Reserved
+ (fp)Dummy,
+//;0x02F8 Reserved
+ (fp)Dummy,
+//;0x02FC Reserved
+ (fp)Dummy,
+//;0x0300 Reserved
+ (fp)Dummy,
+//;0x0304 Reserved
+ (fp)Dummy,
+//;0x0308 Reserved
+ (fp)Dummy,
+//;0x030C Reserved
+ (fp)Dummy,
+//;0x0310 Reserved
+ (fp)Dummy,
+//;0x0314 Reserved
+ (fp)Dummy,
+//;0x0318
+ (fp)Dummy,
+//;0x031C
+ (fp)Dummy,
+//;0x0320
+ (fp)Dummy,
+//;0x0324
+ (fp)Dummy,
+//;0x0328 Reserved
+ (fp)Dummy,
+//;0x032C Reserved
+ (fp)Dummy,
+//;0x0330 Reserved
+ (fp)Dummy,
+//;0x0334 Reserved
+ (fp)Dummy,
+//;0x0338 Reserved
+ (fp)Dummy,
+//;0x033C Reserved
+ (fp)Dummy,
+//;0x0340 Reserved
+ (fp)Dummy,
+//;0x0344 Reserved
+ (fp)Dummy,
+//;0x0348 Reserved
+ (fp)Dummy,
+//;0x034C Reserved
+ (fp)Dummy,
+//;0x0350 Reserved
+ (fp)Dummy,
+//;0x0354 Reserved
+ (fp)Dummy,
+//;0x0358
+ (fp)Dummy,
+//;0x035C
+ (fp)Dummy,
+//;0x0360
+ (fp)Dummy,
+//;0x0364
+ (fp)Dummy,
+//;0x0368
+ (fp)Dummy,
+//;0x036C
+ (fp)Dummy,
+//;0x0370
+ (fp)Dummy,
+//;0x0374
+ (fp)Dummy,
+//;0x0378
+ (fp)Dummy,
+//;0x037C
+ (fp)Dummy,
+//;0x0380
+ (fp)Dummy,
+//;0x0384
+ (fp)Dummy,
+//;0x0388
+ (fp)Dummy,
+//;0x038C
+ (fp)Dummy,
+//;0x0390
+ (fp)Dummy,
+//;0x0394
+ (fp)Dummy,
+//;0x0398
+ (fp)Dummy,
+//;0x039C
+ (fp)Dummy,
+//;0x03A0
+ (fp)Dummy,
+//;0x03A4
+ (fp)Dummy,
+//;0x03A8
+ (fp)Dummy,
+//;0x03AC
+ (fp)Dummy,
+//;0x03B0
+ (fp)Dummy,
+//;0x03B4
+ (fp)Dummy,
+//;0x03B8
+ (fp)Dummy,
+//;0x03BC
+ (fp)Dummy,
+//;0x03C0
+ (fp)Dummy,
+//;0x03C4
+ (fp)Dummy,
+//;0x03C8 Reserved
+ (fp)Dummy,
+//;0x03CC Reserved
+ (fp)Dummy,
+//;0x03D0 Reserved
+ (fp)Dummy,
+//;0x03D4 Reserved
+ (fp)Dummy,
+//;0x03D8
+ (fp)Dummy,
+//;0x03DC
+ (fp)Dummy,
+//;0x03E0
+ (fp)Dummy,
+//;0x03E4
+ (fp)Dummy,
+//;0x03E8
+ (fp)Dummy,
+//;0x03EC
+ (fp)Dummy,
+//;0x03F0
+ (fp)Dummy,
+//;0x03F4
+ (fp)Dummy,
+//;0x03F8 Reserved
+ (fp)0,
+//;0x03FC Reserved
+ (fp)0,
+};
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/platform.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/platform.h
new file mode 100644
index 000000000..3427aab94
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/platform.h
@@ -0,0 +1,88 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : platform.h
+* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using
+* is not listed below, please add your own or use the default 'User Board'.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 30.11.2011 1.00 First Release
+* : 13.01.2012 1.10 Moved from having platform defined using macro defintion, to having platform defined
+* by choosing an include path. This makes this file simpler and cleans up the issue
+* where HEW shows all header files for all platforms under 'Dependencies'.
+* : 14.02.2012 1.20 Added RX210 BSP.
+* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding
+* locking.c and locking.h in board folders. Also, r_bsp can now be configured through
+* r_bsp_config.h.
+* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using
+* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort
+* to remove any extra files that the user would need to touch. Removed the flash_options.c
+* file and put its contents in vecttbl.c.
+* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT
+* macro options in r_bsp_config.h. Added some extra code to handle exceptions in
+* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.
+* : 08.11.2012 1.60 Added RX111 BSP
+***********************************************************************************************************************/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+/***********************************************************************************************************************
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.
+***********************************************************************************************************************/
+/* RSKRX610 */
+//#include "./board/rskrx610/r_bsp.h"
+
+/* RSKRX62N */
+//#include "./board/rskrx62n/r_bsp.h"
+
+/* RSKRX62T */
+//#include "./board/rskrx62t/r_bsp.h"
+
+/* RDKRX62N */
+//#include "./board/rdkrx62n/r_bsp.h"
+
+/* RSKRX630 */
+//#include "./board/rskrx630/r_bsp.h"
+
+/* RSKRX63N */
+//#include "./board/rskrx63n/r_bsp.h"
+
+/* RDKRX63N */
+//#include "./board/rdkrx63n/r_bsp.h"
+
+/* RSKRX210 */
+//#include "./board/rskrx210/r_bsp.h"
+
+/* RSKRX111 */
+#include "./board/rskrx111/r_bsp.h"
+
+/* User Board - Define your own board here. */
+//#include "./board/user/r_bsp.h"
+
+/***********************************************************************************************************************
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT
+***********************************************************************************************************************/
+#ifndef PLATFORM_DEFINED
+#error "Error - No platform defined in platform.h!"
+#endif
+
+#endif /* _PLATFORM_H_ */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/r_bsp_config.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/r_bsp_config.h
new file mode 100644
index 000000000..537479e8a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/r_bsp_config.h
@@ -0,0 +1,250 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.c
+* Device(s) : RX111
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 51 11 5 A D FM
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)
+ | | | | | | |______not used = Blank
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________MCU_PART_GROUP = Group name
+ | | | |______________MCU_PART_SERIES = Series name
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FM = 0x0 = LFQFP/64/0.50
+ FK = 0x1 = LQFP/64/0.80
+ LF = 0x2 = TFLGA/64/0.50
+ FL = 0x3 = LFQFP/48/0.50
+ NE = 0x4 = VQFN/48/0.50
+ NC = 0x5 = HWQFN/36/0.50
+ LM = 0x6 = WFLGA/36/0.50
+ SB = 0x7 = SSOP/36/0.80
+*/
+#define MCU_PART_PACKAGE (0x0)
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 5 = 0x5 = 128KB/16KB/8KB
+ 4 = 0x4 = 96KB/16KB/8KB
+ 3 = 0x3 = 64KB/10KB/8KB
+ 1 = 0x1 = 32KB/10KB/8KB
+ J = 0x0 = 16KB/8KB/8KB
+*/
+#define MCU_PART_MEMORY_SIZE (0x5)
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 10 = 0x0 = RX110 Group
+ 11 = 0x1 = RX111 Group
+*/
+#define MCU_PART_GROUP (0x1)
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 51 = 0x0 = RX100 Series
+*/
+#define MCU_PART_SERIES (0x0)
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define MCU_PART_MEMORY_TYPE (0x0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize su=0x400
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize si=0x100
+#endif
+
+/* Heap size in bytes. */
+#define HEAP_BYTES (0x001)
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define RUN_IN_USER_MODE (0)
+
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = RTOS is used.
+*/
+#define RTOS_USED (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define CLOCK_SOURCE (4) // GI org 4
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the
+ settings would be:
+
+ XTAL_HZ = 16000000
+ PLL_DIV = 2
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz
+*/
+/* XTAL - Input clock frequency in Hz */
+#define XTAL_HZ (16000000)
+/* PLL Input Frequency Divider Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /4
+*/
+#define PLL_DIV (2) // GI org 2
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x6, x8
+*/
+#define PLL_MUL (6) // GI org 6
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define ICK_DIV (2) // NOTE: ICLK CANNOT BE SLOWER THAN PCLK!
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKB_DIV (2) // GI org 2
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKD_DIV (2)
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define FCK_DIV (2)
+
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a
+ function to be called when the event occurs. For example, if the user wanted the function
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would
+ do the following:
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+ If the user does not wish to be alerted of these events then they should comment out the macros.
+
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it
+ is executing. For this reason, it is recommended to keep these callback functions short as to not
+ decrease the real-time response of your system.
+*/
+/* Callback for Supervisor Instruction Violation Exception. */
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb
+
+/* Callback for Undefined Instruction Exception. */
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb
+
+/* Callback for Non-maskable Interrupt. */
+//#define NMI_ISR_CALLBACK nmi_cb
+
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source
+ is creating unwanted interrupts. */
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+
+/* Callback for Bus Error Interrupt. */
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb
+
+/* The user has the option of separately choosing little or big endian for the User Application Area */
+
+/* Endian mode for User Application.
+ 0 = Big Endian
+ Else = Little Endian (Default)
+*/
+#define USER_APP_ENDIAN (1)
+
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ OFS0 - Option Function Select Register 0
+ b31:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1) */
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select
+ 0 1 0 0: 3.10 V
+ 0 1 0 1: 3.00 V
+ 0 1 1 0: 2.90 V
+ 0 1 1 1: 2.79 V
+ 1 0 0 0: 2.68 V
+ 1 0 0 1: 2.58 V
+ 1 0 1 0: 2.48 V
+ 1 0 1 1: 2.06 V
+ 1 1 0 0: 1.96 V
+ 1 1 0 1: 1.86 V
+ b3:b2 Reserved (set to 1)
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define IO_LIB_ENABLE (0)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/readme.txt b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/readme.txt
new file mode 100644
index 000000000..c7ee2b751
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_bsp/readme.txt
@@ -0,0 +1,100 @@
+r_bsp Package
+=============
+
+Document Number
+---------------
+N/A
+
+Version
+-------
+v1.60
+
+Overview
+--------
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder has iodefine
+files and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each
+supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.
+
+Features
+--------
+* Provides foundation to build code on top of.
+* Provides MCU startup code.
+* Provides SFR access through iodefine.h
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.
+* Easily configure BSP through r_bsp_config.h.
+* Choose MCU easily by inputting part number details in r_bsp_config.h.
+* Provides callbacks for MCU exceptions and the bus error interrupt.
+
+Limitations
+-----------
+N/A
+
+Peripherals Used Directly
+-------------------------
+N/A
+
+Required Packages
+-----------------
+* r_glyph [required if you want to use LCD for RDK boards]
+* r_rspi_rx [required if you want to use LCD for RDK boards]
+
+How to add to your project
+--------------------------
+* Copy the r_bsp folder to your project.
+* Add an include path to the 'r_bsp' directory.
+* Add all of the source files for your board from the 'r_bsp\board\--YOUR_BOARD--' directory to your project.
+* Uncomment the include path for your board in 'platform.h' which is located in the 'r_bsp' directory.
+* Copy the file r_bsp_config_reference.h from the 'r_bsp\board\--YOUR_BOARD--' directory and copy it to your project's
+ source code directory. Rename the file r_bsp_config.h.
+* Open r_bsp_config.h and use the macros to configure the BSP for your project.
+
+File Structure
+--------------
+r_bsp
+| platform.h (choose which board is being used)
+| readme.txt
+|
++---board (contains supported boards)
+| +---rdkrx62n (contains BSP source and header files)
+| |
+| +---rdkrx63n
+| |
+| +---rskrx111
+| |
+| +---rskrx210
+| |
+| +---rskrx610
+| |
+| +---rskrx62n
+| |
+| +---rskrx62t
+| |
+| +---rskrx630
+| |
+| +---rskrx63n
+| |
+| \---user
+|
+\---mcu
+ +---rx111 (contains common files to this MCU group, e.g. iodefine.h)
+ |
+ +---rx210
+ |
+ +---rx610
+ |
+ +---rx62n
+ |
+ +---rx62t
+ |
+ +---rx630
+ |
+ \---rx63n
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/doc/r_switches.docx b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/doc/r_switches.docx
new file mode 100644
index 000000000..6fe7e86e5
Binary files /dev/null and b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/doc/r_switches.docx differ
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_config.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_config.h
new file mode 100644
index 000000000..ba6d58f00
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_config.h
@@ -0,0 +1,47 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_config.c
+* Description : Configures the switches code
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+#ifndef SWITCHES_CONFIG_HEADER_FILE
+#define SWITCHES_CONFIG_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* This macro sets whether interrupts or polling is used for detecting switch presses. The benefit of using interrupts
+ is that no extra processing is used for polling and the use of a system timer tick is not a requirement. The downside
+ of using interrupts is that callback functions are called from within an interrupt so if your ISR is long then it can
+ degrade the real-time response of your system. The benefit of polling is that functions are called at the application
+ level and debouncing is supported. The downside to polling is that your system must call the R_SWITCHES_Update() on a
+ regular basis which requires extra processing.
+
+ 0 = Use interrupts
+ 1 = Use polling
+ */
+#define SWITCHES_DETECTION_MODE (0)
+
+#endif /* SWITCHES_CONFIG_HEADER_FILE */
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_if.h b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_if.h
new file mode 100644
index 000000000..c2f8d08cd
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_if.h
@@ -0,0 +1,72 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_if.h
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+
+#ifndef SWITCHES_API_HEADER_FILE
+#define SWITCHES_API_HEADER_FILE
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed width integer support. */
+#include
+/* Used for configuring the code */
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Version Number of API. */
+#define SWITCHES_VERSION_MAJOR (1)
+#define SWITCHES_VERSION_MINOR (0)
+/* The process of getting the version number is done through the macro below. The version number is encoded where the
+ top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example,
+ Version 4.25 would be returned as 0x00040019. */
+#define R_SWITCHES_GetVersion() ((((uint32_t)SWITCHES_VERSION_MAJOR) << 16) | (uint32_t)SWITCHES_VERSION_MINOR)
+
+/***********************************************************************************************************************
+Public Functions
+***********************************************************************************************************************/
+void R_SWITCHES_Init(void);
+void R_SWITCHES_Update(void);
+
+/* Callback prototypes. */
+#if defined(SW1_CALLBACK_FUNCTION)
+void SW1_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW2_CALLBACK_FUNCTION)
+void SW2_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW3_CALLBACK_FUNCTION)
+void SW3_CALLBACK_FUNCTION(void);
+#endif
+
+#endif /* SWITCHES_API_HEADER_FILE */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/readme.txt b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/readme.txt
new file mode 100644
index 000000000..d1e1e40fb
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/readme.txt
@@ -0,0 +1,83 @@
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION
+
+Switches
+========
+
+Document Number
+---------------
+N/A
+
+Version
+-------
+v1.40
+
+Overview
+--------
+Configures port pins for switches and calls user defined function on switch press. Switch presses can be detected using
+IRQ interrupts or by polling. The benefit of using interrupts is that no extra processing is used for polling and the
+use of a system timer tick is not a requirement. The downside of using interrupts is that callback functions are called
+from within an interrupt so if your ISR is long then it can degrade the real-time response of your system. The benefit
+of polling is that functions are called at the application level and debouncing is supported. The downside to polling is
+that your system must call the R_SWITCHES_Update() on a regular basis which requires extra processing.
+
+Features
+--------
+* Call one function to setup switches.
+* Define function to call when switch is pressed.
+* Can be configured to be interrupt or poll driven.
+
+Supported MCUs
+--------------
+* RX610 Group
+* RX621, RX62N Group
+* RX62T Group
+* RX630 Group
+* RX631, RX63N Group
+* RX210 Group
+* RX111 Group
+
+Boards Tested On
+----------------
+* RSKRX610
+* RSK+RX62N
+* RSKRX62T
+* RDKRX62N
+* RSKRX630
+* RSKRX63N
+* RDKRX63N
+* RSKRX111
+
+Limitations
+-----------
+* None
+
+Peripherals Used Directly
+-------------------------
+* None
+
+Required Packages
+-----------------
+* None
+
+How to add to your project
+--------------------------
+* Add src\r_switches.c to your project.
+* Add an include path to the 'r_switches' directory.
+* Add an include path to the 'r_switches\src' directory.
+* Configure middleware through r_switches_config.h.
+* Add a #include for r_switches_if.h to files that need to use this package.
+
+Toolchain(s) Used
+-----------------
+* Renesas RX v1.02
+
+File Structure
+--------------
+r_switches
+| readme.txt
+| r_switches_config.h
+| r_switches_if.h
+|
+\---src
+ r_switches.c
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/src/r_switches.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/src/r_switches.c
new file mode 100644
index 000000000..1fb19e19f
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/Renesas_Files/r_switches/src/r_switches.c
@@ -0,0 +1,232 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches.c
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+* : 07.11.2012 1.40 Added support for RSKRX111
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Board and MCU support. */
+#include "platform.h"
+/* Switches prototypes. */
+#include "r_switches_if.h"
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+typedef int bool;
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* This helps reduce the amount of unique code for each supported board. */
+#define X_IRQ( x ) XX_IRQ( x )
+#define XX_IRQ( x ) _ICU_IRQ##x
+
+/* These macros define which IRQ pins are used for the switches. Note that these defintions cannot have parentheses
+ around them. */
+#if defined(PLATFORM_BOARD_RSKRX111)
+ #define SW1_IRQ_NUMBER 0
+ #define SW2_IRQ_NUMBER 1
+ #define SW3_IRQ_NUMBER 4
+#else
+ #error This file is only for use on the RX100 RSK
+#endif
+
+/* Number of switches on this board. */
+#define SWITCHES_NUM (3)
+
+/* Register definitions not yet correct in iodefine.h. */
+#define MPC_P30PFS_REG ( * ( unsigned char * ) 0x0008C158 )
+#define MPC_P31PFS_REG ( * ( unsigned char * ) 0x0008C159 )
+#define MPC_PE4PFS_REG ( * ( unsigned char * ) 0x0008C1B4 )
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef struct
+{
+ bool active;
+ int32_t debounce_cnt;
+} switch_t;
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+#if SWITCHES_DETECTION_MODE == 1
+/* Update Hz */
+static uint32_t g_sw_debounce_cnts;
+/* Used for debounce. */
+switch_t g_switches[SWITCHES_NUM];
+#endif
+
+/***********************************************************************************************************************
+* Function Name: R_SWITCHES_Init
+* Description : Initializes pins to be input and interrupt on switch presses.
+* Arguments :
+* Return Value : none
+***********************************************************************************************************************/
+
+void R_SWITCHES_Init (void)
+{
+ /* Unlock protection register */
+ MPC.PWPR.BYTE &= 0x7F;
+ /* Unlock MPC registers */
+ MPC.PWPR.BYTE |= 0x40;
+
+ /* Make switch pins inputs. */
+ PORT3.PDR.BYTE &= 0xFC;
+ PORTE.PDR.BYTE &= 0xEF;
+
+ /* Set port mode registers for switches. */
+ PORT3.PMR.BYTE &= 0xFC;
+ PORTE.PMR.BYTE &= 0xEF;
+
+ MPC_P30PFS_REG = 0x40; /* P30 is used as IRQ pin */
+ MPC_P31PFS_REG = 0x40; /* P31 is used as IRQ pin */
+ MPC_PE4PFS_REG = 0x40; /* PE4 is used as IRQ pin */
+
+ /* Set IRQ type (falling edge) */
+ ICU.IRQCR[ SW1_IRQ_NUMBER ].BYTE = 0x04;
+ ICU.IRQCR[ SW2_IRQ_NUMBER ].BYTE = 0x04;
+ ICU.IRQCR[ SW3_IRQ_NUMBER ].BYTE = 0x04;
+
+ /* Set interrupt priorities, which must be below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ _IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+ _IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+ _IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Clear any pending interrupts */
+ _IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;
+ _IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;
+ _IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;
+
+ /* Enable the interrupts */
+ _IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;
+ _IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;
+ _IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;
+}
+
+/* If using polling then the user must call the update function. */
+
+/***********************************************************************************************************************
+* Function name: R_SWITCHES_Update
+* Description : Polls switches and calls callback functions as needed. If you are using IRQ mode then this function
+* is not needed and can be removed if desired. It is left in so that code will not fail when switching
+* between polling or IRQ mode.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void R_SWITCHES_Update (void)
+{
+#if SWITCHES_DETECTION_MODE == 1
+ /* This code is only needed for polling mode. */
+ /* Check switch 1. */
+ if (SW1 == SW_ACTIVE)
+ {
+ if (g_switches[0].active != true)
+ {
+ if (++g_switches[0].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[0].active = true;
+
+ /* Call callback function. */
+ SW1_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[0].debounce_cnt)
+ {
+ g_switches[0].active = false;
+ }
+ else
+ {
+ g_switches[0].debounce_cnt--;
+ }
+ }
+
+ /* Check switch 2. */
+ if (SW2 == SW_ACTIVE)
+ {
+ if (g_switches[1].active != true)
+ {
+ if (++g_switches[1].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[1].active = true;
+
+ /* Call callback function. */
+ SW2_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[1].debounce_cnt)
+ {
+ g_switches[1].active = false;
+ }
+ else
+ {
+ g_switches[1].debounce_cnt--;
+ }
+ }
+
+ /* Check switch 3. */
+ if (SW3 == SW_ACTIVE)
+ {
+ if (g_switches[2].active != true)
+ {
+ if (++g_switches[2].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[2].active = true;
+
+ /* Call callback function. */
+ SW3_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[2].debounce_cnt)
+ {
+ g_switches[2].active = false;
+ }
+ else
+ {
+ g_switches[2].debounce_cnt--;
+ }
+ }
+#endif /* SWITCHES_DETECTION_MODE */
+}
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c
new file mode 100644
index 000000000..194cde0f1
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main.c
@@ -0,0 +1,204 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ * This project provides two demo applications. A low power project that
+ * demonstrates the FreeRTOS tickless mode, and a more comprehensive test and
+ * demo application. The configCREATE_LOW_POWER_DEMO setting (defined at the
+ * top of FreeRTOSConfig.h) is used to select between the two. The low power
+ * demo is implemented and described in main_low_power.c. The more
+ * comprehensive test and demo application is implemented and described in
+ * main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Platform includes. */
+#include "lcd.h"
+
+/*-----------------------------------------------------------*/
+
+/*
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.
+ */
+extern void main_low_power( void );
+extern void main_full( void );
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file. */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* See the documentation page for this demo on the FreeRTOS.org web site for
+full information - including hardware setup requirements. */
+
+void main( void )
+{
+ lcd_initialize();
+ lcd_display( LCD_LINE1, "FreeRTOS" );
+
+ /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */
+ #if configCREATE_LOW_POWER_DEMO == 1
+ {
+ lcd_display( LCD_LINE2, "LP Demo" );
+ main_low_power();
+ }
+ #else
+ {
+ lcd_display( LCD_LINE2, "Ful Demo" );
+ main_full();
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size
+ of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE
+ in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
+ called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* This function will be called by each tick interrupt if
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
+ added here, but the tick hook is called from an interrupt context, so
+ code must not attempt to block, and only the interrupt safe FreeRTOS API
+ functions can be used (those that end in FromISR()). */
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile unsigned long ul = 0;
+
+ taskENTER_CRITICAL();
+ {
+ /* Set ul to a non-zero value using the debugger to step out of this
+ function. */
+ while( ul == 0 )
+ {
+ __asm volatile( "NOP" );
+ }
+ }
+ taskEXIT_CRITICAL();
+}
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c
new file mode 100644
index 000000000..1a2934c0c
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_full.c
@@ -0,0 +1,540 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* ****************************************************************************
+ * This project includes a lot of tasks and tests and is therefore complex.
+ * If you would prefer a much simpler project to get started with then select
+ * the 'low power' demo by setting configCREATE_LOW_POWER_DEMO to 1 in
+ * FreeRTOSConfig.h. When configCREATE_LOW_POWER_DEMO is set to 1 main() will
+ * call main_low_power() instead of main_full().
+ * ****************************************************************************
+ *
+ * Creates all the demo application tasks, then starts the scheduler. The web
+ * documentation provides more details of the standard demo application tasks,
+ * which provide no particular functionality but do provide a good example of
+ * how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill the registers with known values, then
+ * repeatedly check that each register still contains its expected value for
+ * the lifetime of the tasks. Each task uses different values. The tasks run
+ * with very low priority so get preempted very frequently. A check variable
+ * is incremented on each iteration of the test loop. A register containing an
+ * unexpected value is indicative of an error in the context switching
+ * mechanism and will result in a branch to a null loop - which in turn will
+ * prevent the check variable from incrementing any further and allow the check
+ * timer (described below) to determine that an error has occurred. The nature
+ * of the reg test tasks necessitates that they are written in assembly code.
+ *
+ * "Check Timer" and Callback Function - The check timer period is initially
+ * set to three seconds. The check timer callback function checks that all the
+ * standard demo tasks are not only still executing, but are executing without
+ * reporting any errors. If the check timer discovers that a task has either
+ * stalled, or reported an error, then it changes its own period from the
+ * initial three seconds, to just 200ms. The check timer callback function
+ * also toggles LED 0 each time it is called. This provides a visual
+ * indication of the system status: If the LED toggles every three seconds,
+ * then no issues have been discovered. If the LED toggles every 200ms, then
+ * an issue has been discovered with at least one task.
+ *
+ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started.
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.
+*/
+
+/* Standard includes. */
+#include
+
+/* Hardware specific includes. */
+#include "iodefine.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo includes. */
+#include "partest.h"
+#include "death.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+
+/* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set
+to 0, otherwise the code in main_low_power.c is used. */
+#if configCREATE_LOW_POWER_DEMO == 0
+
+
+/* Values that are passed into the reg test tasks using the task parameter.
+The tasks check that the values are passed in correctly. */
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )
+
+/* Priorities at which the standard demo tasks are created. */
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+
+/* The LED toggled by the check timer. */
+#define mainCHECK_LED ( 0 )
+
+/* The period at which the check timer will expire, in ms, provided no errors
+have been reported by any of the standard demo tasks. ms are converted to the
+equivalent in ticks using the portTICK_RATE_MS constant. */
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
+
+/* The period at which the check timer will expire, in ms, if an error has been
+reported in one of the standard demo tasks. ms are converted to the equivalent
+in ticks using the portTICK_RATE_MS constant. */
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
+
+/* A block time of zero simple means "Don't Block". */
+#define mainDONT_BLOCK ( 0UL )
+
+/*
+ * The reg test tasks as described at the top of this file.
+ */
+static void prvRegTest1Task( void *pvParameters );
+static void prvRegTest2Task( void *pvParameters );
+
+/*
+ * The actual implementation of the reg test functionality, which, because of
+ * the direct register access, have to be in assembly.
+ */
+static void prvRegTest1Implementation( void ) __attribute__(( naked ));
+static void prvRegTest2Implementation( void ) __attribute__(( naked ));
+
+/*
+ * The check timer callback function, as described at the top of this file.
+ */
+static void prvCheckTimerCallback( xTimerHandle xTimer );
+
+
+/*-----------------------------------------------------------*/
+
+/* Variables that are incremented on each iteration of the reg test tasks -
+provided the tasks have not reported any errors. The check timer inspects these
+variables to ensure they are still incrementing as expected. If a variable
+stops incrementing then it is likely that its associated task has stalled. */
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;
+
+/* The check timer. This uses prvCheckTimerCallback() as its callback
+function. */
+static xTimerHandle xCheckTimer = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+ /* Start the reg test tasks which test the context switching mechanism. */
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+ /* Create the standard demo tasks. */
+ vCreateBlockTimeTasks();
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
+ vStartRecursiveMutexTasks();
+
+ /* The suicide tasks must be created last as they need to know how many
+ tasks were running prior to their creation in order to ascertain whether
+ or not the correct/expected number of tasks are running at any given time. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Create the software timer that performs the 'check' functionality,
+ as described at the top of this file. */
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
+ );
+
+ configASSERT( xCheckTimer );
+
+ /* Start the check timer. It will actually start when the scheduler is
+ started. */
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );
+
+ /* Start the tasks running. */
+ vTaskStartScheduler();
+
+ /* If all is well execution will never reach here as the scheduler will be
+ running. If this null loop is reached then it is likely there was
+ insufficient FreeRTOS heap available for the idle task and/or timer task to
+ be created. See http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTimerCallback( xTimerHandle xTimer )
+{
+static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS;
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;
+
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) xTimer;
+
+ /* Check the standard demo tasks are running without error. */
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ /* Check the reg test tasks are still cycling. They will stop incrementing
+ their loop counters if they encounter an error. */
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ /* Remember the loop counter values this time around so they can be checked
+ again the next time this callback function executes. */
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;
+
+ /* Toggle the check LED to give an indication of the system status. If
+ the LED toggles every three seconds then everything is ok. A faster toggle
+ indicates an error. */
+ vParTestToggleLED( mainCHECK_LED );
+
+ /* Was an error detected this time through the callback execution? */
+ if( lErrorStatus != pdPASS )
+ {
+ if( lChangedTimerPeriodAlready == pdFALSE )
+ {
+ lChangedTimerPeriodAlready = pdTRUE;
+
+ /* This call to xTimerChangePeriod() uses a zero block time.
+ Functions called from inside of a timer callback function must
+ *never* attempt to block. */
+ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest1Task( void *pvParameters )
+{
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )
+ {
+ /* The parameter did not contain the expected value. */
+ for( ;; )
+ {
+ /* Stop the tick interrupt so its obvious something has gone wrong. */
+ taskDISABLE_INTERRUPTS();
+ }
+ }
+
+ /* This is an inline asm function that never returns. */
+ prvRegTest1Implementation();
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest2Task( void *pvParameters )
+{
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )
+ {
+ /* The parameter did not contain the expected value. */
+ for( ;; )
+ {
+ /* Stop the tick interrupt so its obvious something has gone wrong. */
+ taskDISABLE_INTERRUPTS();
+ }
+ }
+
+ /* This is an inline asm function that never returns. */
+ prvRegTest2Implementation();
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest1Implementation( void )
+{
+ __asm volatile
+ (
+ /* Set each register to a known value. */
+ " MOV.L #0x33333333, R15 \n\t"
+ " MVTACHI R15 \n\t"
+ " MOV.L #0x44444444, R15 \n\t"
+ " MVTACLO R15 \n\t"
+ " MOV.L #1, R1 \n\t"
+ " MOV.L #2, R2 \n\t"
+ " MOV.L #3, R3 \n\t"
+ " MOV.L #4, R4 \n\t"
+ " MOV.L #5, R5 \n\t"
+ " MOV.L #6, R6 \n\t"
+ " MOV.L #7, R7 \n\t"
+ " MOV.L #8, R8 \n\t"
+ " MOV.L #9, R9 \n\t"
+ " MOV.L #10, R10 \n\t"
+ " MOV.L #11, R11 \n\t"
+ " MOV.L #12, R12 \n\t"
+ " MOV.L #13, R13 \n\t"
+ " MOV.L #14, R14 \n\t"
+ " MOV.L #15, R15 \n\t"
+ " \n\t"
+ /* Loop, checking each iteration that each register still contains the
+ expected value. */
+ "TestLoop1: \n\t"
+ " \n\t"
+ /* Push the registers that are going to get clobbered. */
+ " PUSHM R14-R15 \n\t"
+ " \n\t"
+ /* Increment the loop counter to show this task is still getting CPU
+ time. */
+ " MOV.L #_ulRegTest1CycleCount, R14 \n\t"
+ " MOV.L [ R14 ], R15 \n\t"
+ " ADD #1, R15 \n\t"
+ " MOV.L R15, [ R14 ] \n\t"
+ " \n\t"
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR
+ register. */
+ " MOV.L #1, R14 \n\t"
+ " MOV.L #0872E0H, R15 \n\t"
+ " MOV.B R14, [R15] \n\t"
+ " NOP \n\t"
+ " NOP \n\t"
+ " \n\t"
+ /* Check the accumulator value. */
+ " MVFACHI R15 \n\t"
+ " CMP #0x33333333, R15 \n\t"
+ " BNE RegTest2Error \n\t"
+ " MVFACMI R15 \n\t"
+ " CMP #0x33334444, R15 \n\t"
+ " BNE RegTest2Error \n\t"
+ " \n\t"
+ /* Restore the clobbered registers. */
+ " POPM R14-R15 \n\t"
+ " \n\t"
+ /* Now compare each register to ensure it still contains the value that
+ was set before this loop was entered. */
+ " CMP #1, R1 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #2, R2 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #3, R3 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #4, R4 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #5, R5 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #6, R6 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #7, R7 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #8, R8 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #9, R9 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #10, R10 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #11, R11 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #12, R12 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #13, R13 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #14, R14 \n\t"
+ " BNE RegTest1Error \n\t"
+ " CMP #15, R15 \n\t"
+ " BNE RegTest1Error \n\t"
+ " \n\t"
+ /* All comparisons passed, start a new iteration of this loop. */
+ " BRA TestLoop1 \n\t"
+ " \n\t"
+ /* A compare failed, just loop here so the loop counter stops
+ incrementing causing the check timer to indicate the error. */
+ "RegTest1Error: \n\t"
+ " BRA RegTest1Error "
+ );
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest2Implementation( void )
+{
+ __asm volatile
+ (
+ /* Set each register to a known value. */
+ " MOV.L #0x11111111, R15 \n\t"
+ " MVTACHI R15 \n\t"
+ " MOV.L #0x22222222, R15 \n\t"
+ " MVTACLO R15 \n\t"
+ " MOV.L #100, R1 \n\t"
+ " MOV.L #200, R2 \n\t"
+ " MOV.L #300, R3 \n\t"
+ " MOV.L #400, R4 \n\t"
+ " MOV.L #500, R5 \n\t"
+ " MOV.L #600, R6 \n\t"
+ " MOV.L #700, R7 \n\t"
+ " MOV.L #800, R8 \n\t"
+ " MOV.L #900, R9 \n\t"
+ " MOV.L #1000, R10 \n\t"
+ " MOV.L #1001, R11 \n\t"
+ " MOV.L #1002, R12 \n\t"
+ " MOV.L #1003, R13 \n\t"
+ " MOV.L #1004, R14 \n\t"
+ " MOV.L #1005, R15 \n\t"
+ " \n\t"
+ /* Loop, checking each iteration that each register still contains the
+ expected value. */
+ "TestLoop2: \n\t"
+ " \n\t"
+ /* Push the registers that are going to get clobbered. */
+ " PUSHM R14-R15 \n\t"
+ " \n\t"
+ /* Increment the loop counter to show this task is still getting CPU
+ time. */
+ " MOV.L #_ulRegTest2CycleCount, R14 \n\t"
+ " MOV.L [ R14 ], R15 \n\t"
+ " ADD #1, R15 \n\t"
+ " MOV.L R15, [ R14 ] \n\t"
+ " \n\t"
+ /* Check the accumulator value. */
+ " MVFACHI R15 \n\t"
+ " CMP #0x11111111, R15 \n\t"
+ " BNE RegTest2Error \n\t"
+ " MVFACMI R15 \n\t"
+ " CMP #0x11112222, R15 \n\t"
+ " BNE RegTest2Error \n\t"
+ " \n\t"
+ /* Restore the clobbered registers. */
+ " POPM R14-R15 \n\t"
+ " \n\t"
+ /* Now compare each register to ensure it still contains the value that
+ was set before this loop was entered. */
+ " CMP #100, R1 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #200, R2 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #300, R3 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #400, R4 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #500, R5 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #600, R6 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #700, R7 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #800, R8 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #900, R9 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #1000, R10 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #1001, R11 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #1002, R12 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #1003, R13 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #1004, R14 \n\t"
+ " BNE RegTest2Error \n\t"
+ " CMP #1005, R15 \n\t"
+ " BNE RegTest2Error \n\t"
+ " \n\t"
+ /* All comparisons passed, start a new iteration of this loop. */
+ " BRA TestLoop2 \n\t"
+ " \n\t"
+ /* A compare failed, just loop here so the loop counter stops
+ incrementing causing the check timer to indicate the error. */
+ "RegTest2Error: \n\t"
+ " BRA RegTest2Error "
+ );
+}
+/*-----------------------------------------------------------*/
+
+#endif /* configCREATE_LOW_POWER_DEMO */
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c
new file mode 100644
index 000000000..a69396058
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/main_low_power.c
@@ -0,0 +1,436 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* ****************************************************************************
+ * When configCREATE_LOW_POWER_DEMO is set to 1 in FreeRTOSConfig.h main() will
+ * call main_low_power(), which is defined in this file. main_low_power()
+ * demonstrates FreeRTOS tick suppression being used to allow the MCU to be
+ * placed into both the low power deep sleep mode and the low power software
+ * standby mode. When configCREATE_LOW_POWER_DEMO is set to 0 main will
+ * instead call main_full(), which is a more comprehensive RTOS demonstration.
+ * ****************************************************************************
+ *
+ * This application demonstrates the FreeRTOS tickless idle mode (tick
+ * suppression). See http://www.freertos.org/low-power-tickless-rtos.html
+ * The demo is configured to execute on the Renesas RX100 RSK.
+ *
+ * Functionality:
+ *
+ * + Two tasks are created, an Rx task and a Tx task.
+ *
+ * + The Rx task repeatedly blocks on a queue to wait for data. The Rx task
+ * toggles LED 0 each time is receives a value from the queue.
+ *
+ * + The Tx task repeatedly enters the Blocked state for an amount of time
+ * that is set by the position of the potentiometer. On exiting the blocked
+ * state the Tx task sends a value through the queue to the Rx task (causing
+ * the Rx task to exit the blocked state and toggle LED 0).
+ *
+ * If the value read from the potentiometer is less than or equal to
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks for the equivalent
+ * number of milliseconds. For example, if the sampled analog value is
+ * 2000, then the Tx task blocks for 2000ms. Blocking for a finite period
+ * allows the kernel to stop the tick interrupt and place the RX100 into
+ * deep sleep mode.
+ *
+ * If the value read form the potentiometer is greater than
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks on a semaphore with
+ * an infinite timeout. Blocking with an infinite timeout allows the kernel
+ * to stop the tick interrupt and place the RX100 into software standby
+ * mode. Pressing a button will generate an interrupt that causes the RX100
+ * to exit software standby mode. The interrupt service routine 'gives' the
+ * semaphore to unblock the Tx task.
+ *
+ *
+ * Using the Demo and Observed Behaviour:
+ *
+ * 1) Turn the potentiometer completely counter clockwise.
+ *
+ * 2) Program the RX100 with the application, then disconnect the programming/
+ * debugging hardware to ensure power readings are not effected by any
+ * connected interfaces.
+ *
+ * 3) Start the application running. LED 0 will toggle quickly because the
+ * potentiometer is turned to its lowest value. LED 1 will be illuminated
+ * when the RX100 is not in a power saving mode, but will appear to be off
+ * because most execution time is spent in a sleep mode. Led 2 will be
+ * illuminated when the RX100 is in deep sleep mode, and will appear to be
+ * always on, again because most execution time is spent in deep sleep mode.
+ * The LEDs are turned on and off by the application defined pre and post
+ * sleep macros (see the definitions of configPRE_SLEEP_PROCESSING() and
+ * configPOST_SLEEP_PROCESSING() in FreeRTOSConfig.h).
+ *
+ * 4) Slowly turn the potentiometer in the clockwise direction. This will
+ * increase the value read from the potentiometer, which will increase the
+ * time the Tx task spends in the Blocked state, which will therefore
+ * decrease the frequency at which the Tx task sends data to the queue (and
+ * the rate at which LED 0 is toggled).
+ *
+ * 5) Keep turning the potentiometer in the clockwise direction. Eventually
+ * the value read from the potentiometer will go above
+ * mainSOFTWARE_STANDBY_DELAY, causing the Tx task to block on the semaphore
+ * with an infinite timeout. LED 0 will stop toggling because the Tx task is
+ * no longer sending to the queue. LED 1 and LED 2 will both be off because
+ * the RX100 is neither running or in deep sleep mode (it is in software
+ * standby mode).
+ *
+ * 6) Turn the potentiometer counter clockwise again to ensure its value goes
+ * back below mainSOFTWARE_STANDBY_DELAY.
+ *
+ * 7) Press any of the three buttons to generate an interrupt. The interrupt
+ * will take the RX100 out of software standby mode, and the interrupt
+ * service routine will unblock the Tx task by 'giving' the semaphore. LED 0
+ * will then start to toggle again.
+ *
+ */
+
+
+/* Hardware specific includes. */
+#include "platform.h"
+#include "r_switches_if.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Common demo includes. */
+#include "partest.h"
+
+/* Priorities at which the Rx and Tx tasks are created. */
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+
+/* The number of items the queue can hold. This is 1 as the Rx task will
+remove items as they are added so the Tx task should always find the queue
+empty. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/* The LED used to indicate that a value has been received on the queue. */
+#define mainQUEUE_LED ( 0 )
+
+/* The LED used to indicate that full power is being used (the MCU is not in
+deep sleep or software standby mode). */
+#define mainFULL_POWER_LED ( 1 )
+
+/* The LED used to indicate that deep sleep mode is being used. */
+#define mainDEEP_SLEEP_LED ( 2 )
+
+/* The Tx task sends to the queue with a frequency that is set by the value
+read from the potentiometer until the value goes above that set by the
+mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks
+indefinitely on a semaphore. */
+#define mainSOFTWARE_STANDBY_DELAY ( 3000UL )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK ( 0 )
+
+/* The value that is sent from the Tx task to the Rx task on the queue. */
+#define mainQUEUED_VALUE ( 100UL )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The Rx and Tx tasks as described at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Reads and returns the value of the ADC connected to the potentiometer built
+ * onto the RSK.
+ */
+static unsigned short prvReadPOT( void );
+
+/*
+ * The handler for the interrupt generated when any of the buttons are pressed.
+ */
+void vButtonInterrupt( void ) __attribute__((interrupt));
+
+/*-----------------------------------------------------------*/
+
+/* The queue to pass data from the Tx task to the Rx task. */
+static xQueueHandle xQueue = NULL;
+
+/* The semaphore that is 'given' by interrupts generated from button pushes. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_low_power( void )
+{
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+ configASSERT( xQueue );
+
+ /* Create the semaphore that is 'given' by an interrupt generated from a
+ button push. */
+ vSemaphoreCreateBinary( xSemaphore );
+ configASSERT( xSemaphore );
+
+ /* Make sure the semaphore starts in the expected state - no button pushes
+ have yet occurred. A block time of zero can be used as it is guaranteed
+ that the semaphore will be available because it has just been created. */
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );
+
+ /* Start the two tasks as described at the top of this file. */
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* The CPU is currently running, not sleeping, so turn on the LED that
+ shows the CPU is not in a sleep mode. */
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );
+
+ /* Start the scheduler running running. */
+ vTaskStartScheduler();
+
+ /* If all is well the next line of code will not be reached as the
+ scheduler will be running. If the next line is reached then it is likely
+ there was insufficient FreeRTOS heap available for the idle task and/or
+ timer task to be created. See http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xDelay;
+const unsigned long ulValueToSend = mainQUEUED_VALUE;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* The delay period between successive sends to the queue is set by
+ the potentiometer reading. */
+ xDelay = ( portTickType ) prvReadPOT();
+
+ /* If the block time is greater than 3000 milliseconds then block
+ indefinitely waiting for a button push. */
+ if( xDelay > mainSOFTWARE_STANDBY_DELAY )
+ {
+ /* As this is an indefinite delay the kernel will place the CPU
+ into software standby mode the next time the idle task runs. */
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );
+ }
+ else
+ {
+ /* Convert a time in milliseconds to a time in ticks. */
+ xDelay /= portTICK_RATE_MS;
+
+ /* Place this task in the blocked state until it is time to run
+ again. As this is not an indefinite sleep the kernel will place
+ the CPU into the deep sleep state when the idle task next runs. */
+ vTaskDelay( xDelay );
+ }
+
+ /* Send to the queue - causing the queue receive task to flash its LED.
+ It should not be necessary to block on the queue send because the Rx
+ task will have removed the last queued item. */
+ xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have arrived, but is it the expected
+ value? If it is, toggle the LED. */
+ if( ulReceivedValue == mainQUEUED_VALUE )
+ {
+ vParTestToggleLED( mainQUEUE_LED );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPreSleepProcessing( unsigned long ulExpectedIdleTime )
+{
+ /* Called by the kernel before it places the MCU into a sleep mode because
+ configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing().
+
+ NOTE: Additional actions can be taken here to get the power consumption
+ even lower. For example, the ADC input used by this demo could be turned
+ off here, and then back on again in the power sleep processing function.
+ For maximum power saving ensure all unused pins are in their lowest power
+ state. */
+
+ /* Avoid compiler warnings about the unused parameter. */
+ ( void ) ulExpectedIdleTime;
+
+ /* Is the MCU about to enter deep sleep mode or software standby mode? */
+ if( SYSTEM.SBYCR.BIT.SSBY == 0 )
+ {
+ /* Turn on the LED that indicates deep sleep mode is being entered. */
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE );
+ }
+ else
+ {
+ /* Software standby mode is being used, so no LEDs are illuminated to
+ ensure minimum power readings are obtained. Ensure the Queue LED is
+ also off. */
+ vParTestSetLED( mainQUEUE_LED, pdFALSE );
+ }
+
+ /* Turn off the LED that indicates full power is being used. */
+ vParTestSetLED( mainFULL_POWER_LED, pdFALSE );
+}
+/*-----------------------------------------------------------*/
+
+void vPostSleepProcessing( unsigned long ulExpectedIdleTime )
+{
+ /* Called by the kernel when the MCU exits a sleep mode because
+ configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */
+
+ /* Avoid compiler warnings about the unused parameter. */
+ ( void ) ulExpectedIdleTime;
+
+ /* Turn off the LED that indicates deep sleep mode, and turn on the LED
+ that indicates full power is being used. */
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE );
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+static unsigned short prvReadPOT( void )
+{
+unsigned short usADCValue;
+const unsigned short usMinADCValue = 128;
+
+ /* Start an ADC scan. */
+ S12AD.ADCSR.BIT.ADST = 1;
+ while( S12AD.ADCSR.BIT.ADST == 1 )
+ {
+ /* Just waiting for the ADC scan to complete. Inefficient
+ polling! */
+ }
+
+ usADCValue = S12AD.ADDR4;
+
+ /* Don't let the ADC value get too small as the LED behaviour will look
+ erratic. */
+ if( usADCValue < usMinADCValue )
+ {
+ usADCValue = usMinADCValue;
+ }
+
+ return usADCValue;
+}
+/*-----------------------------------------------------------*/
+
+void vButtonInterrupt( void )
+{
+long lHigherPriorityTaskWoken = pdFALSE;
+
+ /* The semaphore is only created when the build is configured to create the
+ low power demo. */
+ if( xSemaphore != NULL )
+ {
+ /* This interrupt will bring the CPU out of deep sleep and software
+ standby modes. Give the semaphore that was used to place the Tx task
+ into an indefinite sleep. */
+ if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )
+ {
+ xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );
+ }
+ else
+ {
+ /* The semaphore was already available, so the task is not blocked
+ on it and there is no point giving it. */
+ }
+
+ /* If giving the semaphore caused a task to leave the Blocked state,
+ and the task that left the Blocked state has a priority equal to or
+ above the priority of the task that this interrupt interrupted, then
+ lHigherPriorityTaskWoken will have been set to pdTRUE inside the call
+ to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause
+ a context switch to the unblocked task. */
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
+ }
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/printf-stdarg.c b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/printf-stdarg.c
new file mode 100644
index 000000000..b5ac41be7
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo/printf-stdarg.c
@@ -0,0 +1,293 @@
+/*
+ Copyright 2001, 2002 Georges Menie (www.menie.org)
+ stdarg version contributed by Christian Ettinger
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+/*
+ putchar is the only external dependency for this file,
+ if you have a working putchar, leave it commented out.
+ If not, uncomment the define below and
+ replace outbyte(c) by your own function call.
+
+*/
+
+#define putchar(c) c
+
+#include
+
+static void printchar(char **str, int c)
+{
+ //extern int putchar(int c);
+
+ if (str) {
+ **str = (char)c;
+ ++(*str);
+ }
+ else
+ {
+ (void)putchar(c);
+ }
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad)
+{
+ register int pc = 0, padchar = ' ';
+
+ if (width > 0) {
+ register int len = 0;
+ register const char *ptr;
+ for (ptr = string; *ptr; ++ptr) ++len;
+ if (len >= width) width = 0;
+ else width -= len;
+ if (pad & PAD_ZERO) padchar = '0';
+ }
+ if (!(pad & PAD_RIGHT)) {
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+ }
+ for ( ; *string ; ++string) {
+ printchar (out, *string);
+ ++pc;
+ }
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+
+ return pc;
+}
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
+{
+ char print_buf[PRINT_BUF_LEN];
+ register char *s;
+ register int t, neg = 0, pc = 0;
+ register unsigned int u = (unsigned int)i;
+
+ if (i == 0) {
+ print_buf[0] = '0';
+ print_buf[1] = '\0';
+ return prints (out, print_buf, width, pad);
+ }
+
+ if (sg && b == 10 && i < 0) {
+ neg = 1;
+ u = (unsigned int)-i;
+ }
+
+ s = print_buf + PRINT_BUF_LEN-1;
+ *s = '\0';
+
+ while (u) {
+ t = (unsigned int)u % b;
+ if( t >= 10 )
+ t += letbase - '0' - 10;
+ *--s = (char)(t + '0');
+ u /= b;
+ }
+
+ if (neg) {
+ if( width && (pad & PAD_ZERO) ) {
+ printchar (out, '-');
+ ++pc;
+ --width;
+ }
+ else {
+ *--s = '-';
+ }
+ }
+
+ return pc + prints (out, s, width, pad);
+}
+
+static int print( char **out, const char *format, va_list args )
+{
+ register int width, pad;
+ register int pc = 0;
+ char scr[2];
+
+ for (; *format != 0; ++format) {
+ if (*format == '%') {
+ ++format;
+ width = pad = 0;
+ if (*format == '\0') break;
+ if (*format == '%') goto out;
+ if (*format == '-') {
+ ++format;
+ pad = PAD_RIGHT;
+ }
+ while (*format == '0') {
+ ++format;
+ pad |= PAD_ZERO;
+ }
+ for ( ; *format >= '0' && *format <= '9'; ++format) {
+ width *= 10;
+ width += *format - '0';
+ }
+ if( *format == 's' ) {
+ register char *s = (char *)va_arg( args, int );
+ pc += prints (out, s?s:"(null)", width, pad);
+ continue;
+ }
+ if( *format == 'd' ) {
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'x' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'X' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
+ continue;
+ }
+ if( *format == 'u' ) {
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'c' ) {
+ /* char are converted to int then pushed on the stack */
+ scr[0] = (char)va_arg( args, int );
+ scr[1] = '\0';
+ pc += prints (out, scr, width, pad);
+ continue;
+ }
+ }
+ else {
+ out:
+ printchar (out, *format);
+ ++pc;
+ }
+ }
+ if (out) **out = '\0';
+ va_end( args );
+ return pc;
+}
+
+int printf(const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( 0, format, args );
+}
+
+int sprintf(char *out, const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( &out, format, args );
+}
+
+
+int snprintf( char *buf, unsigned int count, const char *format, ... )
+{
+ va_list args;
+
+ ( void ) count;
+
+ va_start( args, format );
+ return print( &buf, format, args );
+}
+
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+ char *ptr = "Hello world!";
+ char *np = 0;
+ int i = 5;
+ unsigned int bs = sizeof(int)*8;
+ int mi;
+ char buf[80];
+
+ mi = (1 << (bs-1)) + 1;
+ printf("%s\n", ptr);
+ printf("printf test\n");
+ printf("%s is null pointer\n", np);
+ printf("%d = 5\n", i);
+ printf("%d = - max int\n", mi);
+ printf("char %c = 'a'\n", 'a');
+ printf("hex %x = ff\n", 0xff);
+ printf("hex %02x = 00\n", 0);
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+ printf("%d %s(s)%", 0, "message");
+ printf("\n");
+ printf("%d %s(s) with %%\n", 0, "message");
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
+
+ return 0;
+}
+
+/*
+ * if you compile this file with
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
+ * you will get a normal warning:
+ * printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ * printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left "
+ * justif: " right"
+ * 3: 0003 zero padded
+ * 3: 3 left justif.
+ * 3: 3 right justif.
+ * -3: -003 zero padded
+ * -3: -3 left justif.
+ * -3: -3 right justif.
+ */
+
+#endif
+
+
+/* To keep linker happy. */
+int write( int i, char* c, int n)
+{
+ (void)i;
+ (void)n;
+ (void)c;
+ return 0;
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch
new file mode 100644
index 000000000..6bbe77a1a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch
@@ -0,0 +1,78 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/custom.bat b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/custom.bat
new file mode 100644
index 000000000..e69de29bb
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h
new file mode 100644
index 000000000..3fb787a99
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/FreeRTOSConfig.h
@@ -0,0 +1,183 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/* Hardware specifics. */
+#include "platform.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* DEMO SPECIFIC SETTING:
+ * Set configCREATE_LOW_POWER_DEMO to one to run the low power demo with tick
+ * suppression, or 0 to run the more comprehensive test and demo application.
+ * If configCREATE_LOW_POWER_DEMO is set to 1 then main() calls main_low_power().
+ * If configCREATE_LOW_POWER_DEMO is set to 0 then main() calls main_full().
+ */
+#define configCREATE_LOW_POWER_DEMO 1
+
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE configCREATE_LOW_POWER_DEMO
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( ICLK_HZ ) /* Set in mcu_info.h. */
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_HZ ) /* Set in muc_info.h. */
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 9 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions - only included when the demo is configured to
+build the full demo (as opposed to the low power demo). */
+#if configCREATE_LOW_POWER_DEMO == 1
+ #define configUSE_TIMERS 0
+#else
+ #define configUSE_TIMERS 1
+ #define configTIMER_TASK_PRIORITY ( 3 )
+ #define configTIMER_QUEUE_LENGTH 5
+ #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
+#endif /* configCREATE_LOW_POWER_DEMO */
+
+/*
+The interrupt priority used by the kernel itself for the tick interrupt and
+the pended interrupt is set by configKERNEL_INTERRUPT_PRIORITY. This would
+normally be the lowest priority (1 in this case). The maximum interrupt
+priority from which FreeRTOS API calls can be made is set by
+configMAX_SYSCALL_INTERRUPT_PRIORITY. Interrupts that use a priority above this
+will not be effected by anything the kernel is doing. Interrupts at or below
+this priority can use FreeRTOS API functions - but *only* those that end in
+"FromISR". Both these constants are defined in 'PriorityDefinitions.h' so they
+can also be included in assembly source files.
+*/
+#include "PriorityDefinitions.h"
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+
+extern void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled();
+
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros
+allow the application writer to add additional code before and after the MCU is
+placed into the low power state respectively. The implementations provided in
+this demo can be extended to save even more power - for example the analog
+input used by the low power demo could be switched off in the pre-sleep macro
+and back on again in the post sleep macro. */
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );
+
+/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral
+that generates the tick interrupt. */
+#define configTICK_VECTOR VECT_CMT0_CMI0
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c b/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c
new file mode 100644
index 000000000..827da190d
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/ParTest.c
@@ -0,0 +1,200 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/*-----------------------------------------------------------
+ * Simple IO routines to control the LEDs.
+ *-----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo includes. */
+#include "partest.h"
+
+#define partestNUM_LEDS ( 4 )
+
+long lParTestGetLEDState( unsigned long ulLED );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+ /* Port pin configuration is done by the low level set up prior to this
+ function being called. */
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned long ulLED, signed long xValue )
+{
+ if( ulLED < partestNUM_LEDS )
+ {
+ if( xValue != 0 )
+ {
+ /* Turn the LED on. */
+ taskENTER_CRITICAL();
+ {
+ switch( ulLED )
+ {
+ case 0: LED0 = LED_ON;
+ break;
+ case 1: LED1 = LED_ON;
+ break;
+ case 2: LED2 = LED_ON;
+ break;
+ case 3: LED3 = LED_ON;
+ break;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ /* Turn the LED off. */
+ taskENTER_CRITICAL();
+ {
+ switch( ulLED )
+ {
+ case 0: LED0 = LED_OFF;
+ break;
+ case 1: LED1 = LED_OFF;
+ break;
+ case 2: LED2 = LED_OFF;
+ break;
+ case 3: LED3 = LED_OFF;
+ break;
+ }
+
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned long ulLED )
+{
+ if( ulLED < partestNUM_LEDS )
+ {
+ taskENTER_CRITICAL();
+ {
+ if( lParTestGetLEDState( ulLED ) != 0x00 )
+ {
+ vParTestSetLED( ulLED, 0 );
+ }
+ else
+ {
+ vParTestSetLED( ulLED, 1 );
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+/*-----------------------------------------------------------*/
+
+long lParTestGetLEDState( unsigned long ulLED )
+{
+long lReturn = pdTRUE;
+
+ if( ulLED < partestNUM_LEDS )
+ {
+ switch( ulLED )
+ {
+ case 0 : if( LED0 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 1 : if( LED1 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 2 : if( LED2 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 3 : if( LED3 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ }
+ }
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h b/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h
new file mode 100644
index 000000000..a530b5ca5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/PriorityDefinitions.h
@@ -0,0 +1,91 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+#ifndef PRIORITY_DEFINITIONS_H
+#define PRIORITY_DEFINITIONS_H
+
+
+/* The interrupt priority used by the kernel itself for the tick interrupt and
+the pended interrupt. This would normally be the lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY 1
+
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.
+Interrupts that use a priority above this will not be effected by anything the
+kernel is doing but must not make any use of FreeRTOS functionality.
+interrupts that use a priority at or below configMAX_SYSCALL_INTERRUPT_PRIORITY
+can make use of FreeRTOS API function but *only* functions that end in
+"FromISR()". */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+#endif /* PRIORITY_DEFINITIONS_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.dep b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.dep
new file mode 100644
index 000000000..e4be4cfe6
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.dep
@@ -0,0 +1,398 @@
+
+
+
+ 2
+ 1022944783
+
+ Debug
+
+ $PROJ_DIR$\Debug\Obj\reg_test.o
+ $PROJ_DIR$\..\..\Source\include\queue.h
+ $PROJ_DIR$\..\..\Source\include\FreeRTOS.h
+ $PROJ_DIR$\..\..\Source\include\projdefs.h
+ $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c
+ $PROJ_DIR$\Debug\Obj\port.pbi
+ $PROJ_DIR$\Debug\Obj\heap_4.pbi
+ $PROJ_DIR$\Debug\Obj\blocktim.pbi
+ $PROJ_DIR$\Debug\Obj\queue.pbi
+ $PROJ_DIR$\Debug\Obj\port_asm.o
+ $PROJ_DIR$\Debug\Obj\ParTest.o
+ $PROJ_DIR$\Debug\Obj\GenQTest.o
+ $TOOLKIT_DIR$\inc\c\yvals.h
+ $PROJ_DIR$\Debug\Obj\main.pbi
+ $PROJ_DIR$\Debug\Obj\lcd.o
+ $PROJ_DIR$\Debug\Obj\list.pbi
+ $PROJ_DIR$\Debug\Obj\blocktim.o
+ $PROJ_DIR$\Debug\Obj\death.o
+ $PROJ_DIR$\Debug\Obj\hardware_setup.o
+ $PROJ_DIR$\FreeRTOSConfig.h
+ $PROJ_DIR$\main.c
+ $PROJ_DIR$\main_full.c
+ $PROJ_DIR$\main_low_power.c
+ $PROJ_DIR$\ParTest.c
+ $PROJ_DIR$\reg_test.s
+ $PROJ_DIR$\Debug\Obj\main_low_power.o
+ $PROJ_DIR$\Debug\Obj\timers.o
+ $PROJ_DIR$\Debug\Obj\list.o
+ $TOOLKIT_DIR$\inc\c\DLib_Defaults.h
+ $TOOLKIT_DIR$\inc\DLib_Product.h
+ $TOOLKIT_DIR$\inc\c\ycheck.h
+ $TOOLKIT_DIR$\inc\c\xencoding_limits.h
+ $TOOLKIT_DIR$\inc\c\DLib_Threads.h
+ $PROJ_DIR$\Renesas_Files\r_bsp\platform.h
+ $PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\r_bsp.h
+ $TOOLKIT_DIR$\inc\c\stddef.h
+ $TOOLKIT_DIR$\inc\c\ysizet.h
+ $TOOLKIT_DIR$\inc\c\stdint.h
+ $PROJ_DIR$\Renesas_Files\r_bsp\r_bsp_config.h
+ $PROJ_DIR$\Renesas_Files\r_bsp\mcu\rx111\mcu_info.h
+ $PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\lcd.h
+ $PROJ_DIR$\..\..\Source\include\portable.h
+ $PROJ_DIR$\Debug\Obj\tasks.pbi
+ $PROJ_DIR$\Debug\Obj\timers.pbi
+ $PROJ_DIR$\Debug\Obj\lcd.pbi
+ $PROJ_DIR$\Debug\Obj\queue.o
+ $PROJ_DIR$\Debug\Obj\main_full.pbi
+ $PROJ_DIR$\Debug\Obj\main_low_power.pbi
+ $PROJ_DIR$\Debug\Exe\templproj.out
+ $PROJ_DIR$\Debug\Obj\RTOSDemo_IAR.pbd
+ $TOOLKIT_DIR$\inc\c\limits.h
+ $PROJ_DIR$\PriorityDefinitions.h
+ $PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\rskrx111.h
+ $PROJ_DIR$\Debug\Obj\heap_4.o
+ $TOOLKIT_DIR$\inc\intrinsics.h
+ $TOOLKIT_DIR$\inc\iorx111.h
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+ $PROJ_DIR$\Debug\Obj\tasks.o
+ $TOOLKIT_DIR$\lib\dlrxfllsn.h
+ $PROJ_DIR$\..\..\Source\include\mpu_wrappers.h
+ $TOOLKIT_DIR$\inc\c\string.h
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+ $TOOLKIT_DIR$\inc\c\stdlib.h
+ $TOOLKIT_DIR$\inc\machine.h
+ $PROJ_DIR$\..\..\Source\include\task.h
+ $PROJ_DIR$\..\..\Source\include\timers.h
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+ $PROJ_DIR$\..\..\Source\portable\IAR\RX100\portmacro.h
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+ $TOOLKIT_DIR$\inc\c\stdio.h
+ $PROJ_DIR$\Renesas_Files\r_switches\r_switches_config.h
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diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.ewd b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.ewd
new file mode 100644
index 000000000..91508e074
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.ewd
@@ -0,0 +1,312 @@
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diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.ewp b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.ewp
new file mode 100644
index 000000000..57000a6b0
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+++ b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.ewp
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 1
+
+ 0
+ 1
+ 1
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ FreeRTOS Source
+
+ include
+
+ $PROJ_DIR$\..\..\Source\include\FreeRTOS.h
+
+
+ $PROJ_DIR$\..\..\Source\include\projdefs.h
+
+
+ $PROJ_DIR$\..\..\Source\include\queue.h
+
+
+ $PROJ_DIR$\..\..\Source\include\semphr.h
+
+
+ $PROJ_DIR$\..\..\Source\include\task.h
+
+
+ $PROJ_DIR$\..\..\Source\include\timers.h
+
+
+
+ portable
+
+ IAR
+
+ RX100
+
+ $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c
+
+
+ $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s
+
+
+ $PROJ_DIR$\..\..\Source\portable\IAR\RX100\portmacro.h
+
+
+
+
+ MemMang
+
+ $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c
+
+
+
+
+ $PROJ_DIR$\..\..\Source\list.c
+
+
+ $PROJ_DIR$\..\..\Source\queue.c
+
+
+ $PROJ_DIR$\..\..\Source\tasks.c
+
+
+ $PROJ_DIR$\..\..\Source\timers.c
+
+
+
+ Renesas Files
+
+ $PROJ_DIR$\Renesas_Files\r_bsp\board\user\hardware_setup.c
+
+
+ $PROJ_DIR$\Renesas_Files\r_bsp\board\rskrx111\lcd.c
+
+
+ $PROJ_DIR$\Renesas_Files\r_switches\src\r_switches.c
+
+
+
+ Standard Demo Tasks
+
+ $PROJ_DIR$\..\Common\Minimal\blocktim.c
+
+
+ $PROJ_DIR$\..\Common\Minimal\death.c
+
+
+ $PROJ_DIR$\..\Common\Minimal\GenQTest.c
+
+
+ $PROJ_DIR$\..\Common\Minimal\recmutex.c
+
+
+
+ $PROJ_DIR$\FreeRTOSConfig.h
+
+
+ $PROJ_DIR$\main.c
+
+
+ $PROJ_DIR$\main_full.c
+
+
+ $PROJ_DIR$\main_low_power.c
+
+
+ $PROJ_DIR$\ParTest.c
+
+
+ $PROJ_DIR$\reg_test.s
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.eww b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.eww
new file mode 100644
index 000000000..f4971a444
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IAR.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\RTOSDemo_IAR.ewp
+
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IARCustomSfr.sfr b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IARCustomSfr.sfr
new file mode 100644
index 000000000..5ac9e8be2
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/RTOSDemo_IARCustomSfr.sfr
@@ -0,0 +1,4 @@
+[Sfr]
+
+
+[SfrGroupInfo]
\ No newline at end of file
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/lcd.c b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/lcd.c
new file mode 100644
index 000000000..a904f76d5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/lcd.c
@@ -0,0 +1,252 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lcd.c
+* Device(s) : RX
+* H/W Platform : RSKRX111
+* Description : Provides variable and function declarations for lcd.c file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Standard string manipulation & formatting functions */
+#include
+#include
+/* Defines standard variable types used in this function */
+#include
+/* Bring in board includes. */
+#include "platform.h"
+/* Following header file provides function prototypes for LCD controlling functions & macro defines */
+#include "lcd.h"
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+static void lcd_delay(volatile int32_t nsecs);
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value);
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value);
+
+/***********************************************************************************************************************
+* Function name : lcd_initialize
+* Description : Initializes the LCD display.
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_initialize(void)
+{
+ /* Set LCD data pins as outputs. */
+ PORT4.PDR.BYTE |= 0x0F;
+
+ /* Set LCD control pins as outputs. */
+ RS_PIN_DDR = 1;
+ E_PIN_DDR = 1;
+
+ /* Power Up Delay for the LCD Module */
+ lcd_delay(50000000);
+
+ /* Display initialises in 8 bit mode - so send one write (seen as 8 bit) to set to 4 bit mode. */
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+
+ /* Function Set */
+ lcd_nibble_write(CTRL_WR, 0x02);
+ lcd_delay(39000);
+ lcd_nibble_write(CTRL_WR, 0x02);
+ lcd_nibble_write(CTRL_WR, (LCD_DISPLAY_ON | LCD_TWO_LINE ));
+ lcd_delay(39000);
+
+ /* Display ON/OFF control */
+ lcd_write(CTRL_WR, LCD_CURSOR_OFF);
+ lcd_delay(39000);
+
+ /* Display Clear */
+ lcd_write(CTRL_WR, LCD_CLEAR);
+ lcd_delay(2000000);
+
+ /* Entry Mode Set */
+ lcd_write(CTRL_WR, 0x06);
+ lcd_delay(39000);
+
+ /* Home the cursor */
+ lcd_write(CTRL_WR, LCD_HOME_L1);
+ lcd_delay(5000000);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_clear
+* Description : Clears the LCD
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_clear(void)
+{
+ /* Display Clear */
+ lcd_write(CTRL_WR, LCD_CLEAR);
+ lcd_delay(2000000);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_display
+* Description : This function controls LCD writes to line 1 or 2 of the LCD.
+* You need to use the defines LCD_LINE1 and LCD_LINE2 in order to specify the starting position.
+* For example, to start at the 2nd position on line 1...
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : position -
+* Line number of display
+* string -
+* Pointer to null terminated string
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_display(uint8_t position, uint8_t const * string)
+{
+ /* Declare next position variable */
+ static uint8_t next_pos = 0xFF;
+
+ /* Set line position if needed. We don't want to if we don't need to because LCD control operations take longer
+ than LCD data operations. */
+ if (next_pos != position)
+ {
+ if(position < LCD_LINE2)
+ {
+ /* Display on Line 1 */
+ lcd_write(CTRL_WR, ((uint8_t)(LCD_HOME_L1 + position)));
+ }
+ else
+ {
+ /* Display on Line 2 */
+ lcd_write(CTRL_WR, ((uint8_t)((LCD_HOME_L2 + position) - LCD_LINE2)));
+ }
+
+ lcd_delay(39000);
+
+ /* set position index to known value */
+ next_pos = position;
+ }
+
+ do
+ {
+ /* Write character to LCD. */
+ lcd_write(DATA_WR,*string++);
+
+ lcd_delay(43000);
+
+ /* Increment position index */
+ next_pos++;
+ }
+ while(*string);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_delay
+* Description : Implements LCD required delays.
+* Arguments : nsecs -
+* Number of nanoseconds to delay. RX111 has max clock of 32MHz which gives a cycle time of 31.3ns.
+* This means that nothing under 313ns should be input. 313ns would be 10 cycles which is still
+* being optimistic for getting in and out of this function.
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_delay(volatile int32_t nsecs)
+{
+ while (0 < nsecs)
+ {
+ /* Subtract off 10 cycles per iteration. This number was obtained when using the Renesas toolchain at
+ optimization level 2. The number to nanoseconds to subtract off below is calculated off of the ICLK speed. */
+ nsecs -= (int32_t)((313.0)*(32000000.0/(float)ICLK_HZ));
+ }
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_nibble_write
+* Description : Writes data to display. Sends command to display.
+* Arguments : value -
+* The value to write
+* data_or_ctrl -
+* Whether to write data or control.
+* 1 = DATA
+* 0 = CONTROL
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value)
+{
+ /* Set Register Select pin high for Data */
+ if (data_or_ctrl == DATA_WR)
+ {
+ /* Data write. */
+ RS_PIN = 1;
+ }
+ else
+ {
+ /* Control write. */
+ RS_PIN = 0;
+ }
+
+ /* tsu1 delay */
+ lcd_delay(60);
+
+ /* EN enable chip (HIGH) */
+ E_PIN = 1;
+
+ /* Output the data */
+ PORT4.PODR.BYTE = (value & 0x0F);
+
+ /* tw delay */
+ lcd_delay(450);
+
+ /* Latch data by dropping E */
+ E_PIN = 0;
+
+ /* th2 delay */
+ lcd_delay(10);
+
+ /* tc delay */
+ lcd_delay(480);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_write
+* Description : This function controls LCD writes to line 1 or 2 of the LCD. You need to use the defines LCD_LINE1 and
+* LCD_LINE2 in order to specify the starting position.
+* For example, to start at the 2nd position on line 1...
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : value -
+* The value to write
+* data_or_ctrl -
+* Whether to write data or control.
+* 1 = DATA
+* 0 = CONTROL
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value)
+{
+ /* Write upper nibble first */
+ lcd_nibble_write(data_or_ctrl, (uint8_t)((value & 0xF0) >> 4));
+
+ /* Write lower nibble second */
+ lcd_nibble_write(data_or_ctrl, (uint8_t)(value & 0x0F));
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/lcd.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/lcd.h
new file mode 100644
index 000000000..7a57f77d2
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/lcd.h
@@ -0,0 +1,101 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lcd.h
+* Device(s) : RX
+* H/W Platform : RSKRX111
+* Description : Provides variable and function declarations for lcd.c file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/* Multiple inclusion prevention macro */
+#ifndef LCD_H
+#define LCD_H
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Defines standard integer variable types used in this file */
+#include
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* RS register select pin */
+#define RS_PIN PORTC.PODR.BIT.B5
+#define RS_PIN_DDR PORTC.PDR.BIT.B5
+/* Display enable pin */
+#define E_PIN PORTB.PODR.BIT.B1
+#define E_PIN_DDR PORTB.PDR.BIT.B1
+/* Data write/read definition */
+#define DATA_WR 1
+/* Control write/read definition */
+#define CTRL_WR 0
+/* Maximum characters per line of LCD display. */
+#define NUMB_CHARS_PER_LINE 8
+/* Number of lines on the LCD display */
+#define MAXIMUM_LINES 2
+/* Character position of LCD line 1 */
+#define LCD_LINE1 0
+/* Character position of LCD line 2 */
+#define LCD_LINE2 16
+/* Clear LCD display and home cursor */
+#define LCD_CLEAR 0x01
+/* Move cursor to line 1 */
+#define LCD_HOME_L1 0x80
+/* Move cursor to line 2 */
+#define LCD_HOME_L2 0xC0
+/* Cursor auto decrement after R/W */
+#define CURSOR_MODE_DEC 0x04
+/* Cursor auto increment after R/W */
+#define CURSOR_MODE_INC 0x06
+/* Setup, 4 bits,2 lines, 5X7 */
+#define FUNCTION_SET 0x28
+/* Display ON with Cursor */
+#define LCD_CURSOR_ON 0x0E
+/* Display ON with Cursor off */
+#define LCD_CURSOR_OFF 0x0C
+/* Display on with blinking cursor */
+#define LCD_CURSOR_BLINK 0x0D
+/* Move Cursor Left One Position */
+#define LCD_CURSOR_LEFT 0x10
+/* Move Cursor Right One Position */
+#define LCD_CURSOR_RIGHT 0x14
+/* Enable LCD display */
+#define LCD_DISPLAY_ON 0x04
+/* Enable both LCD lines */
+#define LCD_TWO_LINE 0x08
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+/* LCD initialisation function declaration */
+void lcd_initialize (void);
+
+/* Update display function declaration */
+void lcd_display(uint8_t position, uint8_t const * string);
+
+/* Clear LCD function delcaration */
+void lcd_clear (void);
+
+/* End of multiple inclusion prevention macro */
+#endif
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h
new file mode 100644
index 000000000..19e36ac6f
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp.h
+* H/W Platform : RSKRX111
+* Description : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef PLATFORM_BOARD_RSKRX111
+#define PLATFORM_BOARD_RSKRX111
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef PLATFORM_DEFINED
+#error "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+#include "r_bsp_config.h"
+#include "iorx111.h"
+#include ".\mcu\rx111\mcu_info.h"
+#include ".\board\rskrx111\rskrx111.h"
+#include ".\board\rskrx111\lcd.h"
+
+#endif /* PLATFORM_BOARD_RSKRX111 */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h
new file mode 100644
index 000000000..da6dc9d1e
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h
@@ -0,0 +1,250 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.c
+* Device(s) : RX111
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 51 11 5 A D FM
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)
+ | | | | | | |______not used = Blank
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________MCU_PART_GROUP = Group name
+ | | | |______________MCU_PART_SERIES = Series name
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FM = 0x0 = LFQFP/64/0.50
+ FK = 0x1 = LQFP/64/0.80
+ LF = 0x2 = TFLGA/64/0.50
+ FL = 0x3 = LFQFP/48/0.50
+ NE = 0x4 = VQFN/48/0.50
+ NC = 0x5 = HWQFN/36/0.50
+ LM = 0x6 = WFLGA/36/0.50
+ SB = 0x7 = SSOP/36/0.80
+*/
+#define MCU_PART_PACKAGE (0x0)
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 5 = 0x5 = 128KB/16KB/8KB
+ 4 = 0x4 = 96KB/16KB/8KB
+ 3 = 0x3 = 64KB/10KB/8KB
+ 1 = 0x1 = 32KB/10KB/8KB
+ J = 0x0 = 16KB/8KB/8KB
+*/
+#define MCU_PART_MEMORY_SIZE (0x5)
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 10 = 0x0 = RX110 Group
+ 11 = 0x1 = RX111 Group
+*/
+#define MCU_PART_GROUP (0x1)
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 51 = 0x0 = RX100 Series
+*/
+#define MCU_PART_SERIES (0x0)
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define MCU_PART_MEMORY_TYPE (0x0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize su=0x400
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize si=0x100
+#endif
+
+/* Heap size in bytes. */
+#define HEAP_BYTES (0x400)
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define RUN_IN_USER_MODE (0)
+
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = RTOS is used.
+*/
+#define RTOS_USED (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define CLOCK_SOURCE (4)
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the
+ settings would be:
+
+ XTAL_HZ = 16000000
+ PLL_DIV = 2
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz
+*/
+/* XTAL - Input clock frequency in Hz */
+#define XTAL_HZ (16000000)
+/* PLL Input Frequency Divider Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /4
+*/
+#define PLL_DIV (2)
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x6, x8
+*/
+#define PLL_MUL (6)
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define ICK_DIV (2)
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKB_DIV (2)
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKD_DIV (2)
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define FCK_DIV (2)
+
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a
+ function to be called when the event occurs. For example, if the user wanted the function
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would
+ do the following:
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+ If the user does not wish to be alerted of these events then they should comment out the macros.
+
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it
+ is executing. For this reason, it is recommended to keep these callback functions short as to not
+ decrease the real-time response of your system.
+*/
+/* Callback for Supervisor Instruction Violation Exception. */
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb
+
+/* Callback for Undefined Instruction Exception. */
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb
+
+/* Callback for Non-maskable Interrupt. */
+//#define NMI_ISR_CALLBACK nmi_cb
+
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source
+ is creating unwanted interrupts. */
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+
+/* Callback for Bus Error Interrupt. */
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb
+
+/* The user has the option of separately choosing little or big endian for the User Application Area */
+
+/* Endian mode for User Application.
+ 0 = Big Endian
+ Else = Little Endian (Default)
+*/
+#define USER_APP_ENDIAN (1)
+
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ OFS0 - Option Function Select Register 0
+ b31:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1) */
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select
+ 0 1 0 0: 3.10 V
+ 0 1 0 1: 3.00 V
+ 0 1 1 0: 2.90 V
+ 0 1 1 1: 2.79 V
+ 1 0 0 0: 2.68 V
+ 1 0 0 1: 2.58 V
+ 1 0 1 0: 2.48 V
+ 1 0 1 1: 2.06 V
+ 1 1 0 0: 1.96 V
+ 1 1 0 1: 1.86 V
+ b3:b2 Reserved (set to 1)
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define IO_LIB_ENABLE (1)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h
new file mode 100644
index 000000000..8ab534a7b
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : rskrx111.h
+* H/W Platform : RSKRX111
+* Description : Board specific definitions for the RSKRX111.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef RSKRX111_H
+#define RSKRX111_H
+
+/* Local defines */
+#define LED_ON (0)
+#define LED_OFF (1)
+#define SET_BIT_HIGH (1)
+#define SET_BIT_LOW (0)
+#define SET_BYTE_HIGH (0xFF)
+#define SET_BYTE_LOW (0x00)
+
+/* Switches */
+#define SW_ACTIVE 0
+#define SW1 PORT3.PIDR.BIT.B0
+#define SW2 PORT3.PIDR.BIT.B1
+#define SW3 PORTE.PIDR.BIT.B4
+#define SW1_PDR PORT3.PDR.BIT.B0
+#define SW2_PDR PORT3.PDR.BIT.B1
+#define SW3_PDR PORTE.PDR.BIT.B4
+#define SW1_PMR PORT3.PMR.BIT.B0
+#define SW2_PMR PORT3.PMR.BIT.B1
+#define SW3_PMR PORTE.PMR.BIT.B4
+
+/* LEDs */
+#define LED0 PORTB.PODR.BIT.B7
+#define LED1 PORTA.PODR.BIT.B0
+#define LED2 PORT5.PODR.BIT.B4
+#define LED3 PORT1.PODR.BIT.B7
+#define LED0_PDR PORTB.PDR.BIT.B7
+#define LED1_PDR PORTA.PDR.BIT.B0
+#define LED2_PDR PORT5.PDR.BIT.B4
+#define LED3_PDR PORT1.PDR.BIT.B7
+
+
+#endif /* RSKRX111_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/user/hardware_setup.c b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/user/hardware_setup.c
new file mode 100644
index 000000000..2be30adb5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/user/hardware_setup.c
@@ -0,0 +1,366 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : hwsetup.c
+* Device(s) : RX
+* H/W Platform : RSKRX210
+* Description : Defines the initialization routines used each time the MCU is restarted.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* I/O Register and board definitions */
+#include "platform.h"
+#include "r_switches_if.h"
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* MCU I/O port configuration function delcaration */
+static void output_ports_configure(void);
+
+/* Interrupt configuration function delcaration */
+static void interrupts_configure(void);
+
+/* MCU peripheral module configuration function declaration */
+static void peripheral_modules_enable(void);
+
+/* Configure MCU clocks. */
+static void clock_source_select (void);
+void operating_frequency_set(void);
+
+/***********************************************************************************************************************
+* Function name: hardware_setup
+* Description : Contains setup functions called at device restart
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void vHardwareSetup(void)
+{
+ operating_frequency_set();
+ output_ports_configure();
+ interrupts_configure();
+ peripheral_modules_enable();
+}
+
+/***********************************************************************************************************************
+* Function name: output_ports_configure
+* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void output_ports_configure(void)
+{
+ /* Enable LEDs. */
+ /* Start with LEDs off. */
+ LED0 = LED_OFF;
+ LED1 = LED_OFF;
+ LED2 = LED_OFF;
+ LED3 = LED_OFF;
+
+ /* Set LED pins as outputs. */
+ LED0_PDR = 1;
+ LED1_PDR = 1;
+ LED2_PDR = 1;
+ LED3_PDR = 1;
+
+ /* Enable switches. */
+ /* Set pins as inputs. */
+ SW1_PDR = 0;
+ SW2_PDR = 0;
+ SW3_PDR = 0;
+
+ /* Set port mode registers for switches. */
+ SW1_PMR = 0;
+ SW2_PMR = 0;
+ SW3_PMR = 0;
+
+ /* Unlock MPC registers to enable writing to them. */
+ MPC.PWPR.BIT.B0WI = 0 ; /* Unlock protection register */
+ MPC.PWPR.BIT.PFSWE = 1 ; /* Unlock MPC registers */
+
+ /* TXD1 is output. */
+ PORT1.PDR.BIT.B6 = 1;
+ PORT1.PMR.BIT.B6 = 1;
+ MPC.P16PFS.BYTE = 0x0A;
+ /* RXD1 is input. */
+ PORT1.PDR.BIT.B5 = 0;
+ PORT1.PMR.BIT.B5 = 1;
+ MPC.P15PFS.BYTE = 0x0A;
+
+ /* Configure the pin connected to the ADC Pot as an input */
+ PORT4.PDR.BIT.B4 = 0;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Turn off module stop for the A2D converter. */
+ SYSTEM.MSTPCRA.BIT.MSTPA17 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Initialise the first button to generate an interrupt. */
+ R_SWITCHES_Init();
+}
+
+/***********************************************************************************************************************
+* Function name: interrupts_configure
+* Description : Configures interrupts used
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void interrupts_configure(void)
+{
+ /* Add code here to setup additional interrupts */
+}
+
+/***********************************************************************************************************************
+* Function name: peripheral_modules_enable
+* Description : Enables and configures peripheral devices on the MCU
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void peripheral_modules_enable(void)
+{
+ /* Enable triggers to start an ADC conversion. */
+ S12AD.ADCSR.BIT.TRGE = 1;
+
+ /* Only channel 4 is going to be used. */
+ S12AD.ADANSA.BIT.ANSA4 = 1;
+}
+
+/***********************************************************************************************************************
+* Function name: operating_frequency_set
+* Description : Configures the clock settings for each of the device clocks
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void operating_frequency_set(void)
+{
+ /* Used for constructing value to write to SCKCR and CKOCR registers. */
+ uint32_t temp_clock = 0;
+
+ /*
+ Clock Description Frequency
+ ----------------------------------------
+ Input Clock Frequency............ 16 MHz
+ PLL frequency (x3)............... 48 MHz
+ Internal Clock Frequency......... 24 MHz
+ Peripheral Clock Frequency....... 24 MHz
+ Clock Out Frequency.............. 1 MHz */
+
+ volatile unsigned int i;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Select the clock based upon user's choice. */
+ clock_source_select();
+
+
+ /* Figure out setting for FCK bits. */
+#if FCK_DIV == 1
+ /* Do nothing since FCK bits should be 0. */
+#elif FCK_DIV == 2
+ temp_clock |= 0x10000000;
+#elif FCK_DIV == 4
+ temp_clock |= 0x20000000;
+#elif FCK_DIV == 8
+ temp_clock |= 0x30000000;
+#elif FCK_DIV == 16
+ temp_clock |= 0x40000000;
+#elif FCK_DIV == 32
+ temp_clock |= 0x50000000;
+#elif FCK_DIV == 64
+ temp_clock |= 0x60000000;
+#else
+ #error "Error! Invalid setting for FCK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for ICK bits. */
+#if ICK_DIV == 1
+ /* Do nothing since ICK bits should be 0. */
+#elif ICK_DIV == 2
+ temp_clock |= 0x01000000;
+#elif ICK_DIV == 4
+ temp_clock |= 0x02000000;
+#elif ICK_DIV == 8
+ temp_clock |= 0x03000000;
+#elif ICK_DIV == 16
+ temp_clock |= 0x04000000;
+#elif ICK_DIV == 32
+ temp_clock |= 0x05000000;
+#elif ICK_DIV == 64
+ temp_clock |= 0x06000000;
+#else
+ #error "Error! Invalid setting for ICK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKB bits. */
+#if PCKB_DIV == 1
+ /* Do nothing since PCKB bits should be 0. */
+#elif PCKB_DIV == 2
+ temp_clock |= 0x00000100;
+#elif PCKB_DIV == 4
+ temp_clock |= 0x00000200;
+#elif PCKB_DIV == 8
+ temp_clock |= 0x00000300;
+#elif PCKB_DIV == 16
+ temp_clock |= 0x00000400;
+#elif PCKB_DIV == 32
+ temp_clock |= 0x00000500;
+#elif PCKB_DIV == 64
+ temp_clock |= 0x00000600;
+#else
+ #error "Error! Invalid setting for PCKB_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKD bits. */
+#if PCKD_DIV == 1
+ /* Do nothing since PCKD bits should be 0. */
+#elif PCKD_DIV == 2
+ temp_clock |= 0x00000001;
+#elif PCKD_DIV == 4
+ temp_clock |= 0x00000002;
+#elif PCKD_DIV == 8
+ temp_clock |= 0x00000003;
+#elif PCKD_DIV == 16
+ temp_clock |= 0x00000004;
+#elif PCKD_DIV == 32
+ temp_clock |= 0x00000005;
+#elif PCKD_DIV == 64
+ temp_clock |= 0x00000006;
+#else
+ #error "Error! Invalid setting for PCKD_DIV in r_bsp_config.h"
+#endif
+
+ /* Set SCKCR register. */
+ SYSTEM.SCKCR.LONG = temp_clock;
+
+ /* Choose clock source. Default for r_bsp_config.h is PLL. */
+ SYSTEM.SCKCR3.WORD = ((uint16_t)CLOCK_SOURCE) << 8;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+}
+
+/***********************************************************************************************************************
+* Function name: clock_source_select
+* Description : Enables and disables clocks as chosen by the user. This function also implements the software delays
+* needed for the clocks to stabilize.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+static void clock_source_select (void)
+{
+ /* Declared volatile for software delay purposes. */
+ volatile unsigned int i;
+
+ /* NOTE: AS OF VERSION 0.50 OF THE RX111 HARDWARE MANUAL, ALL OF THE CLOCK
+ * STABILIZATION TIMES ARE TBD. FOR NOW, WHERE EVER A WAIT COUNT REGISTER
+ * IS AVAILABLE, THE DELAY IS SET TO THE MAX NUMBER OF CYCLES. WHERE EVER
+ * DELAY LOOPS ARE PRESENT, THE VALUES FROM THE 63N ARE RE-USED. KEEP IN
+ * MIND THAT THE 63N RUNS ON A FASTER CRYSTAL.
+ */
+
+#if (CLOCK_SOURCE == 1)
+ /* HOCO is chosen. Start it operating. */
+ SYSTEM.HOCOCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the HOCO has stabilized.*/
+ for(i = 0; i< 28; i++) // tHOCOWT2 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#else
+ /* HOCO is not chosen. Stop the HOCO. */
+ SYSTEM.HOCOCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 2)
+ /* Main clock oscillator is chosen. Start it operating. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock has stabilized. */
+ for(i = 0; i< 140; i++) // tMAINOSCWT is TBD
+ {
+ __asm volatile( "NOT" );
+ }
+#endif
+
+#if (CLOCK_SOURCE == 3)
+ /* Sub-clock oscillator is chosen. Start it operating. */
+ /* In section 9.8.4, there is a reference to a SOSCWTCR register, but there is no
+ * description for this register in the manual nor reference for it in iorx111.h. */
+
+ /* Set the sub-clock to operating. */
+ SYSTEM.SOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the sub-clock has stabilized. */
+ for(i = 0; i< 30233; i++) // tSUBOSCWT0 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#else
+ /* Set the sub-clock to stopped. */
+ SYSTEM.SOSCCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 4)
+ /* PLL is chosen. Start it operating. Must start main clock as well since PLL uses it. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+
+ /* Set PLL Input Divisor. */
+ SYSTEM.PLLCR.BIT.PLIDIV = PLL_DIV >> 1;
+
+ /* Set PLL Multiplier. */
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL * 2) - 1;
+
+ /* Set the PLL to operating. */
+ SYSTEM.PLLCR2.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock and PLL have stabilized. */
+ for(i = 0; i< 140; i++) // tPLLWT2 is TBD
+ {
+ __asm volatile( "NOP" );
+ }
+#endif
+
+ /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn
+ it off until another clock has been enabled and is ready to use. */
+#if (CLOCK_SOURCE == 0)
+ /* LOCO is chosen. This is the default out of reset. */
+ SYSTEM.LOCOCR.BYTE = 0x00;
+#else
+ /* LOCO is not chosen and another clock has already been setup. Turn off the LOCO. */
+ SYSTEM.LOCOCR.BYTE = 0x01;
+#endif
+
+ /* Make sure a valid clock was chosen. */
+#if (CLOCK_SOURCE > 4) || (CLOCK_SOURCE < 0)
+ #error "ERROR - Valid clock source must be chosen in r_bsp_config.h using CLOCK_SOURCE macro."
+#endif
+}
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/user/r_bsp.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/user/r_bsp.h
new file mode 100644
index 000000000..bd8881cd6
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/board/user/r_bsp.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp.h
+* Description : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 13.01.2012 1.00 First Release
+* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure.
+***********************************************************************************************************************/
+
+#ifndef PLATFORM_BOARD_USER
+#define PLATFORM_BOARD_USER
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef PLATFORM_DEFINED
+#error "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+/* This is a user defined board. Start off by:
+ 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).
+ 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.
+ 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.
+ 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.
+ 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.
+ You can also add your own include files here as well. */
+#include "r_bsp_config.h"
+#include ".\mcu\*MCU Group*\mcu_info.h"
+
+#endif /* PLATFORM_BOARD_USER */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/Copy of iodefine.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/Copy of iodefine.h
new file mode 100644
index 000000000..30d7bd4d8
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/Copy of iodefine.h
@@ -0,0 +1,5142 @@
+/********************************************************************************/
+/* */
+/* Device : RX/RX100/RX111 */
+/* File Name : iodefine.h */
+/* Abstract : Definition of I/O Register. */
+/* History : V0.5 (2012-09-25) [Hardware Manual Revision : 0.50] */
+/* Note : This is a typical example. */
+/* */
+/* Copyright(c) 2012 Renesas Electronics Corp. */
+/* And Renesas Solutions Corp. ,All Rights Reserved. */
+/* */
+/********************************************************************************/
+/* */
+/* DESCRIPTION : Definition of ICU Register */
+/* CPU TYPE : RX111 */
+/* */
+/* Usage : IR,DTCER,IER,IPR of ICU Register */
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */
+/* The bit access operation is "Bit_Name(interrupt source,name)". */
+/* A part of the name can be omitted. */
+/* for example : */
+/* IR(MTU0,TGIA0) = 0; expands to : */
+/* ICU.IR[114].BIT.IR = 0; */
+/* */
+/* DTCE(ICU,IRQ0) = 1; expands to : */
+/* ICU.DTCER[64].BIT.DTCE = 1; */
+/* */
+/* IEN(CMT0,CMI0) = 1; expands to : */
+/* ICU.IER[0x03].BIT.IEN4 = 1; */
+/* */
+/* IPR(MTU1,TGIA1) = 2; expands to : */
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */
+/* ICU.IPR[121].BIT.IPR = 2; */
+/* */
+/* IPR(SCI1,ERI1) = 3; expands to : */
+/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */
+/* ICU.IPR[218].BIT.IPR = 3; */
+/* */
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */
+/* The number of vector is "(interrupt source, name)". */
+/* for example : */
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */
+/* #pragma interrupt INT_IRQ0(vect=64) */
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */
+/* */
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */
+/* The bit access operation is "MSTP(name)". */
+/* The name that can be used is a macro name defined with "iodefine.h". */
+/* for example : */
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */
+/* */
+/* */
+/********************************************************************************/
+#ifndef __RX111IODEFINE_HEADER__
+#define __RX111IODEFINE_HEADER__
+
+
+struct st_bsc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char STSCLR:1;
+ } BIT;
+ } BERCLR;
+ char wk0[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IGAEN:1;
+ } BIT;
+ } BEREN;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MST:3;
+ unsigned char :3;
+ unsigned char IA:1;
+ } BIT;
+ } BERSR1;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADDR:13;
+ } BIT;
+ } BERSR2;
+ char wk3[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short BPFB:2;
+ unsigned short :2;
+ unsigned short BPGB:2;
+ unsigned short BPIB:2;
+ unsigned short BPRO:2;
+ unsigned short BPRA:2;
+ } BIT;
+ } BUSPRI;
+};
+
+struct st_cac {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char CFME:1;
+ } BIT;
+ } CACR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char EDGES:2;
+ unsigned char TCSS:2;
+ unsigned char FMCS:3;
+ unsigned char CACREFE:1;
+ } BIT;
+ } CACR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DFS:2;
+ unsigned char RCDS:2;
+ unsigned char RSCS:3;
+ unsigned char RPS:1;
+ } BIT;
+ } CACR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char OVFFCL:1;
+ unsigned char MENDFCL:1;
+ unsigned char FERRFCL:1;
+ unsigned char :1;
+ unsigned char OVFIE:1;
+ unsigned char MENDIE:1;
+ unsigned char FERRIE:1;
+ } BIT;
+ } CAICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char OVFF:1;
+ unsigned char MENDF:1;
+ unsigned char FERRF:1;
+ } BIT;
+ } CASTR;
+ char wk0[1];
+ unsigned short CAULVR;
+ unsigned short CALLVR;
+ unsigned short CACNTBR;
+};
+
+struct st_cmt {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :14;
+ unsigned short STR1:1;
+ unsigned short STR0:1;
+ } BIT;
+ } CMSTR0;
+};
+
+struct st_cmt0 {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :9;
+ unsigned short CMIE:1;
+ unsigned short :4;
+ unsigned short CKS:2;
+ } BIT;
+ } CMCR;
+ unsigned short CMCNT;
+ unsigned short CMCOR;
+};
+
+struct st_crc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DORCLR:1;
+ unsigned char :4;
+ unsigned char LMS:1;
+ unsigned char GPS:2;
+ } BIT;
+ } CRCCR;
+ unsigned char CRCDIR;
+ unsigned short CRCDOR;
+};
+
+struct st_da {
+ unsigned short DADR0;
+ unsigned short DADR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DAOE1:1;
+ unsigned char DAOE0:1;
+ } BIT;
+ } DACR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DPSEL:1;
+ } BIT;
+ } DADPR;
+};
+
+struct st_doc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char DOPCFCL:1;
+ unsigned char DOPCF:1;
+ unsigned char DOPCIE:1;
+ unsigned char :1;
+ unsigned char DCSEL:1;
+ unsigned char OMS:2;
+ } BIT;
+ } DOCR;
+ char wk0[1];
+ unsigned short DODIR;
+ unsigned short DODSR;
+};
+
+struct st_dtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char RRS:1;
+ } BIT;
+ } DTCCR;
+ char wk0[3];
+ void *DTCVBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SHORT:1;
+ } BIT;
+ } DTCADMOD;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DTCST:1;
+ } BIT;
+ } DTCST;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ACT:1;
+ unsigned short :7;
+ unsigned short VECN:8;
+ } BIT;
+ } DTCSTS;
+};
+
+struct st_elc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELCON:1;
+ } BIT;
+ } ELCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELS:8;
+ } BIT;
+ } ELSR[26];
+ char wk0[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTU3MD:2;
+ unsigned char MTU2MD:2;
+ unsigned char MTU1MD:2;
+ } BIT;
+ } ELOPA;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char MTU4MD:2;
+ } BIT;
+ } ELOPB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char CMT1MD:2;
+ } BIT;
+ } ELOPC;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PGR7:1;
+ unsigned char PGR6:1;
+ unsigned char PGR5:1;
+ unsigned char PGR4:1;
+ unsigned char PGR3:1;
+ unsigned char PGR2:1;
+ unsigned char PGR1:1;
+ unsigned char PGR0:1;
+ } BIT;
+ } PGR1;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PGCO:3;
+ unsigned char :1;
+ unsigned char PGCOVE:1;
+ unsigned char PGCI:2;
+ } BIT;
+ } PGC1;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PDBF7:1;
+ unsigned char PDBF6:1;
+ unsigned char PDBF5:1;
+ unsigned char PDBF4:1;
+ unsigned char PDBF3:1;
+ unsigned char PDBF2:1;
+ unsigned char PDBF1:1;
+ unsigned char PDBF0:1;
+ } BIT;
+ } PDBF1;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSM:2;
+ unsigned char PSP:2;
+ unsigned char PSB:3;
+ } BIT;
+ } PEL0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSM:2;
+ unsigned char PSP:2;
+ unsigned char PSB:3;
+ } BIT;
+ } PEL1;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char WI:1;
+ unsigned char WE:1;
+ unsigned char :5;
+ unsigned char SEG:1;
+ } BIT;
+ } ELSEGR;
+};
+
+struct st_flash {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DFLEN:1;
+ } BIT;
+ } DFLCTL;
+};
+
+struct st_icu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IR:1;
+ } BIT;
+ } IR[250];
+ char wk0[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DTCE:1;
+ } BIT;
+ } DTCER[249];
+ char wk1[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IEN7:1;
+ unsigned char IEN6:1;
+ unsigned char IEN5:1;
+ unsigned char IEN4:1;
+ unsigned char IEN3:1;
+ unsigned char IEN2:1;
+ unsigned char IEN1:1;
+ unsigned char IEN0:1;
+ } BIT;
+ } IER[32];
+ char wk2[192];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SWINT:1;
+ } BIT;
+ } SWINTR;
+ char wk3[15];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FIEN:1;
+ unsigned short :7;
+ unsigned short FVCT:8;
+ } BIT;
+ } FIR;
+ char wk4[14];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char IPR:4;
+ } BIT;
+ } IPR[250];
+ char wk5[262];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char IRQMD:2;
+ } BIT;
+ } IRQCR[8];
+ char wk6[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FLTEN7:1;
+ unsigned char FLTEN6:1;
+ unsigned char FLTEN5:1;
+ unsigned char FLTEN4:1;
+ unsigned char FLTEN3:1;
+ unsigned char FLTEN2:1;
+ unsigned char FLTEN1:1;
+ unsigned char FLTEN0:1;
+ } BIT;
+ } IRQFLTE0;
+ char wk7[3];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FCLKSEL7:2;
+ unsigned short FCLKSEL6:2;
+ unsigned short FCLKSEL5:2;
+ unsigned short FCLKSEL4:2;
+ unsigned short FCLKSEL3:2;
+ unsigned short FCLKSEL2:2;
+ unsigned short FCLKSEL1:2;
+ unsigned short FCLKSEL0:2;
+ } BIT;
+ } IRQFLTC0;
+ char wk8[106];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2ST:1;
+ unsigned char LVD1ST:1;
+ unsigned char IWDTST:1;
+ unsigned char :1;
+ unsigned char OSTST:1;
+ unsigned char NMIST:1;
+ } BIT;
+ } NMISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2EN:1;
+ unsigned char LVD1EN:1;
+ unsigned char IWDTEN:1;
+ unsigned char :1;
+ unsigned char OSTEN:1;
+ unsigned char NMIEN:1;
+ } BIT;
+ } NMIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2CLR:1;
+ unsigned char LVD1CLR:1;
+ unsigned char IWDTCLR:1;
+ unsigned char :1;
+ unsigned char OSTCLR:1;
+ unsigned char NMICLR:1;
+ } BIT;
+ } NMICLR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char NMIMD:1;
+ } BIT;
+ } NMICR;
+ char wk9[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char NFLTEN:1;
+ } BIT;
+ } NMIFLTE;
+ char wk10[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char NFCLKSEL:2;
+ } BIT;
+ } NMIFLTC;
+};
+
+struct st_iwdt {
+ unsigned char IWDTRR;
+ char wk0[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :2;
+ unsigned short RPSS:2;
+ unsigned short :2;
+ unsigned short RPES:2;
+ unsigned short CKS:4;
+ unsigned short :2;
+ unsigned short TOPS:2;
+ } BIT;
+ } IWDTCR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short REFEF:1;
+ unsigned short UNDFF:1;
+ unsigned short CNTVAL:14;
+ } BIT;
+ } IWDTSR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTIRQS:1;
+ } BIT;
+ } IWDTRCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SLCSTP:1;
+ } BIT;
+ } IWDTCSTPR;
+};
+
+struct st_mpc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0WI:1;
+ unsigned char PFSWE:1;
+ } BIT;
+ } PWPR;
+ char wk0[35];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P03PFS;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P05PFS;
+ char wk2[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P14PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P15PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P16PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P17PFS;
+ char wk3[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P26PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P27PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P30PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P31PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P32PFS;
+ char wk4[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ } BIT;
+ } P35PFS;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P40PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P41PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P42PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P43PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P44PFS;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P46PFS;
+ char wk7[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P54PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P55PFS;
+ char wk8[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA1PFS;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA4PFS;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA6PFS;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB1PFS;
+ char wk12[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB3PFS;
+ char wk13[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB7PFS;
+ char wk14[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC7PFS;
+ char wk15[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE1PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE7PFS;
+ char wk16[30];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ7PFS;
+};
+
+struct st_mtu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char OE4D:1;
+ unsigned char OE4C:1;
+ unsigned char OE3D:1;
+ unsigned char OE4B:1;
+ unsigned char OE4A:1;
+ unsigned char OE3B:1;
+ } BIT;
+ } TOER;
+ char wk0[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char BDC:1;
+ unsigned char N:1;
+ unsigned char P:1;
+ unsigned char FB:1;
+ unsigned char WF:1;
+ unsigned char VF:1;
+ unsigned char UF:1;
+ } BIT;
+ } TGCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSYE:1;
+ unsigned char :2;
+ unsigned char TOCL:1;
+ unsigned char TOCS:1;
+ unsigned char OLSN:1;
+ unsigned char OLSP:1;
+ } BIT;
+ } TOCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BF:2;
+ unsigned char OLS3N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS1P:1;
+ } BIT;
+ } TOCR2;
+ char wk1[4];
+ unsigned short TCDR;
+ unsigned short TDDR;
+ char wk2[8];
+ unsigned short TCNTS;
+ unsigned short TCBR;
+ char wk3[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char T3AEN:1;
+ unsigned char T3ACOR:3;
+ unsigned char T4VEN:1;
+ unsigned char T4VCOR:3;
+ } BIT;
+ } TITCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char T3ACNT:3;
+ unsigned char :1;
+ unsigned char T4VCNT:3;
+ } BIT;
+ } TITCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char BTE:2;
+ } BIT;
+ } TBTER;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char TDER:1;
+ } BIT;
+ } TDER;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char OLS3N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS1P:1;
+ } BIT;
+ } TOLBR;
+ char wk6[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCE:1;
+ unsigned char :6;
+ unsigned char WRE:1;
+ } BIT;
+ } TWCR;
+ char wk7[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CST4:1;
+ unsigned char CST3:1;
+ unsigned char :3;
+ unsigned char CST2:1;
+ unsigned char CST1:1;
+ unsigned char CST0:1;
+ } BIT;
+ } TSTR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SYNC4:1;
+ unsigned char SYNC3:1;
+ unsigned char :3;
+ unsigned char SYNC2:1;
+ unsigned char SYNC1:1;
+ unsigned char SYNC0:1;
+ } BIT;
+ } TSYR;
+ char wk8[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char RWE:1;
+ } BIT;
+ } TRWER;
+};
+
+struct st_mtu0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk0[111];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char BFE:1;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk1[16];
+ unsigned short TGRE;
+ unsigned short TGRF;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TGIEF:1;
+ unsigned char TGIEE:1;
+ } BIT;
+ } TIER2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+};
+
+struct st_mtu1 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk1[238];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char CCLR:2;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIOR;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :1;
+ unsigned char TCIEU:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk3[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char I2BE:1;
+ unsigned char I2AE:1;
+ unsigned char I1BE:1;
+ unsigned char I1AE:1;
+ } BIT;
+ } TICCR;
+};
+
+struct st_mtu2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk0[365];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char CCLR:2;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIOR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :1;
+ unsigned char TCIEU:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+};
+
+struct st_mtu3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ char wk3[7];
+ unsigned short TCNT;
+ char wk4[6];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk5[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk6[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+ char wk8[90];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu4 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char TTGE2:1;
+ unsigned char :1;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ char wk4[8];
+ unsigned short TCNT;
+ char wk5[8];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk6[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk8[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+ char wk9[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BF:2;
+ unsigned short :6;
+ unsigned short UT4AE:1;
+ unsigned short DT4AE:1;
+ unsigned short UT4BE:1;
+ unsigned short DT4BE:1;
+ unsigned short ITA3AE:1;
+ unsigned short ITA4VE:1;
+ unsigned short ITB3AE:1;
+ unsigned short ITB4VE:1;
+ } BIT;
+ } TADCR;
+ char wk10[2];
+ unsigned short TADCORA;
+ unsigned short TADCORB;
+ unsigned short TADCOBRA;
+ unsigned short TADCOBRB;
+ char wk11[72];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu5 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char :1;
+ unsigned char NFWEN:1;
+ unsigned char NFVEN:1;
+ unsigned char NFUEN:1;
+ } BIT;
+ } NFCR;
+ char wk1[490];
+ unsigned short TCNTU;
+ unsigned short TGRU;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRU;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORU;
+ char wk3[9];
+ unsigned short TCNTV;
+ unsigned short TGRV;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRV;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORV;
+ char wk5[9];
+ unsigned short TCNTW;
+ unsigned short TGRW;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRW;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORW;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TGIE5U:1;
+ unsigned char TGIE5V:1;
+ unsigned char TGIE5W:1;
+ } BIT;
+ } TIER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char CSTU5:1;
+ unsigned char CSTV5:1;
+ unsigned char CSTW5:1;
+ } BIT;
+ } TSTR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char CMPCLR5U:1;
+ unsigned char CMPCLR5V:1;
+ unsigned char CMPCLR5W:1;
+ } BIT;
+ } TCNTCMPCLR;
+};
+
+struct st_poe {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char POE3F:1;
+ unsigned char POE2F:1;
+ unsigned char POE1F:1;
+ unsigned char POE0F:1;
+ unsigned char :3;
+ unsigned char PIE1:1;
+ unsigned char POE3M:2;
+ unsigned char POE2M:2;
+ unsigned char POE1M:2;
+ unsigned char POE0M:2;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char OSF1:1;
+ unsigned char :5;
+ unsigned char OCE1:1;
+ unsigned char OIE1:1;
+ } BIT;
+ } OCSR1;
+ char wk0[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char POE8F:1;
+ unsigned char :2;
+ unsigned char POE8E:1;
+ unsigned char PIE2:1;
+ unsigned char :6;
+ unsigned char POE8M:2;
+ } BIT;
+ } ICSR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char CH0HIZ:1;
+ unsigned char CH34HIZ:1;
+ } BIT;
+ } SPOER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PE3ZE:1;
+ unsigned char PE2ZE:1;
+ unsigned char PE1ZE:1;
+ unsigned char PE0ZE:1;
+ } BIT;
+ } POECR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char P1CZEA:1;
+ unsigned char P2CZEA:1;
+ unsigned char P3CZEA:1;
+ } BIT;
+ } POECR2;
+ char wk1[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char OSTSTF:1;
+ unsigned char :2;
+ unsigned char OSTSTE:1;
+ } BIT;
+ } ICSR3;
+};
+
+struct st_port {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char PSEL5:1;
+ unsigned char :1;
+ unsigned char PSEL3:1;
+ unsigned char :1;
+ unsigned char PSEL1:1;
+ unsigned char PSEL0:1;
+ } BIT;
+ } PSRB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL7:1;
+ unsigned char PSEL6:1;
+ } BIT;
+ } PSRA;
+};
+
+struct st_port0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PMR;
+ char wk3[33];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[61];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ } BIT;
+ } ODR1;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port4 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+};
+
+struct st_port5 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porta {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :3;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :3;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[52];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[42];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :3;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ } BIT;
+ } ODR1;
+ char wk4[51];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PMR;
+ char wk3[43];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[50];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porte {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[45];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[48];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_riic {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ICE:1;
+ unsigned char IICRST:1;
+ unsigned char CLO:1;
+ unsigned char SOWP:1;
+ unsigned char SCLO:1;
+ unsigned char SDAO:1;
+ unsigned char SCLI:1;
+ unsigned char SDAI:1;
+ } BIT;
+ } ICCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BBSY:1;
+ unsigned char MST:1;
+ unsigned char TRS:1;
+ unsigned char :1;
+ unsigned char SP:1;
+ unsigned char RS:1;
+ unsigned char ST:1;
+ } BIT;
+ } ICCR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTWP:1;
+ unsigned char CKS:3;
+ unsigned char BCWP:1;
+ unsigned char BC:3;
+ } BIT;
+ } ICMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DLCS:1;
+ unsigned char SDDL:3;
+ unsigned char TMWE:1;
+ unsigned char TMOH:1;
+ unsigned char TMOL:1;
+ unsigned char TMOS:1;
+ } BIT;
+ } ICMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SMBS:1;
+ unsigned char WAIT:1;
+ unsigned char RDRFS:1;
+ unsigned char ACKWP:1;
+ unsigned char ACKBT:1;
+ unsigned char ACKBR:1;
+ unsigned char NF:2;
+ } BIT;
+ } ICMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SCLE:1;
+ unsigned char NFE:1;
+ unsigned char NACKE:1;
+ unsigned char SALE:1;
+ unsigned char NALE:1;
+ unsigned char MALE:1;
+ unsigned char TMOE:1;
+ } BIT;
+ } ICFER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HOAE:1;
+ unsigned char :1;
+ unsigned char DIDE:1;
+ unsigned char :1;
+ unsigned char GCAE:1;
+ unsigned char SAR2E:1;
+ unsigned char SAR1E:1;
+ unsigned char SAR0E:1;
+ } BIT;
+ } ICSER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char TEIE:1;
+ unsigned char RIE:1;
+ unsigned char NAKIE:1;
+ unsigned char SPIE:1;
+ unsigned char STIE:1;
+ unsigned char ALIE:1;
+ unsigned char TMOIE:1;
+ } BIT;
+ } ICIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HOA:1;
+ unsigned char :1;
+ unsigned char DID:1;
+ unsigned char :1;
+ unsigned char GCA:1;
+ unsigned char AAS2:1;
+ unsigned char AAS1:1;
+ unsigned char AAS0:1;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TDRE:1;
+ unsigned char TEND:1;
+ unsigned char RDRF:1;
+ unsigned char NACKF:1;
+ unsigned char STOP:1;
+ unsigned char START:1;
+ unsigned char AL:1;
+ unsigned char TMOF:1;
+ } BIT;
+ } ICSR2;
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTL;
+ };
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTH;
+ };
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char BRL:5;
+ } BIT;
+ } ICBRL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char BRH:5;
+ } BIT;
+ } ICBRH;
+ unsigned char ICDRT;
+ unsigned char ICDRR;
+};
+
+struct st_rspi {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPRIE:1;
+ unsigned char SPE:1;
+ unsigned char SPTIE:1;
+ unsigned char SPEIE:1;
+ unsigned char MSTR:1;
+ unsigned char MODFEN:1;
+ unsigned char TXMD:1;
+ unsigned char SPMS:1;
+ } BIT;
+ } SPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char SSL3P:1;
+ unsigned char SSL2P:1;
+ unsigned char SSL1P:1;
+ unsigned char SSL0P:1;
+ } BIT;
+ } SSLP;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char MOIFE:1;
+ unsigned char MOIFV:1;
+ unsigned char :2;
+ unsigned char SPLP2:1;
+ unsigned char SPLP:1;
+ } BIT;
+ } SPPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PERF:1;
+ unsigned char MODF:1;
+ unsigned char IDLNF:1;
+ unsigned char OVRF:1;
+ } BIT;
+ } SPSR;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned short H;
+ } WORD;
+ } SPDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SPSLN:3;
+ } BIT;
+ } SPSCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SPECM:3;
+ unsigned char :1;
+ unsigned char SPCP:3;
+ } BIT;
+ } SPSSR;
+ unsigned char SPBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char SPLW:1;
+ unsigned char SPRDTD:1;
+ unsigned char :2;
+ unsigned char SPFC:2;
+ } BIT;
+ } SPDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SCKDL:3;
+ } BIT;
+ } SPCKD;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SLNDL:3;
+ } BIT;
+ } SSLND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SPNDL:3;
+ } BIT;
+ } SPND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PTE:1;
+ unsigned char SPIIE:1;
+ unsigned char SPOE:1;
+ unsigned char SPPE:1;
+ } BIT;
+ } SPCR2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD5;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD6;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD7;
+};
+
+struct st_rtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char F1HZ:1;
+ unsigned char F2HZ:1;
+ unsigned char F4HZ:1;
+ unsigned char F8HZ:1;
+ unsigned char F16HZ:1;
+ unsigned char F32HZ:1;
+ unsigned char F64HZ:1;
+ } BIT;
+ } R64CNT;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SEC10:3;
+ unsigned char SEC1:4;
+ } BIT;
+ } RSECCNT;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MIN10:3;
+ unsigned char MIN1:4;
+ } BIT;
+ } RMINCNT;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PM:1;
+ unsigned char HR10:2;
+ unsigned char HR1:4;
+ } BIT;
+ } RHRCNT;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char DAYW:3;
+ } BIT;
+ } RWKCNT;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char DATE10:2;
+ unsigned char DATE1:4;
+ } BIT;
+ } RDAYCNT;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char MON10:1;
+ unsigned char MON1:4;
+ } BIT;
+ } RMONCNT;
+ char wk6[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short YR10:4;
+ unsigned short YR1:4;
+ } BIT;
+ } RYRCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char SEC10:3;
+ unsigned char SEC1:4;
+ } BIT;
+ } RSECAR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char MIN10:3;
+ unsigned char MIN1:4;
+ } BIT;
+ } RMINAR;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char PM:1;
+ unsigned char HR10:2;
+ unsigned char HR1:4;
+ } BIT;
+ } RHRAR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :4;
+ unsigned char DAYW:3;
+ } BIT;
+ } RWKAR;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :1;
+ unsigned char DATE10:2;
+ unsigned char DATE1:4;
+ } BIT;
+ } RDAYAR;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :2;
+ unsigned char MON10:1;
+ unsigned char MON1:4;
+ } BIT;
+ } RMONAR;
+ char wk12[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short YR10:4;
+ unsigned short YR1:4;
+ } BIT;
+ } RYRAR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ } BIT;
+ } RYRAREN;
+ char wk13[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PES:4;
+ unsigned char RTCOS:1;
+ unsigned char PIE:1;
+ unsigned char CIE:1;
+ unsigned char AIE:1;
+ } BIT;
+ } RCR1;
+ char wk14[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CNTMD:1;
+ unsigned char HR24:1;
+ unsigned char AADJP:1;
+ unsigned char AADJE:1;
+ unsigned char RTCOE:1;
+ unsigned char ADJ30:1;
+ unsigned char RESET:1;
+ unsigned char START:1;
+ } BIT;
+ } RCR2;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char RTCDV:2;
+ unsigned char RTCEN:1;
+ } BIT;
+ } RCR3;
+ char wk16[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PMADJ:2;
+ unsigned char ADJ:6;
+ } BIT;
+ } RADJ;
+};
+
+struct st_rtcb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT0;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT1;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT3;
+ char wk3[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT0AR;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT1AR;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT2AR;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT3AR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT0AER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT1AER;
+ char wk9[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short ENB:8;
+ } BIT;
+ } BCNT2AER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT3AER;
+};
+
+struct st_s12ad {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADST:1;
+ unsigned short ADCS:2;
+ unsigned short ADIE:1;
+ unsigned short :1;
+ unsigned short ADHSC:1;
+ unsigned short TRGE:1;
+ unsigned short EXTRG:1;
+ unsigned short DBLE:1;
+ unsigned short GBADIE:1;
+ unsigned short :1;
+ unsigned short DBLANS:5;
+ } BIT;
+ } ADCSR;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSA15:1;
+ unsigned short ANSA14:1;
+ unsigned short ANSA13:1;
+ unsigned short ANSA12:1;
+ unsigned short ANSA11:1;
+ unsigned short ANSA10:1;
+ unsigned short ANSA9:1;
+ unsigned short ANSA8:1;
+ unsigned short :1;
+ unsigned short ANSA6:1;
+ unsigned short :1;
+ unsigned short ANSA4:1;
+ unsigned short ANSA3:1;
+ unsigned short ANSA2:1;
+ unsigned short ANSA1:1;
+ unsigned short ANSA0:1;
+ } BIT;
+ } ADANSA;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADS15:1;
+ unsigned short ADS14:1;
+ unsigned short ADS13:1;
+ unsigned short ADS12:1;
+ unsigned short ADS11:1;
+ unsigned short ADS10:1;
+ unsigned short ADS9:1;
+ unsigned short ADS8:1;
+ unsigned short :1;
+ unsigned short ADS6:1;
+ unsigned short :1;
+ unsigned short ADS4:1;
+ unsigned short ADS3:1;
+ unsigned short ADS2:1;
+ unsigned short ADS1:1;
+ unsigned short ADS0:1;
+ } BIT;
+ } ADADS;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char ADC:2;
+ } BIT;
+ } ADADC;
+ char wk3[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADRFMT:1;
+ unsigned short :9;
+ unsigned short ACE:1;
+ } BIT;
+ } ADCER;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short TRSA:4;
+ unsigned short :4;
+ unsigned short TRSB:4;
+ } BIT;
+ } ADSTRGR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short OCS:1;
+ unsigned short TSS:1;
+ unsigned short :6;
+ unsigned short OCSAD:1;
+ } BIT;
+ } ADEXICR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSB15:1;
+ unsigned short ANSB14:1;
+ unsigned short ANSB13:1;
+ unsigned short ANSB12:1;
+ unsigned short ANSB11:1;
+ unsigned short ANSB10:1;
+ unsigned short ANSB9:1;
+ unsigned short ANSB8:1;
+ unsigned short :1;
+ unsigned short ANSB6:1;
+ unsigned short :1;
+ unsigned short ANSB4:1;
+ unsigned short ANSB3:1;
+ unsigned short ANSB2:1;
+ unsigned short ANSB1:1;
+ unsigned short ANSB0:1;
+ } BIT;
+ } ADANSB;
+ char wk4[2];
+ unsigned short ADDBLDR;
+ unsigned short ADTSDR;
+ unsigned short ADOCDR;
+ char wk5[2];
+ unsigned short ADDR0;
+ unsigned short ADDR1;
+ unsigned short ADDR2;
+ unsigned short ADDR3;
+ unsigned short ADDR4;
+ char wk6[2];
+ unsigned short ADDR6;
+ char wk7[2];
+ unsigned short ADDR8;
+ unsigned short ADDR9;
+ unsigned short ADDR10;
+ unsigned short ADDR11;
+ unsigned short ADDR12;
+ unsigned short ADDR13;
+ unsigned short ADDR14;
+ unsigned short ADDR15;
+ char wk8[32];
+ unsigned char ADSSTR0;
+ unsigned char ADSSTRL;
+ char wk9[14];
+ unsigned char ADSSTRT;
+ unsigned char ADSSTRO;
+ char wk10[1];
+ unsigned char ADSSTR1;
+ unsigned char ADSSTR2;
+ unsigned char ADSSTR3;
+ unsigned char ADSSTR4;
+ char wk11[1];
+ unsigned char ADSSTR6;
+};
+
+struct st_sci1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CM:1;
+ unsigned char CHR:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char STOP:1;
+ unsigned char MP:1;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char FER:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RXDESEL:1;
+ unsigned char :1;
+ unsigned char NFEN:1;
+ unsigned char ABCS:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char NFCS:3;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICDL:5;
+ unsigned char :2;
+ unsigned char IICM:1;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char IICACKT:1;
+ unsigned char :3;
+ unsigned char IICCSC:1;
+ unsigned char IICINTM:1;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSCLS:2;
+ unsigned char IICSDAS:2;
+ unsigned char IICSTIF:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTAREQ:1;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IICACKR:1;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKPH:1;
+ unsigned char CKPOL:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char MSS:1;
+ unsigned char CTSE:1;
+ unsigned char SSE:1;
+ } BIT;
+ } SPMR;
+};
+
+struct st_sci12 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CM:1;
+ unsigned char CHR:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char STOP:1;
+ unsigned char MP:1;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char FER:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RXDESEL:1;
+ unsigned char :1;
+ unsigned char NFEN:1;
+ unsigned char ABCS:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char NFCS:3;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICDL:5;
+ unsigned char :2;
+ unsigned char IICM:1;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char IICACKT:1;
+ unsigned char :3;
+ unsigned char IICCSC:1;
+ unsigned char IICINTM:1;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSCLS:2;
+ unsigned char IICSDAS:2;
+ unsigned char IICSTIF:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTAREQ:1;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IICACKR:1;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKPH:1;
+ unsigned char CKPOL:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char MSS:1;
+ unsigned char CTSE:1;
+ unsigned char SSE:1;
+ } BIT;
+ } SPMR;
+ char wk0[18];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ESME:1;
+ } BIT;
+ } ESMER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char BRME:1;
+ unsigned char RXDSF:1;
+ unsigned char SFSF:1;
+ } BIT;
+ } CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PIBS:3;
+ unsigned char PIBE:1;
+ unsigned char CF1DS:2;
+ unsigned char CF0RE:1;
+ unsigned char BFE:1;
+ } BIT;
+ } CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RTS:2;
+ unsigned char BCCS:2;
+ unsigned char :1;
+ unsigned char DFCS:3;
+ } BIT;
+ } CR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SDST:1;
+ } BIT;
+ } CR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char SHARPS:1;
+ unsigned char :2;
+ unsigned char RXDXPS:1;
+ unsigned char TXDXPS:1;
+ } BIT;
+ } PCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDIE:1;
+ unsigned char BCDIE:1;
+ unsigned char PIBDIE:1;
+ unsigned char CF1MIE:1;
+ unsigned char CF0MIE:1;
+ unsigned char BFDIE:1;
+ } BIT;
+ } ICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDF:1;
+ unsigned char BCDF:1;
+ unsigned char PIBDF:1;
+ unsigned char CF1MF:1;
+ unsigned char CF0MF:1;
+ unsigned char BFDF:1;
+ } BIT;
+ } STR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDCL:1;
+ unsigned char BCDCL:1;
+ unsigned char PIBDCL:1;
+ unsigned char CF1MCL:1;
+ unsigned char CF0MCL:1;
+ unsigned char BFDCL:1;
+ } BIT;
+ } STCR;
+ unsigned char CF0DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF0CE7:1;
+ unsigned char CF0CE6:1;
+ unsigned char CF0CE5:1;
+ unsigned char CF0CE4:1;
+ unsigned char CF0CE3:1;
+ unsigned char CF0CE2:1;
+ unsigned char CF0CE1:1;
+ unsigned char CF0CE0:1;
+ } BIT;
+ } CF0CR;
+ unsigned char CF0RR;
+ unsigned char PCF1DR;
+ unsigned char SCF1DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF1CE7:1;
+ unsigned char CF1CE6:1;
+ unsigned char CF1CE5:1;
+ unsigned char CF1CE4:1;
+ unsigned char CF1CE3:1;
+ unsigned char CF1CE2:1;
+ unsigned char CF1CE1:1;
+ unsigned char CF1CE0:1;
+ } BIT;
+ } CF1CR;
+ unsigned char CF1RR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char TCST:1;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char TCSS:3;
+ unsigned char TWRC:1;
+ unsigned char :1;
+ unsigned char TOMS:2;
+ } BIT;
+ } TMR;
+ unsigned char TPRE;
+ unsigned char TCNT;
+};
+
+struct st_smci {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char GM:1;
+ unsigned char BLK:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char BCP:2;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char ERS:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+};
+
+struct st_system {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short MD:1;
+ } BIT;
+ } MDMONR;
+ char wk0[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short RAME:1;
+ } BIT;
+ } SYSCR1;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SSBY:1;
+ } BIT;
+ } SBYCR;
+ char wk2[2];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :3;
+ unsigned long MSTPA28:1;
+ unsigned long :8;
+ unsigned long MSTPA19:1;
+ unsigned long :1;
+ unsigned long MSTPA17:1;
+ unsigned long :1;
+ unsigned long MSTPA15:1;
+ unsigned long :5;
+ unsigned long MSTPA9:1;
+ } BIT;
+ } MSTPCRA;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :1;
+ unsigned long MSTPB30:1;
+ unsigned long :3;
+ unsigned long MSTPB26:1;
+ unsigned long :2;
+ unsigned long MSTPB23:1;
+ unsigned long :1;
+ unsigned long MSTPB21:1;
+ unsigned long :1;
+ unsigned long MSTPB19:1;
+ unsigned long :1;
+ unsigned long MSTPB17:1;
+ unsigned long :7;
+ unsigned long MSTPB9:1;
+ unsigned long :2;
+ unsigned long MSTPB6:1;
+ unsigned long :1;
+ unsigned long MSTPB4:1;
+ } BIT;
+ } MSTPCRB;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long DSLPE:1;
+ unsigned long :11;
+ unsigned long MSTPC19:1;
+ unsigned long :18;
+ unsigned long MSTPC0:1;
+ } BIT;
+ } MSTPCRC;
+ char wk3[4];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long FCK:4;
+ unsigned long ICK:4;
+ unsigned long :12;
+ unsigned long PCKB:4;
+ unsigned long :4;
+ unsigned long PCKD:4;
+ } BIT;
+ } SCKCR;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :5;
+ unsigned short CKSEL:3;
+ } BIT;
+ } SCKCR3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :2;
+ unsigned short STC:6;
+ unsigned short :6;
+ unsigned short PLIDIV:2;
+ } BIT;
+ } PLLCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char PLLEN:1;
+ } BIT;
+ } PLLCR2;
+ char wk5[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char MOSTP:1;
+ } BIT;
+ } MOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SOSTP:1;
+ } BIT;
+ } SOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char LCSTP:1;
+ } BIT;
+ } LOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ILCSTP:1;
+ } BIT;
+ } ILOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char HCSTP:1;
+ } BIT;
+ } HOCOCR;
+ char wk6[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char HCOVF:1;
+ unsigned char PLOVF:1;
+ unsigned char :1;
+ unsigned char MOOVF:1;
+ } BIT;
+ } OSCOVFSR;
+ char wk7[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CKOSTP:1;
+ unsigned short CKODIV:3;
+ unsigned short :1;
+ unsigned short CKOSEL:3;
+ } BIT;
+ } CKOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OSTDE:1;
+ unsigned char :6;
+ unsigned char OSTDIE:1;
+ } BIT;
+ } OSTDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char OSTDF:1;
+ } BIT;
+ } OSTDSR;
+ char wk8[94];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char OPCMTSF:1;
+ unsigned char :1;
+ unsigned char OPCM:3;
+ } BIT;
+ } OPCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTCKEN:1;
+ unsigned char :4;
+ unsigned char RSTCKSEL:3;
+ } BIT;
+ } RSTCKCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char MSTS:5;
+ } BIT;
+ } MOSCWTCR;
+ char wk9[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char SOPCMTSF:1;
+ unsigned char :3;
+ unsigned char SOPCM:1;
+ } BIT;
+ } SOPCCR;
+ char wk10[21];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SWRF:1;
+ unsigned char :1;
+ unsigned char IWDTRF:1;
+ } BIT;
+ } RSTSR2;
+ char wk11[1];
+ unsigned short SWRR;
+ char wk12[28];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char LVD1IRQSEL:1;
+ unsigned char LVD1IDTSEL:2;
+ } BIT;
+ } LVD1CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char LVD1MON:1;
+ unsigned char LVD1DET:1;
+ } BIT;
+ } LVD1SR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char LVD2IRQSEL:1;
+ unsigned char LVD2IDTSEL:2;
+ } BIT;
+ } LVD2CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char LVD2MON:1;
+ unsigned char LVD2DET:1;
+ } BIT;
+ } LVD2SR;
+ char wk13[794];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PRKEY:8;
+ unsigned short :4;
+ unsigned short PRC3:1;
+ unsigned short :1;
+ unsigned short PRC1:1;
+ unsigned short PRC0:1;
+ } BIT;
+ } PRCR;
+ char wk14[48784];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char LVD2RF:1;
+ unsigned char LVD1RF:1;
+ unsigned char :1;
+ unsigned char PORF:1;
+ } BIT;
+ } RSTSR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char CWSF:1;
+ } BIT;
+ } RSTSR1;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MOSEL:1;
+ unsigned char MODRV21:1;
+ } BIT;
+ } MOFCR;
+ char wk16[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char LVD2E:1;
+ unsigned char LVD1E:1;
+ unsigned char :1;
+ unsigned char EXVCCINP2:1;
+ } BIT;
+ } LVCMPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2LVL:2;
+ unsigned char LVD1LVL:4;
+ } BIT;
+ } LVDLVLR;
+ char wk17[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1RN:1;
+ unsigned char LVD1RI:1;
+ unsigned char :3;
+ unsigned char LVD1CMPE:1;
+ unsigned char :1;
+ unsigned char LVD1RIE:1;
+ } BIT;
+ } LVD1CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD2RN:1;
+ unsigned char LVD2RI:1;
+ unsigned char :3;
+ unsigned char LVD2CMPE:1;
+ unsigned char :1;
+ unsigned char LVD2RIE:1;
+ } BIT;
+ } LVD2CR0;
+};
+
+struct st_usb {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :5;
+ unsigned short SCKE:1;
+ unsigned short :1;
+ unsigned short CNEN:1;
+ unsigned short :1;
+ unsigned short DCFM:1;
+ unsigned short DRPD:1;
+ unsigned short DPRPU:1;
+ unsigned short :3;
+ unsigned short USBE:1;
+ } BIT;
+ } SYSCFG;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVCMON:2;
+ unsigned short :7;
+ unsigned short HTACT:1;
+ unsigned short :3;
+ unsigned short IDMON:1;
+ unsigned short LNST:2;
+ } BIT;
+ } SYSSTS0;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short HNPBTOA:1;
+ unsigned short EXICEN:1;
+ unsigned short VBUSEN:1;
+ unsigned short WKUP:1;
+ unsigned short RWUPE:1;
+ unsigned short USBRST:1;
+ unsigned short RESUME:1;
+ unsigned short UACT:1;
+ unsigned short :1;
+ unsigned short RHST:3;
+ } BIT;
+ } DVSTCTR0;
+ char wk2[10];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } CFIFO;
+ char wk3[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D0FIFO;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D1FIFO;
+ char wk5[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short :3;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :2;
+ unsigned short ISEL:1;
+ unsigned short :1;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } CFIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } CFIFOCTR;
+ char wk6[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short DCLRM:1;
+ unsigned short DREQE:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :4;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } D0FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } D0FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short DCLRM:1;
+ unsigned short DREQE:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :4;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } D1FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } D1FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VBSE:1;
+ unsigned short RSME:1;
+ unsigned short SOFE:1;
+ unsigned short DVSE:1;
+ unsigned short CTRE:1;
+ unsigned short BEMPE:1;
+ unsigned short NRDYE:1;
+ unsigned short BRDYE:1;
+ } BIT;
+ } INTENB0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRCRE:1;
+ unsigned short BCHGE:1;
+ unsigned short :1;
+ unsigned short DTCHE:1;
+ unsigned short ATTCHE:1;
+ unsigned short :4;
+ unsigned short EOFERRE:1;
+ unsigned short SIGNE:1;
+ unsigned short SACKE:1;
+ unsigned short :3;
+ unsigned short PDDETINTE0:1;
+ } BIT;
+ } INTENB1;
+ char wk7[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BRDYE:1;
+ unsigned short PIPE8BRDYE:1;
+ unsigned short PIPE7BRDYE:1;
+ unsigned short PIPE6BRDYE:1;
+ unsigned short PIPE5BRDYE:1;
+ unsigned short PIPE4BRDYE:1;
+ unsigned short PIPE3BRDYE:1;
+ unsigned short PIPE2BRDYE:1;
+ unsigned short PIPE1BRDYE:1;
+ unsigned short PIPE0BRDYE:1;
+ } BIT;
+ } BRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9NRDYE:1;
+ unsigned short PIPE8NRDYE:1;
+ unsigned short PIPE7NRDYE:1;
+ unsigned short PIPE6NRDYE:1;
+ unsigned short PIPE5NRDYE:1;
+ unsigned short PIPE4NRDYE:1;
+ unsigned short PIPE3NRDYE:1;
+ unsigned short PIPE2NRDYE:1;
+ unsigned short PIPE1NRDYE:1;
+ unsigned short PIPE0NRDYE:1;
+ } BIT;
+ } NRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BEMPE:1;
+ unsigned short PIPE8BEMPE:1;
+ unsigned short PIPE7BEMPE:1;
+ unsigned short PIPE6BEMPE:1;
+ unsigned short PIPE5BEMPE:1;
+ unsigned short PIPE4BEMPE:1;
+ unsigned short PIPE3BEMPE:1;
+ unsigned short PIPE2BEMPE:1;
+ unsigned short PIPE1BEMPE:1;
+ unsigned short PIPE0BEMPE:1;
+ } BIT;
+ } BEMPENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :7;
+ unsigned short TRNENSEL:1;
+ unsigned short :1;
+ unsigned short BRDYM:1;
+ unsigned short :1;
+ unsigned short EDGESTS:1;
+ } BIT;
+ } SOFCFG;
+ char wk8[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VBINT:1;
+ unsigned short RESM:1;
+ unsigned short SOFR:1;
+ unsigned short DVST:1;
+ unsigned short CTRT:1;
+ unsigned short BEMP:1;
+ unsigned short NRDY:1;
+ unsigned short BRDY:1;
+ unsigned short VBSTS:1;
+ unsigned short DVSQ:3;
+ unsigned short VALID:1;
+ unsigned short CTSQ:3;
+ } BIT;
+ } INTSTS0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRCR:1;
+ unsigned short BCHG:1;
+ unsigned short :1;
+ unsigned short DTCH:1;
+ unsigned short ATTCH:1;
+ unsigned short :4;
+ unsigned short EOFERR:1;
+ unsigned short SIGN:1;
+ unsigned short SACK:1;
+ unsigned short :3;
+ unsigned short PDDETINT0:1;
+ } BIT;
+ } INTSTS1;
+ char wk9[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BRDY:1;
+ unsigned short PIPE8BRDY:1;
+ unsigned short PIPE7BRDY:1;
+ unsigned short PIPE6BRDY:1;
+ unsigned short PIPE5BRDY:1;
+ unsigned short PIPE4BRDY:1;
+ unsigned short PIPE3BRDY:1;
+ unsigned short PIPE2BRDY:1;
+ unsigned short PIPE1BRDY:1;
+ unsigned short PIPE0BRDY:1;
+ } BIT;
+ } BRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9NRDY:1;
+ unsigned short PIPE8NRDY:1;
+ unsigned short PIPE7NRDY:1;
+ unsigned short PIPE6NRDY:1;
+ unsigned short PIPE5NRDY:1;
+ unsigned short PIPE4NRDY:1;
+ unsigned short PIPE3NRDY:1;
+ unsigned short PIPE2NRDY:1;
+ unsigned short PIPE1NRDY:1;
+ unsigned short PIPE0NRDY:1;
+ } BIT;
+ } NRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BEMP:1;
+ unsigned short PIPE8BEMP:1;
+ unsigned short PIPE7BEMP:1;
+ unsigned short PIPE6BEMP:1;
+ unsigned short PIPE5BEMP:1;
+ unsigned short PIPE4BEMP:1;
+ unsigned short PIPE3BEMP:1;
+ unsigned short PIPE2BEMP:1;
+ unsigned short PIPE1BEMP:1;
+ unsigned short PIPE0BEMP:1;
+ } BIT;
+ } BEMPSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRN:1;
+ unsigned short CRCE:1;
+ unsigned short :3;
+ unsigned short FRNM:11;
+ } BIT;
+ } FRMNUM;
+ char wk10[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BREQUEST:8;
+ unsigned short BMREQUESTTYPE:8;
+ } BIT;
+ } USBREQ;
+ unsigned short USBVAL;
+ unsigned short USBINDX;
+ unsigned short USBLENG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short SHTNAK:1;
+ unsigned short :2;
+ unsigned short DIR:1;
+ } BIT;
+ } DCPCFG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DEVSEL:4;
+ unsigned short :5;
+ unsigned short MXPS:7;
+ } BIT;
+ } DCPMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short SUREQ:1;
+ unsigned short :2;
+ unsigned short SUREQCLR:1;
+ unsigned short :2;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :2;
+ unsigned short CCPL:1;
+ unsigned short PID:2;
+ } BIT;
+ } DCPCTR;
+ char wk11[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :12;
+ unsigned short PIPESEL:4;
+ } BIT;
+ } PIPESEL;
+ char wk12[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TYPE:2;
+ unsigned short :3;
+ unsigned short BFRE:1;
+ unsigned short DBLB:1;
+ unsigned short :1;
+ unsigned short SHTNAK:1;
+ unsigned short :2;
+ unsigned short DIR:1;
+ unsigned short EPNUM:4;
+ } BIT;
+ } PIPECFG;
+ char wk13[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DEVSEL:4;
+ unsigned short :3;
+ unsigned short MXPS:9;
+ } BIT;
+ } PIPEMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :3;
+ unsigned short IFIS:1;
+ unsigned short :9;
+ unsigned short IITV:3;
+ } BIT;
+ } PIPEPERI;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE1CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE2CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE3CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE4CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE5CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE6CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE7CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE8CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE9CTR;
+ char wk14[14];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE1TRE;
+ unsigned short PIPE1TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE2TRE;
+ unsigned short PIPE2TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE3TRE;
+ unsigned short PIPE3TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE4TRE;
+ unsigned short PIPE4TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE5TRE;
+ unsigned short PIPE5TRN;
+ char wk15[12];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PDDETSTS0:1;
+ unsigned short CHGDETSTS0:1;
+ unsigned short BATCHGE0:1;
+ unsigned short DCPMODE0:1;
+ unsigned short VDMSRCE0:1;
+ unsigned short IDPSINKE0:1;
+ unsigned short VDPSRCE0:1;
+ unsigned short IDMSINKE0:1;
+ unsigned short IDPSRCE0:1;
+ unsigned short RPDME0:1;
+ } BIT;
+ } USBBCCTRL0;
+ char wk16[26];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short VBRPDCUT:1;
+ unsigned short :6;
+ unsigned short VDDUSBE:1;
+ } BIT;
+ } USBMC;
+ char wk17[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD5;
+};
+
+enum enum_ir {
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,
+IR_CMT0_CMI0,
+IR_CMT1_CMI1,
+IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF,
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,
+IR_DOC_DOPCF=57,
+IR_RTC_CUP=63,
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,
+IR_LVD_LVD1=88,IR_LVD_LVD2,
+IR_USB0_USBR0,
+IR_RTC_ALM=92,IR_RTC_PRD,
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,
+IR_ELC_ELSR18I=106,
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,
+IR_POE_OEI1=170,IR_POE_OEI2,
+IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,
+IR_SCI12_ERI12=238,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0
+};
+
+enum enum_dtce {
+DTCE_ICU_SWINT=27,
+DTCE_CMT0_CMI0,
+DTCE_CMT1_CMI1,
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,
+DTCE_ELC_ELSR18I=106,
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0
+};
+
+enum enum_ier {
+IER_BSC_BUSERR=0x02,
+IER_ICU_SWINT=0x03,
+IER_CMT0_CMI0=0x03,
+IER_CMT1_CMI1=0x03,
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,
+IER_DOC_DOPCF=0x07,
+IER_RTC_CUP=0x07,
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,
+IER_USB0_USBR0=0x0B,
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,
+IER_ELC_ELSR18I=0x0D,
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F
+};
+
+enum enum_ipr {
+IPR_BSC_BUSERR=0,
+IPR_ICU_SWINT=3,
+IPR_CMT0_CMI0=4,
+IPR_CMT1_CMI1=5,
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,
+IPR_DOC_DOPCF=57,
+IPR_RTC_CUP=63,
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,
+IPR_USB0_USBR0=90,
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,
+IPR_ELC_ELSR18I=106,
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249,
+IPR_BSC_=0,
+IPR_CMT0_=4,
+IPR_CMT1_=5,
+IPR_RSPI0_=44,
+IPR_DOC_=57,
+IPR_ELC_=106,
+IPR_MTU1_TGI=121,
+IPR_MTU1_TCI=123,
+IPR_MTU2_TGI=125,
+IPR_MTU2_TCI=127,
+IPR_MTU3_TGI=129,
+IPR_MTU4_TGI=134,
+IPR_MTU5_=139,
+IPR_MTU5_TGI=139,
+IPR_SCI1_=218,
+IPR_SCI5_=222
+};
+
+#define IEN_BSC_BUSERR IEN0
+#define IEN_ICU_SWINT IEN3
+#define IEN_CMT0_CMI0 IEN4
+#define IEN_CMT1_CMI1 IEN5
+#define IEN_CAC_FERRF IEN0
+#define IEN_CAC_MENDF IEN1
+#define IEN_CAC_OVFF IEN2
+#define IEN_USB0_D0FIFO0 IEN4
+#define IEN_USB0_D1FIFO0 IEN5
+#define IEN_USB0_USBI0 IEN6
+#define IEN_RSPI0_SPEI0 IEN4
+#define IEN_RSPI0_SPRI0 IEN5
+#define IEN_RSPI0_SPTI0 IEN6
+#define IEN_RSPI0_SPII0 IEN7
+#define IEN_DOC_DOPCF IEN1
+#define IEN_RTC_CUP IEN7
+#define IEN_ICU_IRQ0 IEN0
+#define IEN_ICU_IRQ1 IEN1
+#define IEN_ICU_IRQ2 IEN2
+#define IEN_ICU_IRQ3 IEN3
+#define IEN_ICU_IRQ4 IEN4
+#define IEN_ICU_IRQ5 IEN5
+#define IEN_ICU_IRQ6 IEN6
+#define IEN_ICU_IRQ7 IEN7
+#define IEN_LVD_LVD1 IEN0
+#define IEN_LVD_LVD2 IEN1
+#define IEN_USB0_USBR0 IEN2
+#define IEN_RTC_ALM IEN4
+#define IEN_RTC_PRD IEN5
+#define IEN_S12AD_S12ADI0 IEN6
+#define IEN_S12AD_GBADI IEN7
+#define IEN_ELC_ELSR18I IEN2
+#define IEN_MTU0_TGIA0 IEN2
+#define IEN_MTU0_TGIB0 IEN3
+#define IEN_MTU0_TGIC0 IEN4
+#define IEN_MTU0_TGID0 IEN5
+#define IEN_MTU0_TCIV0 IEN6
+#define IEN_MTU0_TGIE0 IEN7
+#define IEN_MTU0_TGIF0 IEN0
+#define IEN_MTU1_TGIA1 IEN1
+#define IEN_MTU1_TGIB1 IEN2
+#define IEN_MTU1_TCIV1 IEN3
+#define IEN_MTU1_TCIU1 IEN4
+#define IEN_MTU2_TGIA2 IEN5
+#define IEN_MTU2_TGIB2 IEN6
+#define IEN_MTU2_TCIV2 IEN7
+#define IEN_MTU2_TCIU2 IEN0
+#define IEN_MTU3_TGIA3 IEN1
+#define IEN_MTU3_TGIB3 IEN2
+#define IEN_MTU3_TGIC3 IEN3
+#define IEN_MTU3_TGID3 IEN4
+#define IEN_MTU3_TCIV3 IEN5
+#define IEN_MTU4_TGIA4 IEN6
+#define IEN_MTU4_TGIB4 IEN7
+#define IEN_MTU4_TGIC4 IEN0
+#define IEN_MTU4_TGID4 IEN1
+#define IEN_MTU4_TCIV4 IEN2
+#define IEN_MTU5_TGIU5 IEN3
+#define IEN_MTU5_TGIV5 IEN4
+#define IEN_MTU5_TGIW5 IEN5
+#define IEN_POE_OEI1 IEN2
+#define IEN_POE_OEI2 IEN3
+#define IEN_SCI1_ERI1 IEN2
+#define IEN_SCI1_RXI1 IEN3
+#define IEN_SCI1_TXI1 IEN4
+#define IEN_SCI1_TEI1 IEN5
+#define IEN_SCI5_ERI5 IEN6
+#define IEN_SCI5_RXI5 IEN7
+#define IEN_SCI5_TXI5 IEN0
+#define IEN_SCI5_TEI5 IEN1
+#define IEN_SCI12_ERI12 IEN6
+#define IEN_SCI12_RXI12 IEN7
+#define IEN_SCI12_TXI12 IEN0
+#define IEN_SCI12_TEI12 IEN1
+#define IEN_SCI12_SCIX0 IEN2
+#define IEN_SCI12_SCIX1 IEN3
+#define IEN_SCI12_SCIX2 IEN4
+#define IEN_SCI12_SCIX3 IEN5
+#define IEN_RIIC0_EEI0 IEN6
+#define IEN_RIIC0_RXI0 IEN7
+#define IEN_RIIC0_TXI0 IEN0
+#define IEN_RIIC0_TEI0 IEN1
+
+#define VECT_BSC_BUSERR 16
+#define VECT_ICU_SWINT 27
+#define VECT_CMT0_CMI0 28
+#define VECT_CMT1_CMI1 29
+#define VECT_CAC_FERRF 32
+#define VECT_CAC_MENDF 33
+#define VECT_CAC_OVFF 34
+#define VECT_USB0_D0FIFO0 36
+#define VECT_USB0_D1FIFO0 37
+#define VECT_USB0_USBI0 38
+#define VECT_RSPI0_SPEI0 44
+#define VECT_RSPI0_SPRI0 45
+#define VECT_RSPI0_SPTI0 46
+#define VECT_RSPI0_SPII0 47
+#define VECT_DOC_DOPCF 57
+#define VECT_RTC_CUP 63
+#define VECT_ICU_IRQ0 64
+#define VECT_ICU_IRQ1 65
+#define VECT_ICU_IRQ2 66
+#define VECT_ICU_IRQ3 67
+#define VECT_ICU_IRQ4 68
+#define VECT_ICU_IRQ5 69
+#define VECT_ICU_IRQ6 70
+#define VECT_ICU_IRQ7 71
+#define VECT_LVD_LVD1 88
+#define VECT_LVD_LVD2 89
+#define VECT_USB0_USBR0 90
+#define VECT_RTC_ALM 92
+#define VECT_RTC_PRD 93
+#define VECT_S12AD_S12ADI0 102
+#define VECT_S12AD_GBADI 103
+#define VECT_ELC_ELSR18I 106
+#define VECT_MTU0_TGIA0 114
+#define VECT_MTU0_TGIB0 115
+#define VECT_MTU0_TGIC0 116
+#define VECT_MTU0_TGID0 117
+#define VECT_MTU0_TCIV0 118
+#define VECT_MTU0_TGIE0 119
+#define VECT_MTU0_TGIF0 120
+#define VECT_MTU1_TGIA1 121
+#define VECT_MTU1_TGIB1 122
+#define VECT_MTU1_TCIV1 123
+#define VECT_MTU1_TCIU1 124
+#define VECT_MTU2_TGIA2 125
+#define VECT_MTU2_TGIB2 126
+#define VECT_MTU2_TCIV2 127
+#define VECT_MTU2_TCIU2 128
+#define VECT_MTU3_TGIA3 129
+#define VECT_MTU3_TGIB3 130
+#define VECT_MTU3_TGIC3 131
+#define VECT_MTU3_TGID3 132
+#define VECT_MTU3_TCIV3 133
+#define VECT_MTU4_TGIA4 134
+#define VECT_MTU4_TGIB4 135
+#define VECT_MTU4_TGIC4 136
+#define VECT_MTU4_TGID4 137
+#define VECT_MTU4_TCIV4 138
+#define VECT_MTU5_TGIU5 139
+#define VECT_MTU5_TGIV5 140
+#define VECT_MTU5_TGIW5 141
+#define VECT_POE_OEI1 170
+#define VECT_POE_OEI2 171
+#define VECT_SCI1_ERI1 218
+#define VECT_SCI1_RXI1 219
+#define VECT_SCI1_TXI1 220
+#define VECT_SCI1_TEI1 221
+#define VECT_SCI5_ERI5 222
+#define VECT_SCI5_RXI5 223
+#define VECT_SCI5_TXI5 224
+#define VECT_SCI5_TEI5 225
+#define VECT_SCI12_ERI12 238
+#define VECT_SCI12_RXI12 239
+#define VECT_SCI12_TXI12 240
+#define VECT_SCI12_TEI12 241
+#define VECT_SCI12_SCIX0 242
+#define VECT_SCI12_SCIX1 243
+#define VECT_SCI12_SCIX2 244
+#define VECT_SCI12_SCIX3 245
+#define VECT_RIIC0_EEI0 246
+#define VECT_RIIC0_RXI0 247
+#define VECT_RIIC0_TXI0 248
+#define VECT_RIIC0_TEI0 249
+
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17
+#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0
+
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR
+#define _IR( x ) __IR( x )
+#define IR( x , y ) _IR( _ ## x ## _ ## y )
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE
+#define _DTCE( x ) __DTCE( x )
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x
+#define _IEN( x ) __IEN( x )
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR
+#define _IPR( x ) __IPR( x )
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )
+#define __VECT( x ) VECT ## x
+#define _VECT( x ) __VECT( x )
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )
+#define __MSTP( x ) MSTP ## x
+#define _MSTP( x ) __MSTP( x )
+#define MSTP( x ) _MSTP( _ ## x )
+
+#define BSC (*(volatile struct st_bsc *)0x81300)
+#define CAC (*(volatile struct st_cac *)0x8B000)
+#define CMT (*(volatile struct st_cmt *)0x88000)
+#define CMT0 (*(volatile struct st_cmt0 *)0x88002)
+#define CMT1 (*(volatile struct st_cmt0 *)0x88008)
+#define CRC (*(volatile struct st_crc *)0x88280)
+#define DA (*(volatile struct st_da *)0x880C0)
+#define DOC (*(volatile struct st_doc *)0x8B080)
+#define DTC (*(volatile struct st_dtc *)0x82400)
+#define ELC (*(volatile struct st_elc *)0x8B100)
+#define FLASH (*(volatile struct st_flash *)0x7FC090)
+#define ICU (*(volatile struct st_icu *)0x87000)
+#define IWDT (*(volatile struct st_iwdt *)0x88030)
+#define MPC (*(volatile struct st_mpc *)0x8C11F)
+#define MTU (*(volatile struct st_mtu *)0x8860A)
+#define MTU0 (*(volatile struct st_mtu0 *)0x88690)
+#define MTU1 (*(volatile struct st_mtu1 *)0x88690)
+#define MTU2 (*(volatile struct st_mtu2 *)0x88692)
+#define MTU3 (*(volatile struct st_mtu3 *)0x88600)
+#define MTU4 (*(volatile struct st_mtu4 *)0x88600)
+#define MTU5 (*(volatile struct st_mtu5 *)0x88694)
+#define POE (*(volatile struct st_poe *)0x88900)
+#define PORT (*(volatile struct st_port *)0x8C120)
+#define PORT0 (*(volatile struct st_port0 *)0x8C000)
+#define PORT1 (*(volatile struct st_port1 *)0x8C001)
+#define PORT2 (*(volatile struct st_port2 *)0x8C002)
+#define PORT3 (*(volatile struct st_port3 *)0x8C003)
+#define PORT4 (*(volatile struct st_port4 *)0x8C004)
+#define PORT5 (*(volatile struct st_port5 *)0x8C005)
+#define PORTA (*(volatile struct st_porta *)0x8C00A)
+#define PORTB (*(volatile struct st_portb *)0x8C00B)
+#define PORTC (*(volatile struct st_portc *)0x8C00C)
+#define PORTE (*(volatile struct st_porte *)0x8C00E)
+#define RIIC0 (*(volatile struct st_riic *)0x88300)
+#define RSPI0 (*(volatile struct st_rspi *)0x88380)
+#define RTC (*(volatile struct st_rtc *)0x8C400)
+#define RTCB (*(volatile struct st_rtcb *)0x8C402)
+#define S12AD (*(volatile struct st_s12ad *)0x89000)
+#define SCI1 (*(volatile struct st_sci1 *)0x8A020)
+#define SCI5 (*(volatile struct st_sci1 *)0x8A0A0)
+#define SCI12 (*(volatile struct st_sci12 *)0x8B300)
+#define SMCI1 (*(volatile struct st_smci *)0x8A020)
+#define SMCI5 (*(volatile struct st_smci *)0x8A0A0)
+#define SMCI12 (*(volatile struct st_smci *)0x8B300)
+#define SYSTEM (*(volatile struct st_system *)0x80000)
+#define USB0 (*(volatile struct st_usb *)0xA0000)
+#endif
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h
new file mode 100644
index 000000000..6ed672bf5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h
@@ -0,0 +1,112 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : mcu_info.h
+* Device(s) : RX111
+* Description : Information about the MCU on this board (RSKRX111).
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef _MCU_INFO
+#define _MCU_INFO
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Gets MCU configuration information. */
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* MCU Series. */
+#if MCU_PART_SERIES == 0x0
+ #define MCU_SERIES_RX100 (1)
+#else
+ #error "ERROR - MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"
+#endif
+
+/* MCU Group name. */
+#if MCU_PART_GROUP == 0x1
+ #define MCU_RX111 (1)
+ #define MCU_RX11x (1)
+#else
+ #error "ERROR - MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"
+#endif
+
+/* Package. */
+#if MCU_PART_PACKAGE == 0x0
+ #define PACKAGE_LFQFP64 (1)
+#elif MCU_PART_PACKAGE == 0x1
+ #define PACKAGE_LQFP64 (1)
+#elif MCU_PART_PACKAGE == 0x2
+ #define PACKAGE_TFLGA64 (1)
+#elif MCU_PART_PACKAGE == 0x3
+ #define PACKAGE_LFQFP48 (1)
+#elif MCU_PART_PACKAGE == 0x4
+ #define PACKAGE_VQFN48 (1)
+#elif MCU_PART_PACKAGE == 0x5
+ #define PACKAGE_HWQFN36 (1)
+#elif MCU_PART_PACKAGE == 0x6
+ #define PACKAGE_WFLGA36 (1)
+#elif MCU_PART_PACKAGE == 0x7
+ #define PACKAGE_SSOP36 (1)
+#else
+ #error "ERROR - MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"
+#endif
+
+/* Memory size of your MCU. */
+#if MCU_PART_MEMORY_SIZE == 0x0 // "J" parts
+ #define ROM_SIZE_BYTES (16384)
+ #define RAM_SIZE_BYTES (8192)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x1
+ #define ROM_SIZE_BYTES (32768)
+ #define RAM_SIZE_BYTES (10240)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x3
+ #define ROM_SIZE_BYTES (65536)
+ #define RAM_SIZE_BYTES (10240)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x4
+ #define ROM_SIZE_BYTES (98304)
+ #define RAM_SIZE_BYTES (16384)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x5
+ #define ROM_SIZE_BYTES (131072)
+ #define RAM_SIZE_BYTES (16384)
+ #define DF_SIZE_BYTES (8192)
+#else
+ #error "ERROR - MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"
+#endif
+
+/* System clock speed in Hz. */
+#define ICLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV)
+/* Peripheral Module Clock B speed in Hz. */
+#define PCLKB_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV)
+/* Peripheral Module Clock D speed in Hz. */
+#define PCLKD_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV)
+/* FlashIF clock speed in Hz. */
+#define FCLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV)
+
+#endif /* _MCU_INFO */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/typedefine.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/typedefine.h
new file mode 100644
index 000000000..a52e28687
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/mcu/rx111/typedefine.h
@@ -0,0 +1,25 @@
+/***********************************************************************/
+/* */
+/* PROJECT NAME : RTOSDemo_GCC */
+/* FILE : typedefine.h */
+/* DESCRIPTION : Aliases of Integer Type */
+/* CPU SERIES : RX100 */
+/* CPU TYPE : RX111 */
+/* */
+/* This file is generated by e2studio. */
+/* */
+/***********************************************************************/
+
+
+
+
+typedef signed char _SBYTE;
+typedef unsigned char _UBYTE;
+typedef signed short _SWORD;
+typedef unsigned short _UWORD;
+typedef signed int _SINT;
+typedef unsigned int _UINT;
+typedef signed long _SDWORD;
+typedef unsigned long _UDWORD;
+typedef signed long long _SQWORD;
+typedef unsigned long long _UQWORD;
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/platform.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/platform.h
new file mode 100644
index 000000000..3427aab94
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/platform.h
@@ -0,0 +1,88 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : platform.h
+* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using
+* is not listed below, please add your own or use the default 'User Board'.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 30.11.2011 1.00 First Release
+* : 13.01.2012 1.10 Moved from having platform defined using macro defintion, to having platform defined
+* by choosing an include path. This makes this file simpler and cleans up the issue
+* where HEW shows all header files for all platforms under 'Dependencies'.
+* : 14.02.2012 1.20 Added RX210 BSP.
+* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding
+* locking.c and locking.h in board folders. Also, r_bsp can now be configured through
+* r_bsp_config.h.
+* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using
+* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort
+* to remove any extra files that the user would need to touch. Removed the flash_options.c
+* file and put its contents in vecttbl.c.
+* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT
+* macro options in r_bsp_config.h. Added some extra code to handle exceptions in
+* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.
+* : 08.11.2012 1.60 Added RX111 BSP
+***********************************************************************************************************************/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+/***********************************************************************************************************************
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.
+***********************************************************************************************************************/
+/* RSKRX610 */
+//#include "./board/rskrx610/r_bsp.h"
+
+/* RSKRX62N */
+//#include "./board/rskrx62n/r_bsp.h"
+
+/* RSKRX62T */
+//#include "./board/rskrx62t/r_bsp.h"
+
+/* RDKRX62N */
+//#include "./board/rdkrx62n/r_bsp.h"
+
+/* RSKRX630 */
+//#include "./board/rskrx630/r_bsp.h"
+
+/* RSKRX63N */
+//#include "./board/rskrx63n/r_bsp.h"
+
+/* RDKRX63N */
+//#include "./board/rdkrx63n/r_bsp.h"
+
+/* RSKRX210 */
+//#include "./board/rskrx210/r_bsp.h"
+
+/* RSKRX111 */
+#include "./board/rskrx111/r_bsp.h"
+
+/* User Board - Define your own board here. */
+//#include "./board/user/r_bsp.h"
+
+/***********************************************************************************************************************
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT
+***********************************************************************************************************************/
+#ifndef PLATFORM_DEFINED
+#error "Error - No platform defined in platform.h!"
+#endif
+
+#endif /* _PLATFORM_H_ */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/r_bsp_config.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/r_bsp_config.h
new file mode 100644
index 000000000..537479e8a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/r_bsp_config.h
@@ -0,0 +1,250 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.c
+* Device(s) : RX111
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 51 11 5 A D FM
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)
+ | | | | | | |______not used = Blank
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________MCU_PART_GROUP = Group name
+ | | | |______________MCU_PART_SERIES = Series name
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FM = 0x0 = LFQFP/64/0.50
+ FK = 0x1 = LQFP/64/0.80
+ LF = 0x2 = TFLGA/64/0.50
+ FL = 0x3 = LFQFP/48/0.50
+ NE = 0x4 = VQFN/48/0.50
+ NC = 0x5 = HWQFN/36/0.50
+ LM = 0x6 = WFLGA/36/0.50
+ SB = 0x7 = SSOP/36/0.80
+*/
+#define MCU_PART_PACKAGE (0x0)
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 5 = 0x5 = 128KB/16KB/8KB
+ 4 = 0x4 = 96KB/16KB/8KB
+ 3 = 0x3 = 64KB/10KB/8KB
+ 1 = 0x1 = 32KB/10KB/8KB
+ J = 0x0 = 16KB/8KB/8KB
+*/
+#define MCU_PART_MEMORY_SIZE (0x5)
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 10 = 0x0 = RX110 Group
+ 11 = 0x1 = RX111 Group
+*/
+#define MCU_PART_GROUP (0x1)
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 51 = 0x0 = RX100 Series
+*/
+#define MCU_PART_SERIES (0x0)
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define MCU_PART_MEMORY_TYPE (0x0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize su=0x400
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize si=0x100
+#endif
+
+/* Heap size in bytes. */
+#define HEAP_BYTES (0x001)
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define RUN_IN_USER_MODE (0)
+
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = RTOS is used.
+*/
+#define RTOS_USED (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define CLOCK_SOURCE (4) // GI org 4
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the
+ settings would be:
+
+ XTAL_HZ = 16000000
+ PLL_DIV = 2
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz
+*/
+/* XTAL - Input clock frequency in Hz */
+#define XTAL_HZ (16000000)
+/* PLL Input Frequency Divider Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /4
+*/
+#define PLL_DIV (2) // GI org 2
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x6, x8
+*/
+#define PLL_MUL (6) // GI org 6
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define ICK_DIV (2) // NOTE: ICLK CANNOT BE SLOWER THAN PCLK!
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKB_DIV (2) // GI org 2
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKD_DIV (2)
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define FCK_DIV (2)
+
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a
+ function to be called when the event occurs. For example, if the user wanted the function
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would
+ do the following:
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+ If the user does not wish to be alerted of these events then they should comment out the macros.
+
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it
+ is executing. For this reason, it is recommended to keep these callback functions short as to not
+ decrease the real-time response of your system.
+*/
+/* Callback for Supervisor Instruction Violation Exception. */
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb
+
+/* Callback for Undefined Instruction Exception. */
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb
+
+/* Callback for Non-maskable Interrupt. */
+//#define NMI_ISR_CALLBACK nmi_cb
+
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source
+ is creating unwanted interrupts. */
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+
+/* Callback for Bus Error Interrupt. */
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb
+
+/* The user has the option of separately choosing little or big endian for the User Application Area */
+
+/* Endian mode for User Application.
+ 0 = Big Endian
+ Else = Little Endian (Default)
+*/
+#define USER_APP_ENDIAN (1)
+
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ OFS0 - Option Function Select Register 0
+ b31:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1) */
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select
+ 0 1 0 0: 3.10 V
+ 0 1 0 1: 3.00 V
+ 0 1 1 0: 2.90 V
+ 0 1 1 1: 2.79 V
+ 1 0 0 0: 2.68 V
+ 1 0 0 1: 2.58 V
+ 1 0 1 0: 2.48 V
+ 1 0 1 1: 2.06 V
+ 1 1 0 0: 1.96 V
+ 1 1 0 1: 1.86 V
+ b3:b2 Reserved (set to 1)
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define IO_LIB_ENABLE (0)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/readme.txt b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/readme.txt
new file mode 100644
index 000000000..c7ee2b751
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_bsp/readme.txt
@@ -0,0 +1,100 @@
+r_bsp Package
+=============
+
+Document Number
+---------------
+N/A
+
+Version
+-------
+v1.60
+
+Overview
+--------
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder has iodefine
+files and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each
+supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.
+
+Features
+--------
+* Provides foundation to build code on top of.
+* Provides MCU startup code.
+* Provides SFR access through iodefine.h
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.
+* Easily configure BSP through r_bsp_config.h.
+* Choose MCU easily by inputting part number details in r_bsp_config.h.
+* Provides callbacks for MCU exceptions and the bus error interrupt.
+
+Limitations
+-----------
+N/A
+
+Peripherals Used Directly
+-------------------------
+N/A
+
+Required Packages
+-----------------
+* r_glyph [required if you want to use LCD for RDK boards]
+* r_rspi_rx [required if you want to use LCD for RDK boards]
+
+How to add to your project
+--------------------------
+* Copy the r_bsp folder to your project.
+* Add an include path to the 'r_bsp' directory.
+* Add all of the source files for your board from the 'r_bsp\board\--YOUR_BOARD--' directory to your project.
+* Uncomment the include path for your board in 'platform.h' which is located in the 'r_bsp' directory.
+* Copy the file r_bsp_config_reference.h from the 'r_bsp\board\--YOUR_BOARD--' directory and copy it to your project's
+ source code directory. Rename the file r_bsp_config.h.
+* Open r_bsp_config.h and use the macros to configure the BSP for your project.
+
+File Structure
+--------------
+r_bsp
+| platform.h (choose which board is being used)
+| readme.txt
+|
++---board (contains supported boards)
+| +---rdkrx62n (contains BSP source and header files)
+| |
+| +---rdkrx63n
+| |
+| +---rskrx111
+| |
+| +---rskrx210
+| |
+| +---rskrx610
+| |
+| +---rskrx62n
+| |
+| +---rskrx62t
+| |
+| +---rskrx630
+| |
+| +---rskrx63n
+| |
+| \---user
+|
+\---mcu
+ +---rx111 (contains common files to this MCU group, e.g. iodefine.h)
+ |
+ +---rx210
+ |
+ +---rx610
+ |
+ +---rx62n
+ |
+ +---rx62t
+ |
+ +---rx630
+ |
+ \---rx63n
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/doc/r_switches.docx b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/doc/r_switches.docx
new file mode 100644
index 000000000..6fe7e86e5
Binary files /dev/null and b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/doc/r_switches.docx differ
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/r_switches_config.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/r_switches_config.h
new file mode 100644
index 000000000..ba6d58f00
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/r_switches_config.h
@@ -0,0 +1,47 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_config.c
+* Description : Configures the switches code
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+#ifndef SWITCHES_CONFIG_HEADER_FILE
+#define SWITCHES_CONFIG_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* This macro sets whether interrupts or polling is used for detecting switch presses. The benefit of using interrupts
+ is that no extra processing is used for polling and the use of a system timer tick is not a requirement. The downside
+ of using interrupts is that callback functions are called from within an interrupt so if your ISR is long then it can
+ degrade the real-time response of your system. The benefit of polling is that functions are called at the application
+ level and debouncing is supported. The downside to polling is that your system must call the R_SWITCHES_Update() on a
+ regular basis which requires extra processing.
+
+ 0 = Use interrupts
+ 1 = Use polling
+ */
+#define SWITCHES_DETECTION_MODE (0)
+
+#endif /* SWITCHES_CONFIG_HEADER_FILE */
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/r_switches_if.h b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/r_switches_if.h
new file mode 100644
index 000000000..b08f8f546
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/r_switches_if.h
@@ -0,0 +1,72 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_if.h
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+
+#ifndef SWITCHES_API_HEADER_FILE
+#define SWITCHES_API_HEADER_FILE
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed width integer support. */
+#include
+/* Used for configuring the code */
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Version Number of API. */
+#define SWITCHES_VERSION_MAJOR (1)
+#define SWITCHES_VERSION_MINOR (0)
+/* The process of getting the version number is done through the macro below. The version number is encoded where the
+ top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example,
+ Version 4.25 would be returned as 0x00040019. */
+#define R_SWITCHES_GetVersion() ((((uint32_t)SWITCHES_VERSION_MAJOR) << 16) | (uint32_t)SWITCHES_VERSION_MINOR)
+
+/***********************************************************************************************************************
+Public Functions
+***********************************************************************************************************************/
+void R_SWITCHES_Init(void);
+void R_SWITCHES_Update(void);
+
+/* Callback prototypes. */
+#if defined(SW1_CALLBACK_FUNCTION)
+void SW1_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW2_CALLBACK_FUNCTION)
+void SW2_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW3_CALLBACK_FUNCTION)
+void SW3_CALLBACK_FUNCTION(void);
+#endif
+
+#endif /* SWITCHES_API_HEADER_FILE */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/readme.txt b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/readme.txt
new file mode 100644
index 000000000..d1e1e40fb
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/readme.txt
@@ -0,0 +1,83 @@
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION
+
+Switches
+========
+
+Document Number
+---------------
+N/A
+
+Version
+-------
+v1.40
+
+Overview
+--------
+Configures port pins for switches and calls user defined function on switch press. Switch presses can be detected using
+IRQ interrupts or by polling. The benefit of using interrupts is that no extra processing is used for polling and the
+use of a system timer tick is not a requirement. The downside of using interrupts is that callback functions are called
+from within an interrupt so if your ISR is long then it can degrade the real-time response of your system. The benefit
+of polling is that functions are called at the application level and debouncing is supported. The downside to polling is
+that your system must call the R_SWITCHES_Update() on a regular basis which requires extra processing.
+
+Features
+--------
+* Call one function to setup switches.
+* Define function to call when switch is pressed.
+* Can be configured to be interrupt or poll driven.
+
+Supported MCUs
+--------------
+* RX610 Group
+* RX621, RX62N Group
+* RX62T Group
+* RX630 Group
+* RX631, RX63N Group
+* RX210 Group
+* RX111 Group
+
+Boards Tested On
+----------------
+* RSKRX610
+* RSK+RX62N
+* RSKRX62T
+* RDKRX62N
+* RSKRX630
+* RSKRX63N
+* RDKRX63N
+* RSKRX111
+
+Limitations
+-----------
+* None
+
+Peripherals Used Directly
+-------------------------
+* None
+
+Required Packages
+-----------------
+* None
+
+How to add to your project
+--------------------------
+* Add src\r_switches.c to your project.
+* Add an include path to the 'r_switches' directory.
+* Add an include path to the 'r_switches\src' directory.
+* Configure middleware through r_switches_config.h.
+* Add a #include for r_switches_if.h to files that need to use this package.
+
+Toolchain(s) Used
+-----------------
+* Renesas RX v1.02
+
+File Structure
+--------------
+r_switches
+| readme.txt
+| r_switches_config.h
+| r_switches_if.h
+|
+\---src
+ r_switches.c
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/src/r_switches.c b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/src/r_switches.c
new file mode 100644
index 000000000..601383563
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/Renesas_Files/r_switches/src/r_switches.c
@@ -0,0 +1,232 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches.c
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+* : 07.11.2012 1.40 Added support for RSKRX111
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Board and MCU support. */
+#include "platform.h"
+/* Switches prototypes. */
+#include "r_switches_if.h"
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+typedef int bool;
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* This helps reduce the amount of unique code for each supported board. */
+#define X_IRQ( x ) XX_IRQ( x )
+#define XX_IRQ( x ) _ICU_IRQ##x
+
+/* These macros define which IRQ pins are used for the switches. Note that these defintions cannot have parentheses
+ around them. */
+#if defined(PLATFORM_BOARD_RSKRX111)
+ #define SW1_IRQ_NUMBER 0
+ #define SW2_IRQ_NUMBER 1
+ #define SW3_IRQ_NUMBER 4
+#else
+ #error This file is only for use on the RX100 RSK
+#endif
+
+/* Number of switches on this board. */
+#define SWITCHES_NUM (3)
+
+/* Register definitions not yet correct in iorx111.h. */
+#define MPC_P30PFS_REG ( * ( unsigned char * ) 0x0008C158 )
+#define MPC_P31PFS_REG ( * ( unsigned char * ) 0x0008C159 )
+#define MPC_PE4PFS_REG ( * ( unsigned char * ) 0x0008C1B4 )
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef struct
+{
+ bool active;
+ int32_t debounce_cnt;
+} switch_t;
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+#if SWITCHES_DETECTION_MODE == 1
+/* Update Hz */
+static uint32_t g_sw_debounce_cnts;
+/* Used for debounce. */
+switch_t g_switches[SWITCHES_NUM];
+#endif
+
+/***********************************************************************************************************************
+* Function Name: R_SWITCHES_Init
+* Description : Initializes pins to be input and interrupt on switch presses.
+* Arguments :
+* Return Value : none
+***********************************************************************************************************************/
+
+void R_SWITCHES_Init (void)
+{
+ /* Unlock protection register */
+ MPC.PWPR.BYTE &= 0x7F;
+ /* Unlock MPC registers */
+ MPC.PWPR.BYTE |= 0x40;
+
+ /* Make switch pins inputs. */
+ PORT3.PDR.BYTE &= 0xFC;
+ PORTE.PDR.BYTE &= 0xEF;
+
+ /* Set port mode registers for switches. */
+ PORT3.PMR.BYTE &= 0xFC;
+ PORTE.PMR.BYTE &= 0xEF;
+
+ MPC_P30PFS_REG = 0x40; /* P30 is used as IRQ pin */
+ MPC_P31PFS_REG = 0x40; /* P31 is used as IRQ pin */
+ MPC_PE4PFS_REG = 0x40; /* PE4 is used as IRQ pin */
+
+ /* Set IRQ type (falling edge) */
+ ICU.IRQCR[ SW1_IRQ_NUMBER ].BYTE = 0x04;
+ ICU.IRQCR[ SW2_IRQ_NUMBER ].BYTE = 0x04;
+ ICU.IRQCR[ SW3_IRQ_NUMBER ].BYTE = 0x04;
+
+ /* Set interrupt priorities, which must be below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ _IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+ _IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+ _IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Clear any pending interrupts */
+ _IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;
+ _IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;
+ _IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;
+
+ /* Enable the interrupts */
+ _IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;
+ _IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;
+ _IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;
+}
+
+/* If using polling then the user must call the update function. */
+
+/***********************************************************************************************************************
+* Function name: R_SWITCHES_Update
+* Description : Polls switches and calls callback functions as needed. If you are using IRQ mode then this function
+* is not needed and can be removed if desired. It is left in so that code will not fail when switching
+* between polling or IRQ mode.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void R_SWITCHES_Update (void)
+{
+#if SWITCHES_DETECTION_MODE == 1
+ /* This code is only needed for polling mode. */
+ /* Check switch 1. */
+ if (SW1 == SW_ACTIVE)
+ {
+ if (g_switches[0].active != true)
+ {
+ if (++g_switches[0].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[0].active = true;
+
+ /* Call callback function. */
+ SW1_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[0].debounce_cnt)
+ {
+ g_switches[0].active = false;
+ }
+ else
+ {
+ g_switches[0].debounce_cnt--;
+ }
+ }
+
+ /* Check switch 2. */
+ if (SW2 == SW_ACTIVE)
+ {
+ if (g_switches[1].active != true)
+ {
+ if (++g_switches[1].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[1].active = true;
+
+ /* Call callback function. */
+ SW2_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[1].debounce_cnt)
+ {
+ g_switches[1].active = false;
+ }
+ else
+ {
+ g_switches[1].debounce_cnt--;
+ }
+ }
+
+ /* Check switch 3. */
+ if (SW3 == SW_ACTIVE)
+ {
+ if (g_switches[2].active != true)
+ {
+ if (++g_switches[2].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[2].active = true;
+
+ /* Call callback function. */
+ SW3_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[2].debounce_cnt)
+ {
+ g_switches[2].active = false;
+ }
+ else
+ {
+ g_switches[2].debounce_cnt--;
+ }
+ }
+#endif /* SWITCHES_DETECTION_MODE */
+}
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/main.c b/FreeRTOS/Demo/RX100-RSK_IAR/main.c
new file mode 100644
index 000000000..c2d786b2c
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/main.c
@@ -0,0 +1,211 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ * This project provides two demo applications. A low power project that
+ * demonstrates the FreeRTOS tickless mode, and a more comprehensive test and
+ * demo application. The configCREATE_LOW_POWER_DEMO setting (defined at the
+ * top of FreeRTOSConfig.h) is used to select between the two. The low power
+ * demo is implemented and described in main_low_power.c. The more
+ * comprehensive test and demo application is implemented and described in
+ * main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Platform includes. */
+#include "lcd.h"
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Prepare the board of the demo.
+ */
+extern void vHardwareSetup( void );
+
+/*
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.
+ */
+extern void main_low_power( void );
+extern void main_full( void );
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file. */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* See the documentation page for this demo on the FreeRTOS.org web site for
+full information - including hardware setup requirements. */
+
+void main( void )
+{
+ /* Call the Renesas provided setup. */
+ vHardwareSetup();
+ lcd_initialize();
+ lcd_display( LCD_LINE1, "FreeRTOS" );
+
+ /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */
+ #if configCREATE_LOW_POWER_DEMO == 1
+ {
+ lcd_display( LCD_LINE2, "LP Demo" );
+ main_low_power();
+ }
+ #else
+ {
+ lcd_display( LCD_LINE2, "Ful Demo" );
+ main_full();
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size
+ of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE
+ in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
+ called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* This function will be called by each tick interrupt if
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
+ added here, but the tick hook is called from an interrupt context, so
+ code must not attempt to block, and only the interrupt safe FreeRTOS API
+ functions can be used (those that end in FromISR()). */
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile unsigned long ul = 0;
+
+ taskENTER_CRITICAL();
+ {
+ /* Set ul to a non-zero value using the debugger to step out of this
+ function. */
+ while( ul == 0 )
+ {
+ __asm volatile( "NOP" );
+ }
+ }
+ taskEXIT_CRITICAL();
+}
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c b/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c
new file mode 100644
index 000000000..1380948db
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/main_full.c
@@ -0,0 +1,346 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* ****************************************************************************
+ * This project includes a lot of tasks and tests and is therefore complex.
+ * If you would prefer a much simpler project to get started with then select
+ * the 'low power' demo by setting configCREATE_LOW_POWER_DEMO to 1 in
+ * FreeRTOSConfig.h. When configCREATE_LOW_POWER_DEMO is set to 1 main() will
+ * call main_low_power() instead of main_full().
+ * ****************************************************************************
+ *
+ * Creates all the demo application tasks, then starts the scheduler. The web
+ * documentation provides more details of the standard demo application tasks,
+ * which provide no particular functionality but do provide a good example of
+ * how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill the registers with known values, then
+ * repeatedly check that each register still contains its expected value for
+ * the lifetime of the tasks. Each task uses different values. The tasks run
+ * with very low priority so get preempted very frequently. A check variable
+ * is incremented on each iteration of the test loop. A register containing an
+ * unexpected value is indicative of an error in the context switching
+ * mechanism and will result in a branch to a null loop - which in turn will
+ * prevent the check variable from incrementing any further and allow the check
+ * timer (described below) to determine that an error has occurred. The nature
+ * of the reg test tasks necessitates that they are written in assembly code.
+ *
+ * "Check Timer" and Callback Function - The check timer period is initially
+ * set to three seconds. The check timer callback function checks that all the
+ * standard demo tasks are not only still executing, but are executing without
+ * reporting any errors. If the check timer discovers that a task has either
+ * stalled, or reported an error, then it changes its own period from the
+ * initial three seconds, to just 200ms. The check timer callback function
+ * also toggles LED 0 each time it is called. This provides a visual
+ * indication of the system status: If the LED toggles every three seconds,
+ * then no issues have been discovered. If the LED toggles every 200ms, then
+ * an issue has been discovered with at least one task.
+ *
+ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started.
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.
+*/
+
+/* Standard includes. */
+#include
+
+/* Hardware specific includes. */
+#include "iorx111.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo includes. */
+#include "partest.h"
+#include "death.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+
+
+/* Variables that are incremented on each iteration of the reg test tasks are
+declared outside of the #if configCREATE_LOW_POWER_DEMO conditional compilation
+to prevent linker issues when configCREATE_LOW_POWER_DEMO is set to 1. The
+check timer inspects these variables to ensure they are still incrementing as
+expected. If a variable stops incrementing then it is likely that its associate
+task has stalled. */
+unsigned long volatile ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;
+
+
+/* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set
+to 0, otherwise the code in main_low_power.c is used. */
+#if configCREATE_LOW_POWER_DEMO == 0
+
+
+/* Values that are passed into the reg test tasks using the task parameter.
+The tasks check that the values are passed in correctly. */
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )
+
+/* Priorities at which the standard demo tasks are created. */
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+
+/* The LED toggled by the check timer. */
+#define mainCHECK_LED ( 0 )
+
+/* The period at which the check timer will expire, in ms, provided no errors
+have been reported by any of the standard demo tasks. ms are converted to the
+equivalent in ticks using the portTICK_RATE_MS constant. */
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
+
+/* The period at which the check timer will expire, in ms, if an error has been
+reported in one of the standard demo tasks. ms are converted to the equivalent
+in ticks using the portTICK_RATE_MS constant. */
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
+
+/* A block time of zero simple means "Don't Block". */
+#define mainDONT_BLOCK ( 0UL )
+
+/*
+ * The reg test tasks as described at the top of this file.
+ */
+static void prvRegTest1Task( void *pvParameters );
+static void prvRegTest2Task( void *pvParameters );
+
+/*
+ * The actual implementation of the reg test functionality, which, because of
+ * the direct register access, have to be in assembly.
+ */
+void vRegTest1Implementation( void );
+void vRegTest2Implementation( void );
+
+/*
+ * The check timer callback function, as described at the top of this file.
+ */
+static void prvCheckTimerCallback( xTimerHandle xTimer );
+
+
+/*-----------------------------------------------------------*/
+
+/* The check timer. This uses prvCheckTimerCallback() as its callback
+function. */
+static xTimerHandle xCheckTimer = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+ /* Start the reg test tasks which test the context switching mechanism. */
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+ /* Create the standard demo tasks. */
+ vCreateBlockTimeTasks();
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
+ vStartRecursiveMutexTasks();
+
+ /* The suicide tasks must be created last as they need to know how many
+ tasks were running prior to their creation in order to ascertain whether
+ or not the correct/expected number of tasks are running at any given time. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Create the software timer that performs the 'check' functionality,
+ as described at the top of this file. */
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
+ );
+
+ configASSERT( xCheckTimer );
+
+ /* Start the check timer. It will actually start when the scheduler is
+ started. */
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );
+
+ /* Start the tasks running. */
+ vTaskStartScheduler();
+
+ /* If all is well execution will never reach here as the scheduler will be
+ running. If this null loop is reached then it is likely there was
+ insufficient FreeRTOS heap available for the idle task and/or timer task to
+ be created. See http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTimerCallback( xTimerHandle xTimer )
+{
+static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS;
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;
+
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) xTimer;
+
+ /* Check the standard demo tasks are running without error. */
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ /* Check the reg test tasks are still cycling. They will stop incrementing
+ their loop counters if they encounter an error. */
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ /* Remember the loop counter values this time around so they can be checked
+ again the next time this callback function executes. */
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;
+
+ /* Toggle the check LED to give an indication of the system status. If
+ the LED toggles every three seconds then everything is ok. A faster toggle
+ indicates an error. */
+ vParTestToggleLED( mainCHECK_LED );
+
+ /* Was an error detected this time through the callback execution? */
+ if( lErrorStatus != pdPASS )
+ {
+ if( lChangedTimerPeriodAlready == pdFALSE )
+ {
+ lChangedTimerPeriodAlready = pdTRUE;
+
+ /* This call to xTimerChangePeriod() uses a zero block time.
+ Functions called from inside of a timer callback function must
+ *never* attempt to block. */
+ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest1Task( void *pvParameters )
+{
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )
+ {
+ /* The parameter did not contain the expected value. */
+ for( ;; )
+ {
+ /* Stop the tick interrupt so its obvious something has gone wrong. */
+ taskDISABLE_INTERRUPTS();
+ }
+ }
+
+ /* This is an inline asm function that never returns. */
+ vRegTest1Implementation();
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest2Task( void *pvParameters )
+{
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )
+ {
+ /* The parameter did not contain the expected value. */
+ for( ;; )
+ {
+ /* Stop the tick interrupt so its obvious something has gone wrong. */
+ taskDISABLE_INTERRUPTS();
+ }
+ }
+
+ /* This is an inline asm function that never returns. */
+ vRegTest2Implementation();
+}
+/*-----------------------------------------------------------*/
+
+#endif /* configCREATE_LOW_POWER_DEMO */
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c b/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c
new file mode 100644
index 000000000..1a3f6d035
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/main_low_power.c
@@ -0,0 +1,437 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* ****************************************************************************
+ * When configCREATE_LOW_POWER_DEMO is set to 1 in FreeRTOSConfig.h main() will
+ * call main_low_power(), which is defined in this file. main_low_power()
+ * demonstrates FreeRTOS tick suppression being used to allow the MCU to be
+ * placed into both the low power deep sleep mode and the low power software
+ * standby mode. When configCREATE_LOW_POWER_DEMO is set to 0 main will
+ * instead call main_full(), which is a more comprehensive RTOS demonstration.
+ * ****************************************************************************
+ *
+ * This application demonstrates the FreeRTOS tickless idle mode (tick
+ * suppression). See http://www.freertos.org/low-power-tickless-rtos.html
+ * The demo is configured to execute on the Renesas RX100 RSK.
+ *
+ * Functionality:
+ *
+ * + Two tasks are created, an Rx task and a Tx task.
+ *
+ * + The Rx task repeatedly blocks on a queue to wait for data. The Rx task
+ * toggles LED 0 each time is receives a value from the queue.
+ *
+ * + The Tx task repeatedly enters the Blocked state for an amount of time
+ * that is set by the position of the potentiometer. On exiting the blocked
+ * state the Tx task sends a value through the queue to the Rx task (causing
+ * the Rx task to exit the blocked state and toggle LED 0).
+ *
+ * If the value read from the potentiometer is less than or equal to
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks for the equivalent
+ * number of milliseconds. For example, if the sampled analog value is
+ * 2000, then the Tx task blocks for 2000ms. Blocking for a finite period
+ * allows the kernel to stop the tick interrupt and place the RX100 into
+ * deep sleep mode.
+ *
+ * If the value read form the potentiometer is greater than
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks on a semaphore with
+ * an infinite timeout. Blocking with an infinite timeout allows the kernel
+ * to stop the tick interrupt and place the RX100 into software standby
+ * mode. Pressing a button will generate an interrupt that causes the RX100
+ * to exit software standby mode. The interrupt service routine 'gives' the
+ * semaphore to unblock the Tx task.
+ *
+ *
+ * Using the Demo and Observed Behaviour:
+ *
+ * 1) Turn the potentiometer completely counter clockwise.
+ *
+ * 2) Program the RX100 with the application, then disconnect the programming/
+ * debugging hardware to ensure power readings are not effected by any
+ * connected interfaces.
+ *
+ * 3) Start the application running. LED 0 will toggle quickly because the
+ * potentiometer is turned to its lowest value. LED 1 will be illuminated
+ * when the RX100 is not in a power saving mode, but will appear to be off
+ * because most execution time is spent in a sleep mode. Led 2 will be
+ * illuminated when the RX100 is in deep sleep mode, and will appear to be
+ * always on, again because most execution time is spent in deep sleep mode.
+ * The LEDs are turned on and off by the application defined pre and post
+ * sleep macros (see the definitions of configPRE_SLEEP_PROCESSING() and
+ * configPOST_SLEEP_PROCESSING() in FreeRTOSConfig.h).
+ *
+ * 4) Slowly turn the potentiometer in the clockwise direction. This will
+ * increase the value read from the potentiometer, which will increase the
+ * time the Tx task spends in the Blocked state, which will therefore
+ * decrease the frequency at which the Tx task sends data to the queue (and
+ * the rate at which LED 0 is toggled).
+ *
+ * 5) Keep turning the potentiometer in the clockwise direction. Eventually
+ * the value read from the potentiometer will go above
+ * mainSOFTWARE_STANDBY_DELAY, causing the Tx task to block on the semaphore
+ * with an infinite timeout. LED 0 will stop toggling because the Tx task is
+ * no longer sending to the queue. LED 1 and LED 2 will both be off because
+ * the RX100 is neither running or in deep sleep mode (it is in software
+ * standby mode).
+ *
+ * 6) Turn the potentiometer counter clockwise again to ensure its value goes
+ * back below mainSOFTWARE_STANDBY_DELAY.
+ *
+ * 7) Press any of the three buttons to generate an interrupt. The interrupt
+ * will take the RX100 out of software standby mode, and the interrupt
+ * service routine will unblock the Tx task by 'giving' the semaphore. LED 0
+ * will then start to toggle again.
+ *
+ */
+
+
+/* Hardware specific includes. */
+#include "platform.h"
+#include "r_switches_if.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Common demo includes. */
+#include "partest.h"
+
+/* Priorities at which the Rx and Tx tasks are created. */
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+
+/* The number of items the queue can hold. This is 1 as the Rx task will
+remove items as they are added so the Tx task should always find the queue
+empty. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/* The LED used to indicate that a value has been received on the queue. */
+#define mainQUEUE_LED ( 0 )
+
+/* The LED used to indicate that full power is being used (the MCU is not in
+deep sleep or software standby mode). */
+#define mainFULL_POWER_LED ( 1 )
+
+/* The LED used to indicate that deep sleep mode is being used. */
+#define mainDEEP_SLEEP_LED ( 2 )
+
+/* The Tx task sends to the queue with a frequency that is set by the value
+read from the potentiometer until the value goes above that set by the
+mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks
+indefinitely on a semaphore. */
+#define mainSOFTWARE_STANDBY_DELAY ( 3000UL )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK ( 0 )
+
+/* The value that is sent from the Tx task to the Rx task on the queue. */
+#define mainQUEUED_VALUE ( 100UL )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The Rx and Tx tasks as described at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Reads and returns the value of the ADC connected to the potentiometer built
+ * onto the RSK.
+ */
+static unsigned short prvReadPOT( void );
+
+/*
+ * The handler for the interrupt generated when any of the buttons are pressed.
+ */
+__interrupt void vButtonInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue to pass data from the Tx task to the Rx task. */
+static xQueueHandle xQueue = NULL;
+
+/* The semaphore that is 'given' by interrupts generated from button pushes. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_low_power( void )
+{
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+ configASSERT( xQueue );
+
+ /* Create the semaphore that is 'given' by an interrupt generated from a
+ button push. */
+ vSemaphoreCreateBinary( xSemaphore );
+ configASSERT( xSemaphore );
+
+ /* Make sure the semaphore starts in the expected state - no button pushes
+ have yet occurred. A block time of zero can be used as it is guaranteed
+ that the semaphore will be available because it has just been created. */
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );
+
+ /* Start the two tasks as described at the top of this file. */
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* The CPU is currently running, not sleeping, so turn on the LED that
+ shows the CPU is not in a sleep mode. */
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );
+
+ /* Start the scheduler running running. */
+ vTaskStartScheduler();
+
+ /* If all is well the next line of code will not be reached as the
+ scheduler will be running. If the next line is reached then it is likely
+ there was insufficient FreeRTOS heap available for the idle task and/or
+ timer task to be created. See http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xDelay;
+const unsigned long ulValueToSend = mainQUEUED_VALUE;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* The delay period between successive sends to the queue is set by
+ the potentiometer reading. */
+ xDelay = ( portTickType ) prvReadPOT();
+
+ /* If the block time is greater than 3000 milliseconds then block
+ indefinitely waiting for a button push. */
+ if( xDelay > mainSOFTWARE_STANDBY_DELAY )
+ {
+ /* As this is an indefinite delay the kernel will place the CPU
+ into software standby mode the next time the idle task runs. */
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );
+ }
+ else
+ {
+ /* Convert a time in milliseconds to a time in ticks. */
+ xDelay /= portTICK_RATE_MS;
+
+ /* Place this task in the blocked state until it is time to run
+ again. As this is not an indefinite sleep the kernel will place
+ the CPU into the deep sleep state when the idle task next runs. */
+ vTaskDelay( xDelay );
+ }
+
+ /* Send to the queue - causing the queue receive task to flash its LED.
+ It should not be necessary to block on the queue send because the Rx
+ task will have removed the last queued item. */
+ xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have arrived, but is it the expected
+ value? If it is, toggle the LED. */
+ if( ulReceivedValue == mainQUEUED_VALUE )
+ {
+ vParTestToggleLED( mainQUEUE_LED );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPreSleepProcessing( unsigned long ulExpectedIdleTime )
+{
+ /* Called by the kernel before it places the MCU into a sleep mode because
+ configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing().
+
+ NOTE: Additional actions can be taken here to get the power consumption
+ even lower. For example, the ADC input used by this demo could be turned
+ off here, and then back on again in the post sleep processing function.
+ For maximum power saving ensure all unused pins are in their lowest power
+ state. */
+
+ /* Avoid compiler warnings about the unused parameter. */
+ ( void ) ulExpectedIdleTime;
+
+ /* Is the MCU about to enter deep sleep mode or software standby mode? */
+ if( SYSTEM.SBYCR.BIT.SSBY == 0 )
+ {
+ /* Turn on the LED that indicates deep sleep mode is being entered. */
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE );
+ }
+ else
+ {
+ /* Software standby mode is being used, so no LEDs are illuminated to
+ ensure minimum power readings are obtained. Ensure the Queue LED is
+ also off. */
+ vParTestSetLED( mainQUEUE_LED, pdFALSE );
+ }
+
+ /* Turn off the LED that indicates full power is being used. */
+ vParTestSetLED( mainFULL_POWER_LED, pdFALSE );
+}
+/*-----------------------------------------------------------*/
+
+void vPostSleepProcessing( unsigned long ulExpectedIdleTime )
+{
+ /* Called by the kernel when the MCU exits a sleep mode because
+ configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */
+
+ /* Avoid compiler warnings about the unused parameter. */
+ ( void ) ulExpectedIdleTime;
+
+ /* Turn off the LED that indicates deep sleep mode, and turn on the LED
+ that indicates full power is being used. */
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE );
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+static unsigned short prvReadPOT( void )
+{
+unsigned short usADCValue;
+const unsigned short usMinADCValue = 128;
+
+ /* Start an ADC scan. */
+ S12AD.ADCSR.BIT.ADST = 1;
+ while( S12AD.ADCSR.BIT.ADST == 1 )
+ {
+ /* Just waiting for the ADC scan to complete. Inefficient
+ polling! */
+ }
+
+ usADCValue = S12AD.ADDR4;
+
+ /* Don't let the ADC value get too small as the LED behaviour will look
+ erratic. */
+ if( usADCValue < usMinADCValue )
+ {
+ usADCValue = usMinADCValue;
+ }
+
+ return usADCValue;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = VECT_ICU_IRQ0, VECT_ICU_IRQ1, VECT_ICU_IRQ4
+__interrupt void vButtonInterrupt1( void )
+{
+long lHigherPriorityTaskWoken = pdFALSE;
+
+ /* The semaphore is only created when the build is configured to create the
+ low power demo. */
+ if( xSemaphore != NULL )
+ {
+ /* This interrupt will bring the CPU out of deep sleep and software
+ standby modes. Give the semaphore that was used to place the Tx task
+ into an indefinite sleep. */
+ if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )
+ {
+ xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );
+ }
+ else
+ {
+ /* The semaphore was already available, so the task is not blocked
+ on it and there is no point giving it. */
+ }
+
+ /* If giving the semaphore caused a task to leave the Blocked state,
+ and the task that left the Blocked state has a priority equal to or
+ above the priority of the task that this interrupt interrupted, then
+ lHigherPriorityTaskWoken will have been set to pdTRUE inside the call
+ to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause
+ a context switch to the unblocked task. */
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
+ }
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/reg_test.s b/FreeRTOS/Demo/RX100-RSK_IAR/reg_test.s
new file mode 100644
index 000000000..f467be45b
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/reg_test.s
@@ -0,0 +1,274 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+ PUBLIC _vRegTest1Implementation
+ PUBLIC _vRegTest2Implementation
+
+ EXTERN _ulRegTest1CycleCount
+ EXTERN _ulRegTest2CycleCount
+
+ RSEG CODE:CODE(4)
+
+_vRegTest1Implementation:
+
+ /* Set each register to a known value. */
+ MOV.L #0x33333333, R15
+ MVTACHI R15
+ MOV.L #0x44444444, R15
+ MVTACLO R15
+ MOV.L #1, R1
+ MOV.L #2, R2
+ MOV.L #3, R3
+ MOV.L #4, R4
+ MOV.L #5, R5
+ MOV.L #6, R6
+ MOV.L #7, R7
+ MOV.L #8, R8
+ MOV.L #9, R9
+ MOV.L #10, R10
+ MOV.L #11, R11
+ MOV.L #12, R12
+ MOV.L #13, R13
+ MOV.L #14, R14
+ MOV.L #15, R15
+
+ /* Loop, checking each iteration that each register still contains the
+ expected value. */
+ TestLoop1:
+
+ /* Push the registers that are going to get clobbered. */
+ PUSHM R14-R15
+
+ /* Increment the loop counter to show this task is still getting CPU
+ time. */
+ MOV.L #_ulRegTest1CycleCount, R14
+ MOV.L [ R14 ], R15
+ ADD #1, R15
+ MOV.L R15, [ R14 ]
+
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR
+ register. */
+ MOV.L #1, R14
+ MOV.L #0872E0H, R15
+ MOV.B R14, [R15]
+ NOP
+ NOP
+
+ /* Check the accumulator value. */
+ MVFACHI R15
+ CMP #0x33333333, R15
+ BNE RegTest2Error
+ MVFACMI R15
+ CMP #0x33334444, R15
+ BNE RegTest2Error
+
+ /* Restore the clobbered registers. */
+ POPM R14-R15
+
+ /* Now compare each register to ensure it still contains the value that
+ was set before this loop was entered. */
+ CMP #1, R1
+ BNE RegTest1Error
+ CMP #2, R2
+ BNE RegTest1Error
+ CMP #3, R3
+ BNE RegTest1Error
+ CMP #4, R4
+ BNE RegTest1Error
+ CMP #5, R5
+ BNE RegTest1Error
+ CMP #6, R6
+ BNE RegTest1Error
+ CMP #7, R7
+ BNE RegTest1Error
+ CMP #8, R8
+ BNE RegTest1Error
+ CMP #9, R9
+ BNE RegTest1Error
+ CMP #10, R10
+ BNE RegTest1Error
+ CMP #11, R11
+ BNE RegTest1Error
+ CMP #12, R12
+ BNE RegTest1Error
+ CMP #13, R13
+ BNE RegTest1Error
+ CMP #14, R14
+ BNE RegTest1Error
+ CMP #15, R15
+ BNE RegTest1Error
+
+ /* All comparisons passed, start a new iteration of this loop. */
+ BRA TestLoop1
+
+ /* A compare failed, just loop here so the loop counter stops
+ incrementing causing the check timer to indicate the error. */
+ RegTest1Error:
+ BRA RegTest1Error
+
+/*-----------------------------------------------------------*/
+
+_vRegTest2Implementation:
+
+ /* Set each register to a known value. */
+ MOV.L #0x11111111, R15
+ MVTACHI R15
+ MOV.L #0x22222222, R15
+ MVTACLO R15
+ MOV.L #100, R1
+ MOV.L #200, R2
+ MOV.L #300, R3
+ MOV.L #400, R4
+ MOV.L #500, R5
+ MOV.L #600, R6
+ MOV.L #700, R7
+ MOV.L #800, R8
+ MOV.L #900, R9
+ MOV.L #1000, R10
+ MOV.L #1001, R11
+ MOV.L #1002, R12
+ MOV.L #1003, R13
+ MOV.L #1004, R14
+ MOV.L #1005, R15
+
+ /* Loop, checking each iteration that each register still contains the
+ expected value. */
+ TestLoop2:
+
+ /* Push the registers that are going to get clobbered. */
+ PUSHM R14-R15
+
+ /* Increment the loop counter to show this task is still getting CPU
+ time. */
+ MOV.L #_ulRegTest2CycleCount, R14
+ MOV.L [ R14 ], R15
+ ADD #1, R15
+ MOV.L R15, [ R14 ]
+
+ /* Check the accumulator value. */
+ MVFACHI R15
+ CMP #0x11111111, R15
+ BNE RegTest2Error
+ MVFACMI R15
+ CMP #0x11112222, R15
+ BNE RegTest2Error
+
+ /* Restore the clobbered registers. */
+ POPM R14-R15
+
+ /* Now compare each register to ensure it still contains the value that
+ was set before this loop was entered. */
+ CMP #100, R1
+ BNE RegTest2Error
+ CMP #200, R2
+ BNE RegTest2Error
+ CMP #300, R3
+ BNE RegTest2Error
+ CMP #400, R4
+ BNE RegTest2Error
+ CMP #500, R5
+ BNE RegTest2Error
+ CMP #600, R6
+ BNE RegTest2Error
+ CMP #700, R7
+ BNE RegTest2Error
+ CMP #800, R8
+ BNE RegTest2Error
+ CMP #900, R9
+ BNE RegTest2Error
+ CMP #1000, R10
+ BNE RegTest2Error
+ CMP #1001, R11
+ BNE RegTest2Error
+ CMP #1002, R12
+ BNE RegTest2Error
+ CMP #1003, R13
+ BNE RegTest2Error
+ CMP #1004, R14
+ BNE RegTest2Error
+ CMP #1005, R15
+ BNE RegTest2Error
+
+ /* All comparisons passed, start a new iteration of this loop. */
+ BRA TestLoop2
+
+ /* A compare failed, just loop here so the loop counter stops
+ incrementing causing the check timer to indicate the error. */
+ RegTest2Error:
+ BRA RegTest2Error
+
+/*-----------------------------------------------------------*/
+
+ END
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.cspy.bat b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.cspy.bat
new file mode 100644
index 000000000..5197919fe
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.cspy.bat
@@ -0,0 +1,24 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM --download_only Downloads a code image without starting a debug
+@REM session afterwards.
+@REM --silent Omits the sign-on message.
+@REM --timeout Limits the maximum allowed execution time.
+@REM
+
+
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\bin\rxproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\bin\rxemue20.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\bin\rxbat.dll" --backend -B "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\rx\config\debugger\ior5f51115.ddf" "--endian" "l" "--double" "32" "--core" "RX100" "--int" "32" "-d" "emue20" "--drv_mode" "debugging" "--drv_communication" "USB"
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.dbgdt b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.dbgdt
new file mode 100644
index 000000000..4ae27b523
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.dbgdt
@@ -0,0 +1,92 @@
+
+
+
+
+
+
+
+
+ 201622
+
+ 20
+ 1216
+ 324
+ 81
+
+
+
+
+
+
+
+ 231272727
+
+
+
+
+
+ - Disassembly
- _I0
+
+
+
+ - 599
- 20
+
+
+
+
+
+
+ 200
+
+
+ 11
+ 200200- lErrorStatus
- lChangedTimerPeriodAlready
- Expression
- Location
- Type
- Value
- 200
- 150
- 100
- 62
+
+
+
+
+
+
+ TabID-27185-11031
+ Debug Log
+ Debug-Log
+
+
+
+ TabID-26662-11041
+ Build
+ Build
+
+
+
+
+ 0
+
+
+ TabID-5165-11034
+ Workspace
+ Workspace
+
+
+ RTOSDemo_IARRTOSDemo_IAR/FreeRTOS SourceRTOSDemo_IAR/FreeRTOS Source/portableRTOSDemo_IAR/FreeRTOS Source/portable/IARRTOSDemo_IAR/FreeRTOS Source/portable/IAR/RX100
+
+
+
+ 0
+
+
+
+
+
+ TextEditor$WS_DIR$\main.c00000104601460140TextEditor$WS_DIR$\FreeRTOSConfig.h0000072523752370100000010000001
+
+
+
+
+
+
+ iaridepm.enu1debuggergui.enu1-2-2716305-2-2200200119048203666182738731161-2-21981682-2-216842001002381203666119048203666
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.dni b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.dni
new file mode 100644
index 000000000..2d503d3b9
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.dni
@@ -0,0 +1,104 @@
+[Stack]
+FillEnabled=0
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnLogOnly=1
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[DebugChecksum]
+Checksum=222757635
+[CallStack]
+ShowArgs=0
+[Disassembly]
+MixedMode=1
+[InterruptLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+SumSortOrder=0
+[DataLog]
+LogEnabled=0
+SumEnabled=0
+GraphEnabled=0
+ShowTimeLog=1
+ShowTimeSum=1
+[Breakpoints2]
+Count=0
+[Interrupts]
+Enabled=1
+[MemoryMap]
+Enabled=0
+Base=0
+UseAuto=0
+TypeViolation=1
+UnspecRange=1
+ActionState=1
+[E1/E20 Emulator]
+BlockBits=15
+B0=1,0
+B1=1,1024
+B2=1,2048
+B3=1,3072
+StartEnabled=0
+StartSymbol=
+StopEnabled=0
+StopSymbol=
+TraceMode=0
+TraceOutput=2
+TraceCapacity=0
+TraceRestart=0
+OperatingFrequency=22.000000
+PerfEnabled=0
+PerfCondition=0,0
+PerfDisplayTime=0,0
+PerfOnlyOnce=0,0
+PerfUse64Bit=0
+ChipName=R5F51115
+PinMode=0
+RegMode=0
+Endian=0
+ExtMemBlockNum=0
+InputClock=22.000000
+AllowClkSrcChange=0
+WorkRamStart=4096
+ComunicationSelect=1
+JtagClock=0
+FINE=2000000
+FlashOvrNum=0
+DebugFlags=0,0
+EmulatorMode=0
+PowerTargetFromEmulator=0
+Voltage=0
+NeedInit=0
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[CallStackLog]
+Enabled=0
+[DriverProfiling]
+Enabled=0
+Mode=1
+Graph=0
+Symbiont=0
+Exclusions=
+[Breakpoints]
+Bp0=_ "STD_CODE" "{$PROJ_DIR$\Renesas_Files\r_bsp\board\user\hardware_setup.c}.60.2" 0 0 0 0 "" 0 ""
+Count=1
+[Monitor Execution]
+Leave target running=0
+Release target=0
+[Aliases]
+Count=0
+SuppressDialog=0
+[Trace1]
+Enabled=0
+ShowSource=1
diff --git a/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.wsdt b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.wsdt
new file mode 100644
index 000000000..d06af2ea2
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_IAR/settings/RTOSDemo_IAR.wsdt
@@ -0,0 +1,49 @@
+
+
+
+
+
+ RTOSDemo_IAR/Debug
+
+
+
+
+
+
+
+
+ 199272727
+
+ 201216324815808299469582994
+
+
+
+
+
+ TabID-3933-19799
+ Workspace
+ Workspace
+
+
+ RTOSDemo_IARRTOSDemo_IAR/Renesas Files
+
+
+
+ 0TabID-4909-11467BuildBuildTabID-18506-4030Ambiguous DefinitionsSelect-Ambiguous-DefinitionsTabID-16773-20028Find in FilesFind-in-Files0
+
+
+
+
+
+ TextEditor$WS_DIR$\main.c00000746014601400100000010000001
+
+
+
+
+
+
+ iaridepm.enu1-2-2648273-2-2200200119048203666163690661914-2-22901682-2-216842921002381297352119048203666
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.HardwareDebuglinker b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.HardwareDebuglinker
new file mode 100644
index 000000000..2a9748a21
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.HardwareDebuglinker
@@ -0,0 +1,34 @@
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
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+
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+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.Releaselinker b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.Releaselinker
new file mode 100644
index 000000000..2a9748a21
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.Releaselinker
@@ -0,0 +1,34 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.cproject b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.cproject
new file mode 100644
index 000000000..afcd0cbf6
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.cproject
@@ -0,0 +1,236 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.info b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.info
new file mode 100644
index 000000000..0b75c11fa
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.info
@@ -0,0 +1,5 @@
+TOOL_CHAIN=Renesas RXC Toolchain
+VERSION=v1.02.01
+TC_INSTALL=C:\Devtools\Renesas\Hew\Tools\Renesas\RX\1_2_1\
+VERSION_IDE=3.06.02.080
+E2STUDIO_VERSION=1.1.1.7
\ No newline at end of file
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.project b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.project
new file mode 100644
index 000000000..33fd54604
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.project
@@ -0,0 +1,83 @@
+
+
+ RTOSDemo_Renesas
+
+
+
+
+
+ com.renesas.cdt.core.genmakebuilder
+
+
+ ?name?
+
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.autoBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.buildArguments
+
+
+
+ org.eclipse.cdt.make.core.buildCommand
+ make
+
+
+ org.eclipse.cdt.make.core.buildLocation
+ ${workspace_loc:/BSP111/HardwareDebug}
+
+
+ org.eclipse.cdt.make.core.cleanBuildTarget
+ clean
+
+
+ org.eclipse.cdt.make.core.contents
+ org.eclipse.cdt.make.core.configurationIds
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ false
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.fullBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ true
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ com.renesas.cdt.core.kpitcnature
+ com.renesas.cdt.core.kpitccnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs
new file mode 100644
index 000000000..73b6fd783
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs
@@ -0,0 +1,69 @@
+#Tue Nov 06 09:14:28 EST 2012
+com.renesas.cdt.renesas.Assembler.option.userDefine=-nologo;;;
+com.renesas.cdt.renesas.Compiler.option.C=com.renesas.cdt.renesas.Compiler.option.C99
+com.renesas.cdt.renesas.Compiler.option.UserDef=-nologo;-change_message\=warning;
+com.renesas.cdt.renesas.Compiler.option.incFileDirectories="C\:\\PROGRA~1\\Renesas\\Hew\\Tools\\Renesas\\RX\\1_2_0\\include";
+com.renesas.cdt.renesas.Linker.option.userDefined=-rom\=D\=R,D_1\=R_1,D_2\=R_2;-nomessage;-nologo;
+com.renesas.cdt.renesas.StandardLibrary.option.complexC99=false
+com.renesas.cdt.renesas.StandardLibrary.option.ctypec89=false
+com.renesas.cdt.renesas.StandardLibrary.option.fenvC99=false
+com.renesas.cdt.renesas.StandardLibrary.option.inttypesC99=false
+com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration=C99
+com.renesas.cdt.renesas.StandardLibrary.option.mathc89=false
+com.renesas.cdt.renesas.StandardLibrary.option.mathfc89=false
+com.renesas.cdt.renesas.StandardLibrary.option.runtime=true
+com.renesas.cdt.renesas.StandardLibrary.option.rxccomplexCPP=false
+com.renesas.cdt.renesas.StandardLibrary.option.rxciosCPP=false
+com.renesas.cdt.renesas.StandardLibrary.option.rxcnewCPP=true
+com.renesas.cdt.renesas.StandardLibrary.option.rxcstringCPP=false
+com.renesas.cdt.renesas.StandardLibrary.option.stdargc89=false
+com.renesas.cdt.renesas.StandardLibrary.option.stdioc89=true
+com.renesas.cdt.renesas.StandardLibrary.option.stdlibc89=true
+com.renesas.cdt.renesas.StandardLibrary.option.stringc89=true
+com.renesas.cdt.renesas.StandardLibrary.option.wcharC99=false
+com.renesas.cdt.renesas.StandardLibrary.option.wctypeC99=false
+com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian=Little-endian data
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM=None
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM=None
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.address=00000000
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister=None
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit=Lower bit
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType=RX100
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.denormalized=false
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian=Little-endian data
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.enumSize=false
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.packStructures=false
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode=None
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble=Single precision
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt=None
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.replaceFromIntWithShort=false
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo=Nearest
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField=unsigned
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar=unsigned
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useDynamic=false
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useTry=false
+com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence=24 bit
+com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian=Little-endian data
+com.renesas.cdt.rxc.Release.Assembler.option.endian=Little-endian data
+com.renesas.cdt.rxc.Release.Compiler.option.RAM=None
+com.renesas.cdt.rxc.Release.Compiler.option.ROM=None
+com.renesas.cdt.rxc.Release.Compiler.option.address=00000000
+com.renesas.cdt.rxc.Release.Compiler.option.addressRegister=None
+com.renesas.cdt.rxc.Release.Compiler.option.allocLowerBit=Lower bit
+com.renesas.cdt.rxc.Release.Compiler.option.cpuType=RX100
+com.renesas.cdt.rxc.Release.Compiler.option.denormalized=false
+com.renesas.cdt.rxc.Release.Compiler.option.endian=Little-endian data
+com.renesas.cdt.rxc.Release.Compiler.option.enumSize=false
+com.renesas.cdt.rxc.Release.Compiler.option.packStructures=false
+com.renesas.cdt.rxc.Release.Compiler.option.patchCode=None
+com.renesas.cdt.rxc.Release.Compiler.option.precisionDouble=Single precision
+com.renesas.cdt.rxc.Release.Compiler.option.registerFastInterrupt=None
+com.renesas.cdt.rxc.Release.Compiler.option.replaceFromIntWithShort=false
+com.renesas.cdt.rxc.Release.Compiler.option.roundTo=Nearest
+com.renesas.cdt.rxc.Release.Compiler.option.signBitField=unsigned
+com.renesas.cdt.rxc.Release.Compiler.option.signChar=unsigned
+com.renesas.cdt.rxc.Release.Compiler.option.useDynamic=false
+com.renesas.cdt.rxc.Release.Compiler.option.useTry=false
+com.renesas.cdt.rxc.Release.Compiler.option.widthDivergence=24 bit
+com.renesas.cdt.rxc.Release.StandardLibrary.option.endian=Little-endian data
+eclipse.preferences.version=1
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 000000000..d3ebcda34
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Fri Nov 09 15:36:42 EST 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/append=true
+environment/buildEnvironmentInclude/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/appendContributed=true
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/append=true
+environment/buildEnvironmentLibrary/com.renesas.cdt.rxc.hardwaredebug.win32.configuration.Id.287456189/appendContributed=true
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/BSP111.launch b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/BSP111.launch
new file mode 100644
index 000000000..03ec6f933
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/BSP111.launch
@@ -0,0 +1,77 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/CreateProjectDirectoryStructure.bat b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/CreateProjectDirectoryStructure.bat
new file mode 100644
index 000000000..b2261eafb
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/CreateProjectDirectoryStructure.bat
@@ -0,0 +1,52 @@
+REM This file should be executed from the command line prior to the first
+REM build. It will be necessary to refresh the Eclipse project once the
+REM .bat file has been executed (normally just press F5 to refresh).
+
+REM Copies all the required files from their location within the standard
+REM FreeRTOS directory structure to under the Eclipse project directory.
+REM This permits the Eclipse project to be used in 'managed' mode and without
+REM having to setup any linked resources.
+
+REM Standard paths
+SET FREERTOS_SOURCE=..\..\Source
+SET COMMON_SOURCE=..\Common\minimal
+SET COMMON_INCLUDE=..\Common\include
+
+REM Have the files already been copied?
+IF EXIST RTOSDemo\FreeRTOS_Source Goto END
+
+ REM Create the required directory structure.
+ MD RTOSDemo\FreeRTOS_Source
+ MD RTOSDemo\FreeRTOS_Source\include
+ MD RTOSDemo\FreeRTOS_Source\portable
+ MD RTOSDemo\FreeRTOS_Source\portable\MemMang
+ MD RTOSDemo\FreeRTOS_Source\portable\Renesas
+ MD RTOSDemo\FreeRTOS_Source\portable\Renesas\RX100
+ MD RTOSDemo\Common_Demo_Tasks
+ MD RTOSDemo\Common_Demo_Tasks\include
+
+ REM Copy the core kernel files into the project directory
+ copy %FREERTOS_SOURCE%\tasks.c RTOSDemo\FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\queue.c RTOSDemo\FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\list.c RTOSDemo\FreeRTOS_Source
+ copy %FREERTOS_SOURCE%\timers.c RTOSDemo\FreeRTOS_Source
+
+ REM Copy the common header files into the project directory
+ copy %FREERTOS_SOURCE%\include\*.* RTOSDemo\FreeRTOS_Source\include
+
+ REM Copy the portable layer files into the project directory
+ copy %FREERTOS_SOURCE%\portable\Renesas\RX100\*.* RTOSDemo\FreeRTOS_Source\portable\Renesas\RX100
+
+ REM Copy the memory allocation files into the project directory
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c RTOSDemo\FreeRTOS_Source\portable\MemMang
+
+ REM Copy the files that define the common demo tasks.
+ copy %COMMON_SOURCE%\death.c RTOSDemo\Common_Demo_Tasks
+ copy %COMMON_SOURCE%\blocktim.c RTOSDemo\Common_Demo_Tasks
+ copy %COMMON_SOURCE%\GenQTest.c RTOSDemo\Common_Demo_Tasks
+ copy %COMMON_SOURCE%\recmutex.c RTOSDemo\Common_Demo_Tasks
+
+ REM Copy the common demo file headers.
+ copy %COMMON_INCLUDE%\*.h RTOSDemo\Common_Demo_Tasks\include
+
+: END
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h
new file mode 100644
index 000000000..c29caee9c
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/FreeRTOSConfig.h
@@ -0,0 +1,188 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+
+/*
+ * The following #error directive is to remind users that a batch file must be
+ * executed prior to this project being built. The batch file *cannot* be
+ * executed from within the IDE! Once it has been executed, re-open or refresh
+ * the Eclipse project and remove the #error line below.
+ */
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/* Hardware specifics. */
+#include "platform.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* DEMO SPECIFIC SETTING:
+ * Set configCREATE_LOW_POWER_DEMO to one to run the low power demo with tick
+ * suppression, or 0 to run the more comprehensive test and demo application.
+ * If configCREATE_LOW_POWER_DEMO is set to 1 then main() calls main_low_power().
+ * If configCREATE_LOW_POWER_DEMO is set to 0 then main() calls main_full().
+ */
+#define configCREATE_LOW_POWER_DEMO 1
+
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE configCREATE_LOW_POWER_DEMO
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( ICLK_HZ ) /* Set in mcu_info.h. */
+#define configPERIPHERAL_CLOCK_HZ ( PCLKB_HZ ) /* Set in muc_info.h. */
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 9 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_APPLICATION_TASK_TAG 0
+
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions - only included when the demo is configured to
+build the full demo (as opposed to the low power demo). */
+#if configCREATE_LOW_POWER_DEMO == 1
+ #define configUSE_TIMERS 0
+#else
+ #define configUSE_TIMERS 1
+ #define configTIMER_TASK_PRIORITY ( 3 )
+ #define configTIMER_QUEUE_LENGTH 5
+ #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
+#endif /* configCREATE_LOW_POWER_DEMO */
+
+/* The interrupt priority used by the kernel itself for the tick interrupt and
+the pended interrupt. This would normally be the lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY 1
+
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.
+Interrupts that use a priority above this will not be effected by anything the
+kernel is doing. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_xTaskGetSchedulerState 1
+
+extern void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled();
+
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros
+allow the application writer to add additional code before and after the MCU is
+placed into the low power state respectively. The implementations provided in
+this demo can be extended to save even more power - for example the analog
+input used by the low power demo could be switched off in the pre-sleep macro
+and back on again in the post sleep macro. */
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );
+
+/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral
+that generates the tick interrupt. */
+#define configTICK_VECTOR VECT_CMT0_CMI0
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c
new file mode 100644
index 000000000..827da190d
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/ParTest.c
@@ -0,0 +1,200 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/*-----------------------------------------------------------
+ * Simple IO routines to control the LEDs.
+ *-----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo includes. */
+#include "partest.h"
+
+#define partestNUM_LEDS ( 4 )
+
+long lParTestGetLEDState( unsigned long ulLED );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+ /* Port pin configuration is done by the low level set up prior to this
+ function being called. */
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned long ulLED, signed long xValue )
+{
+ if( ulLED < partestNUM_LEDS )
+ {
+ if( xValue != 0 )
+ {
+ /* Turn the LED on. */
+ taskENTER_CRITICAL();
+ {
+ switch( ulLED )
+ {
+ case 0: LED0 = LED_ON;
+ break;
+ case 1: LED1 = LED_ON;
+ break;
+ case 2: LED2 = LED_ON;
+ break;
+ case 3: LED3 = LED_ON;
+ break;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ /* Turn the LED off. */
+ taskENTER_CRITICAL();
+ {
+ switch( ulLED )
+ {
+ case 0: LED0 = LED_OFF;
+ break;
+ case 1: LED1 = LED_OFF;
+ break;
+ case 2: LED2 = LED_OFF;
+ break;
+ case 3: LED3 = LED_OFF;
+ break;
+ }
+
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned long ulLED )
+{
+ if( ulLED < partestNUM_LEDS )
+ {
+ taskENTER_CRITICAL();
+ {
+ if( lParTestGetLEDState( ulLED ) != 0x00 )
+ {
+ vParTestSetLED( ulLED, 0 );
+ }
+ else
+ {
+ vParTestSetLED( ulLED, 1 );
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+/*-----------------------------------------------------------*/
+
+long lParTestGetLEDState( unsigned long ulLED )
+{
+long lReturn = pdTRUE;
+
+ if( ulLED < partestNUM_LEDS )
+ {
+ switch( ulLED )
+ {
+ case 0 : if( LED0 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 1 : if( LED1 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 2 : if( LED2 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ case 3 : if( LED3 != 0 )
+ {
+ lReturn = pdFALSE;
+ }
+ break;
+ }
+ }
+
+ return lReturn;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/dbsct.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/dbsct.c
new file mode 100644
index 000000000..b92493a47
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/dbsct.c
@@ -0,0 +1,83 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : dbsct.c
+* Device(s) : RX
+* Description : Defines the structure of the ROM and RAM areas.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 26.10.2011 1.00 First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Defines type structures used in this file */
+#include
+
+/* Preprocessor directive */
+#pragma unpack
+
+/* Section start */
+#pragma section C C$DSEC
+
+/* MCU ROM and RAM structure definition */
+extern const struct {
+ uint8_t *rom_s; /* Start address of the initialized data section in ROM */
+ uint8_t *rom_e; /* End address of the initialized data section in ROM */
+ uint8_t *ram_s; /* Start address of the initialized data section in RAM */
+} _DTBL[] = {
+ { __sectop("D"), __secend("D"), __sectop("R") },
+ { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },
+ { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }
+};
+
+/* Section start */
+#pragma section C C$BSEC
+
+/* MCU ROM and RAM structure definition */
+extern const struct {
+ uint8_t *b_s; /* Start address of non-initialized data section */
+ uint8_t *b_e; /* End address of non-initialized data section */
+} _BTBL[] = {
+ { __sectop("B"), __secend("B") },
+ { __sectop("B_2"), __secend("B_2") },
+ { __sectop("B_1"), __secend("B_1") }
+};
+
+/* Section start */
+#pragma section
+
+/* CTBL prevents excessive output of L1100 messages when linking.
+ Even if CTBL is deleted, the operation of the program does not change. */
+uint8_t * const _CTBL[] = {
+ __sectop("C_1"), __sectop("C_2"), __sectop("C"),
+ __sectop("W_1"), __sectop("W_2"), __sectop("W")
+};
+
+/* Preprocessor directive */
+#pragma packoption
+
+/* This is to ensure compatibility with new L section in version 1.1 and up of the RXC compiler. Do not remove! */
+#pragma section C L
+const unsigned long deadSpace = 0xDEADDEAD;
+#pragma section
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/hwsetup.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/hwsetup.c
new file mode 100644
index 000000000..3ba6ce53c
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/hwsetup.c
@@ -0,0 +1,149 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : hwsetup.c
+* Device(s) : RX
+* H/W Platform : RSKRX210
+* Description : Defines the initialization routines used each time the MCU is restarted.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* I/O Register and board definitions */
+#include "platform.h"
+/* Contains delcarations for the functions defined in this file */
+#include "hwsetup.h"
+#include "r_switches_config.h"
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* MCU I/O port configuration function delcaration */
+static void output_ports_configure(void);
+
+/* Interrupt configuration function delcaration */
+static void interrupts_configure(void);
+
+/* MCU peripheral module configuration function declaration */
+static void peripheral_modules_enable(void);
+
+
+/***********************************************************************************************************************
+* Function name: hardware_setup
+* Description : Contains setup functions called at device restart
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void hardware_setup(void)
+{
+ output_ports_configure();
+ interrupts_configure();
+ peripheral_modules_enable();
+}
+
+/***********************************************************************************************************************
+* Function name: output_ports_configure
+* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void output_ports_configure(void)
+{
+ /* Enable LEDs. */
+ /* Start with LEDs off. */
+ LED0 = LED_OFF;
+ LED1 = LED_OFF;
+ LED2 = LED_OFF;
+ LED3 = LED_OFF;
+
+ /* Set LED pins as outputs. */
+ LED0_PDR = 1;
+ LED1_PDR = 1;
+ LED2_PDR = 1;
+ LED3_PDR = 1;
+
+ /* Enable switches. */
+ /* Set pins as inputs. */
+ SW1_PDR = 0;
+ SW2_PDR = 0;
+ SW3_PDR = 0;
+
+ /* Set port mode registers for switches. */
+ SW1_PMR = 0;
+ SW2_PMR = 0;
+ SW3_PMR = 0;
+
+ /* Unlock MPC registers to enable writing to them. */
+ MPC.PWPR.BIT.B0WI = 0 ; /* Unlock protection register */
+ MPC.PWPR.BIT.PFSWE = 1 ; /* Unlock MPC registers */
+
+ /* TXD1 is output. */
+ PORT1.PDR.BIT.B6 = 1;
+ PORT1.PMR.BIT.B6 = 1;
+ MPC.P16PFS.BYTE = 0x0A;
+ /* RXD1 is input. */
+ PORT1.PDR.BIT.B5 = 0;
+ PORT1.PMR.BIT.B5 = 1;
+ MPC.P15PFS.BYTE = 0x0A;
+
+ /* Configure the pin connected to the ADC Pot as an input */
+ PORT4.PDR.BIT.B4 = 0;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Turn off module stop for the A2D converter. */
+ SYSTEM.MSTPCRA.BIT.MSTPA17 = 0;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+
+ /* Initialise the first button to generate an interrupt. */
+ R_SWITCHES_Init();
+}
+
+/***********************************************************************************************************************
+* Function name: interrupts_configure
+* Description : Configures interrupts used
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void interrupts_configure(void)
+{
+ /* Add code here to setup additional interrupts */
+}
+
+/***********************************************************************************************************************
+* Function name: peripheral_modules_enable
+* Description : Enables and configures peripheral devices on the MCU
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void peripheral_modules_enable(void)
+{
+ /* Enable triggers to start an ADC conversion. */
+ S12AD.ADCSR.BIT.TRGE = 1;
+
+ /* Only channel 4 is going to be used. */
+ S12AD.ADANSA.BIT.ANSA4 = 1;
+}
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/hwsetup.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/hwsetup.h
new file mode 100644
index 000000000..35e068633
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/hwsetup.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : hwsetup.h
+* Description : Hardware setup header file.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 26.10.2011 1.00 First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Multiple inclusion prevention macro */
+#ifndef HWSETUP_H
+#define HWSETUP_H
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+/* Hardware setup funtion declaration */
+void hardware_setup(void);
+
+/* End of multiple inclusion prevention macro */
+#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.c
new file mode 100644
index 000000000..a01280257
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.c
@@ -0,0 +1,254 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lcd.c
+* Device(s) : RX
+* H/W Platform : RSKRX111
+* Description : Provides variable and function declarations for lcd.c file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Processor-specific details */
+#include
+/* Standard string manipulation & formatting functions */
+#include
+#include
+/* Defines standard variable types used in this function */
+#include
+/* Bring in board includes. */
+#include "platform.h"
+/* Following header file provides function prototypes for LCD controlling functions & macro defines */
+#include "lcd.h"
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+static void lcd_delay(volatile int32_t nsecs);
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value);
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value);
+
+/***********************************************************************************************************************
+* Function name : lcd_initialize
+* Description : Initializes the LCD display.
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_initialize(void)
+{
+ /* Set LCD data pins as outputs. */
+ PORT4.PDR.BYTE |= 0x0F;
+
+ /* Set LCD control pins as outputs. */
+ RS_PIN_DDR = 1;
+ E_PIN_DDR = 1;
+
+ /* Power Up Delay for the LCD Module */
+ lcd_delay(50000000);
+
+ /* Display initialises in 8 bit mode - so send one write (seen as 8 bit) to set to 4 bit mode. */
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+ lcd_nibble_write(CTRL_WR, 0x03);
+ lcd_delay(5000000);
+
+ /* Function Set */
+ lcd_nibble_write(CTRL_WR, 0x02);
+ lcd_delay(39000);
+ lcd_nibble_write(CTRL_WR, 0x02);
+ lcd_nibble_write(CTRL_WR, (LCD_DISPLAY_ON | LCD_TWO_LINE ));
+ lcd_delay(39000);
+
+ /* Display ON/OFF control */
+ lcd_write(CTRL_WR, LCD_CURSOR_OFF);
+ lcd_delay(39000);
+
+ /* Display Clear */
+ lcd_write(CTRL_WR, LCD_CLEAR);
+ lcd_delay(2000000);
+
+ /* Entry Mode Set */
+ lcd_write(CTRL_WR, 0x06);
+ lcd_delay(39000);
+
+ /* Home the cursor */
+ lcd_write(CTRL_WR, LCD_HOME_L1);
+ lcd_delay(5000000);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_clear
+* Description : Clears the LCD
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_clear(void)
+{
+ /* Display Clear */
+ lcd_write(CTRL_WR, LCD_CLEAR);
+ lcd_delay(2000000);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_display
+* Description : This function controls LCD writes to line 1 or 2 of the LCD.
+* You need to use the defines LCD_LINE1 and LCD_LINE2 in order to specify the starting position.
+* For example, to start at the 2nd position on line 1...
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : position -
+* Line number of display
+* string -
+* Pointer to null terminated string
+* Return Value : none
+***********************************************************************************************************************/
+void lcd_display(uint8_t position, uint8_t const * string)
+{
+ /* Declare next position variable */
+ static uint8_t next_pos = 0xFF;
+
+ /* Set line position if needed. We don't want to if we don't need to because LCD control operations take longer
+ than LCD data operations. */
+ if (next_pos != position)
+ {
+ if(position < LCD_LINE2)
+ {
+ /* Display on Line 1 */
+ lcd_write(CTRL_WR, ((uint8_t)(LCD_HOME_L1 + position)));
+ }
+ else
+ {
+ /* Display on Line 2 */
+ lcd_write(CTRL_WR, ((uint8_t)((LCD_HOME_L2 + position) - LCD_LINE2)));
+ }
+
+ lcd_delay(39000);
+
+ /* set position index to known value */
+ next_pos = position;
+ }
+
+ do
+ {
+ /* Write character to LCD. */
+ lcd_write(DATA_WR,*string++);
+
+ lcd_delay(43000);
+
+ /* Increment position index */
+ next_pos++;
+ }
+ while(*string);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_delay
+* Description : Implements LCD required delays.
+* Arguments : nsecs -
+* Number of nanoseconds to delay. RX111 has max clock of 32MHz which gives a cycle time of 31.3ns.
+* This means that nothing under 313ns should be input. 313ns would be 10 cycles which is still
+* being optimistic for getting in and out of this function.
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_delay(volatile int32_t nsecs)
+{
+ while (0 < nsecs)
+ {
+ /* Subtract off 10 cycles per iteration. This number was obtained when using the Renesas toolchain at
+ optimization level 2. The number to nanoseconds to subtract off below is calculated off of the ICLK speed. */
+ nsecs -= (int32_t)((313.0)*(32000000.0/(float)ICLK_HZ));
+ }
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_nibble_write
+* Description : Writes data to display. Sends command to display.
+* Arguments : value -
+* The value to write
+* data_or_ctrl -
+* Whether to write data or control.
+* 1 = DATA
+* 0 = CONTROL
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_nibble_write(uint8_t data_or_ctrl, uint8_t value)
+{
+ /* Set Register Select pin high for Data */
+ if (data_or_ctrl == DATA_WR)
+ {
+ /* Data write. */
+ RS_PIN = 1;
+ }
+ else
+ {
+ /* Control write. */
+ RS_PIN = 0;
+ }
+
+ /* tsu1 delay */
+ lcd_delay(60);
+
+ /* EN enable chip (HIGH) */
+ E_PIN = 1;
+
+ /* Output the data */
+ PORT4.PODR.BYTE = (value & 0x0F);
+
+ /* tw delay */
+ lcd_delay(450);
+
+ /* Latch data by dropping E */
+ E_PIN = 0;
+
+ /* th2 delay */
+ lcd_delay(10);
+
+ /* tc delay */
+ lcd_delay(480);
+}
+
+/***********************************************************************************************************************
+* Function name : lcd_write
+* Description : This function controls LCD writes to line 1 or 2 of the LCD. You need to use the defines LCD_LINE1 and
+* LCD_LINE2 in order to specify the starting position.
+* For example, to start at the 2nd position on line 1...
+* lcd_display(LCD_LINE1 + 1, "Hello")
+* Arguments : value -
+* The value to write
+* data_or_ctrl -
+* Whether to write data or control.
+* 1 = DATA
+* 0 = CONTROL
+* Return Value : none
+***********************************************************************************************************************/
+static void lcd_write(uint8_t data_or_ctrl, uint8_t value)
+{
+ /* Write upper nibble first */
+ lcd_nibble_write(data_or_ctrl, (uint8_t)((value & 0xF0) >> 4));
+
+ /* Write lower nibble second */
+ lcd_nibble_write(data_or_ctrl, (uint8_t)(value & 0x0F));
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.h
new file mode 100644
index 000000000..0c7ee085f
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lcd.h
@@ -0,0 +1,101 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lcd.h
+* Device(s) : RX
+* H/W Platform : RSKRX111
+* Description : Provides variable and function declarations for lcd.c file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/* Multiple inclusion prevention macro */
+#ifndef LCD_H
+#define LCD_H
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Defines standard integer variable types used in this file */
+#include
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* RS register select pin */
+#define RS_PIN PORTC.PODR.BIT.B5
+#define RS_PIN_DDR PORTC.PDR.BIT.B5
+/* Display enable pin */
+#define E_PIN PORTB.PODR.BIT.B1
+#define E_PIN_DDR PORTB.PDR.BIT.B1
+/* Data write/read definition */
+#define DATA_WR 1
+/* Control write/read definition */
+#define CTRL_WR 0
+/* Maximum characters per line of LCD display. */
+#define NUMB_CHARS_PER_LINE 8
+/* Number of lines on the LCD display */
+#define MAXIMUM_LINES 2
+/* Character position of LCD line 1 */
+#define LCD_LINE1 0
+/* Character position of LCD line 2 */
+#define LCD_LINE2 16
+/* Clear LCD display and home cursor */
+#define LCD_CLEAR 0x01
+/* Move cursor to line 1 */
+#define LCD_HOME_L1 0x80
+/* Move cursor to line 2 */
+#define LCD_HOME_L2 0xC0
+/* Cursor auto decrement after R/W */
+#define CURSOR_MODE_DEC 0x04
+/* Cursor auto increment after R/W */
+#define CURSOR_MODE_INC 0x06
+/* Setup, 4 bits,2 lines, 5X7 */
+#define FUNCTION_SET 0x28
+/* Display ON with Cursor */
+#define LCD_CURSOR_ON 0x0E
+/* Display ON with Cursor off */
+#define LCD_CURSOR_OFF 0x0C
+/* Display on with blinking cursor */
+#define LCD_CURSOR_BLINK 0x0D
+/* Move Cursor Left One Position */
+#define LCD_CURSOR_LEFT 0x10
+/* Move Cursor Right One Position */
+#define LCD_CURSOR_RIGHT 0x14
+/* Enable LCD display */
+#define LCD_DISPLAY_ON 0x04
+/* Enable both LCD lines */
+#define LCD_TWO_LINE 0x08
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+/* LCD initialisation function declaration */
+void lcd_initialize (void);
+
+/* Update display function declaration */
+void lcd_display(uint8_t position, uint8_t const * string);
+
+/* Clear LCD function delcaration */
+void lcd_clear (void);
+
+/* End of multiple inclusion prevention macro */
+#endif
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/locking.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/locking.c
new file mode 100644
index 000000000..0e9e0fff4
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/locking.c
@@ -0,0 +1,118 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : locking.c
+* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so
+* common resources can be accessed safely.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.03.2012 1.00 First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed-size integer typedefs. */
+#include
+/* bool support. */
+#include
+/* Has intrinsic support. Includes xchg() which is used in this code. */
+#include
+/* Includes board and MCU related header files. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global variables (to be accessed by other files)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_Lock
+* Description : Attempt to acquire the lock that has been sent in.
+* Arguments : plock -
+* Pointer to lock structure with lock to try and acquire.
+* Return Value : true -
+* Lock was acquired.
+* false -
+* Lock was not acquired.
+***********************************************************************************************************************/
+bool R_BSP_Lock(bsp_lock_t * plock)
+{
+ bool ret = false;
+
+ /* Variable used in trying to acquire lock. Using the xchg instruction makes this atomic */
+ int32_t is_locked = true;
+
+ /* This example uses the RX MCU's atomic xchg() instruction. plock->lock is the lock we are trying to reserve.
+ The way this works is that 'is_locked' gets the value of the plock->lock and plock->lock gets the value of
+ 'is_locked' which we just set to 'true'. Basically this is an atomic 'swap' command. If the lock had not yet been
+ reserved then its value would be 'false' and after the xchg() instruction finished 'is_locked' would have
+ 'false'. If it had already been reserved then 'is_locked' would have 'true' after the xchg() instruction. Since
+ plock->lock was already 'true' and we just set it back to 'true' everything is ok. To see if we reserved the lock
+ we just need to check the value of 'is_locked' after this instruction finishes. */
+
+ /* Try to acquire semaphore to obtain lock */
+ xchg(&is_locked, &plock->lock);
+
+ /* Check to see if semaphore was successfully taken */
+ if (is_locked == false)
+ {
+ /* Lock obtained, return success. */
+ ret = true;
+ }
+ else
+ {
+ /* Lock was not obtained, another task already has it. */
+ }
+
+ return ret;
+} /* End of function R_BSP_Lock() */
+
+
+/***********************************************************************************************************************
+* Function Name: R_BSP_Unlock
+* Description : Release hold on lock.
+* Arguments : plock -
+* Pointer to lock structure with lock to release.
+* Return Value : true -
+* Lock was released.
+* false -
+* Lock was not released.
+***********************************************************************************************************************/
+bool R_BSP_Unlock(bsp_lock_t * plock)
+{
+ /* Set lock back to unlocked. */
+ plock->lock = false;
+
+ return true;
+} /* End of function R_BSP_Unlock() */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/locking.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/locking.h
new file mode 100644
index 000000000..454ce4776
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/locking.h
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : locking.h
+* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so
+* common resources can be accessed safely.
+***********************************************************************************************************************/
+/**********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.03.2012 1.00 First Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed-size integer typedefs. */
+#include
+/* bool support. */
+#include
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef struct
+{
+ /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */
+ int32_t lock;
+ /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */
+} bsp_lock_t;
+
+/***********************************************************************************************************************
+Exported global variables
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+bool R_BSP_Lock(bsp_lock_t * plock);
+bool R_BSP_Unlock(bsp_lock_t * plock);
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lowlvl.src b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lowlvl.src
new file mode 100644
index 000000000..a75845e40
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lowlvl.src
@@ -0,0 +1,54 @@
+;-----------------------------------------------------------------------
+;
+; FILE :lowlvl.src
+; DATE :Wed, Jul 01, 2009
+; DESCRIPTION :Program of Low level
+; CPU TYPE :RX
+;
+;-----------------------------------------------------------------------
+ .GLB _charput
+ .GLB _charget
+
+FC2E0 .EQU 00084080h
+FE2C0 .EQU 00084090h
+DBGSTAT .EQU 000840C0h
+RXFL0EN .EQU 00001000h
+TXFL0EN .EQU 00000100h
+
+ .SECTION P,CODE
+
+;-----------------------------------------------------------------------
+; _charput:
+;-----------------------------------------------------------------------
+_charput:
+ .STACK _charput = 00000000h
+__C2ESTART: MOV.L #TXFL0EN,R3
+ MOV.L #DBGSTAT,R4
+__TXLOOP: MOV.L [R4],R5
+ AND R3,R5
+ BNZ __TXLOOP
+__WRITEFC2E0: MOV.L #FC2E0,R2
+ MOV.L R1,[R2]
+__CHARPUTEXIT: RTS
+
+;-----------------------------------------------------------------------
+; _charget:
+;-----------------------------------------------------------------------
+_charget:
+ .STACK _charget = 00000000h
+__E2CSTART: MOV.L #RXFL0EN,R3
+ MOV.L #DBGSTAT,R4
+__RXLOOP: MOV.L [R4],R5
+ AND R3,R5
+ BZ __RXLOOP
+__READFE2C0: MOV.L #FE2C0,R2
+ MOV.L [R2],R1
+__CHARGETEXIT: RTS
+
+;-----------------------------------------------------------------------
+
+; End of conditional code
+ .END
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lowsrc.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lowsrc.c
new file mode 100644
index 000000000..ad9f32ce4
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/lowsrc.c
@@ -0,0 +1,332 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : lowsrc.c
+* Description : Functions to support stream I/O
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 26.10.2011 1.00 First Release
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+#include
+#include
+#include
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/*Number of I/O Stream*/
+#define IOSTREAM 20
+
+/* file number */
+#define STDIN 0 /* Standard input (console) */
+#define STDOUT 1 /* Standard output (console) */
+#define STDERR 2 /* Standard error output (console) */
+
+#define FLMIN 0 /* Minimum file number */
+#define _MOPENR 0x1
+#define _MOPENW 0x2
+#define _MOPENA 0x4
+#define _MTRUNC 0x8
+#define _MCREAT 0x10
+#define _MBIN 0x20
+#define _MEXCL 0x40
+#define _MALBUF 0x40
+#define _MALFIL 0x80
+#define _MEOF 0x100
+#define _MERR 0x200
+#define _MLBF 0x400
+#define _MNBF 0x800
+#define _MREAD 0x1000
+#define _MWRITE 0x2000
+#define _MBYTE 0x4000
+#define _MWIDE 0x8000
+/* File Flags */
+#define O_RDONLY 0x0001 /* Read only */
+#define O_WRONLY 0x0002 /* Write only */
+#define O_RDWR 0x0004 /* Both read and Write */
+#define O_CREAT 0x0008 /* A file is created if it is not existed */
+#define O_TRUNC 0x0010 /* The file size is changed to 0 if it is existed. */
+#define O_APPEND 0x0020 /* The position is set for next reading/writing */
+ /* 0: Top of the file 1: End of file */
+
+/* Special character code */
+#define CR 0x0d /* Carriage return */
+#define LF 0x0a /* Line feed */
+
+#if defined( __RX )
+const long _nfiles = IOSTREAM; /* The number of files for input/output files */
+#else
+const int _nfiles = IOSTREAM; /* The number of files for input/output files */
+#endif
+char flmod[IOSTREAM]; /* The location for the mode of opened file. */
+
+unsigned char sml_buf[IOSTREAM];
+
+#define FPATH_STDIN "C:\\stdin"
+#define FPATH_STDOUT "C:\\stdout"
+#define FPATH_STDERR "C:\\stderr"
+
+/* H8 Normal mode ,SH and RX */
+#if defined( __2000N__ ) || defined( __2600N__ ) || defined( __300HN__ ) || defined( _SH )
+/* Output one character to standard output */
+extern void charput(char);
+/* Input one character from standard input */
+extern char charget(void);
+/* Output one character to the file */
+extern char fcharput(char, unsigned char);
+/* Input one character from the file */
+extern char fcharget(char*, unsigned char);
+/* Open the file */
+extern char fileopen(char*, unsigned char, unsigned char*);
+/* Close the file */
+extern char fileclose(unsigned char);
+/* Move the file offset */
+extern char fpseek(unsigned char, long, unsigned char);
+/* Get the file offset */
+extern char fptell(unsigned char, long*);
+
+/* RX */
+#elif defined( __RX )
+/* Output one character to standard output */
+extern void charput(unsigned char);
+/* Input one character from standard input */
+extern unsigned char charget(void);
+
+/* H8 Advanced mode */
+#elif defined( __2000A__ ) || defined( __2600A__ ) || defined( __300HA__ ) || defined( __H8SXN__ ) || defined( __H8SXA__ ) || defined( __H8SXM__ ) || defined( __H8SXX__ )
+/* Output one character to standard output */
+extern void charput(char);
+/* Input one character from standard input */
+extern char charget(void);
+/* Output one character to the file */
+extern char fcharput(char, unsigned char);
+/* Input one character from the file */
+extern char fcharget(char*, unsigned char);
+/* Open the file */
+/* Specified as the number of register which stored paramter is 3 */
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);
+/* Close the file */
+extern char fileclose(unsigned char);
+/* Move the file offset */
+extern char fpseek(unsigned char, long, unsigned char);
+/* Get the file offset */
+extern char fptell(unsigned char, long*);
+
+/* H8300 and H8300L */
+#elif defined( __300__ ) || defined( __300L__ )
+/* Output one character to standard output */
+extern void charput(char);
+/* Input one character from standard input */
+extern char charget(void);
+/* Output one character to the file */
+extern char fcharput(char, unsigned char);
+/* Input one character from the file */
+extern char fcharget(char*, unsigned char);
+/* Open the file */
+/* Specified as the number of register which stored paramter is 3 */
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);
+/* Close the file */
+extern char fileclose(unsigned char);
+/* Move the file offset */
+/* Move the file offset */
+extern char __regparam3 fpseek(unsigned char, long, unsigned char);
+/* Get the file offset */
+extern char fptell(unsigned char, long*);
+#endif
+
+#include
+FILE *_Files[IOSTREAM]; // structure for FILE
+char *env_list[] = { // Array for environment variables(**environ)
+ "ENV1=temp01",
+ "ENV2=temp02",
+ "ENV9=end",
+ '\0' // Terminal for environment variables
+};
+
+char **environ = env_list;
+
+/****************************************************************************/
+/* _INIT_IOLIB */
+/* Initialize C library Functions, if necessary. */
+/* Define USES_SIMIO on Assembler Option. */
+/****************************************************************************/
+void _INIT_IOLIB( void )
+{
+ /* A file for standard input/output is opened or created. Each FILE */
+ /* structure members are initialized by the library. Each _Buf member */
+ /* in it is re-set the end of buffer pointer. */
+
+ /* Standard Input File */
+ if( freopen( FPATH_STDIN, "r", stdin ) == NULL )
+ stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */
+ stdin->_Mode = _MOPENR; /* Read only attribute */
+ stdin->_Mode |= _MNBF; /* Non-buffering for data */
+ stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */
+
+ /* Standard Output File */
+ if( freopen( FPATH_STDOUT, "w", stdout ) == NULL )
+ stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */
+ stdout->_Mode |= _MNBF; /* Non-buffering for data */
+ stdout->_Bend = stdout->_Buf + 1;/* Re-set pointer to the end of buffer */
+
+ /* Standard Error File */
+ if( freopen( FPATH_STDERR, "w", stderr ) == NULL )
+ stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */
+ stderr->_Mode |= _MNBF; /* Non-buffering for data */
+ stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */
+}
+
+/****************************************************************************/
+/* _CLOSEALL */
+/****************************************************************************/
+void _CLOSEALL( void )
+{
+ long i;
+
+ for( i=0; i < _nfiles; i++ )
+ {
+ /* Checks if the file is opened or not */
+ if( _Files[i]->_Mode & (_MOPENR | _MOPENW | _MOPENA ) )
+ fclose( _Files[i] ); /* Closes the file */
+ }
+}
+
+/**************************************************************************/
+/* open:file open */
+/* Return value:File number (Pass) */
+/* -1 (Failure) */
+/**************************************************************************/
+#if defined( __RX )
+long open(const char *name, /* File name */
+ long mode, /* Open mode */
+ long flg) /* Open flag */
+#else
+int open(char *name, /* File name */
+ int mode, /* Open mode */
+ int flg) /* Open flag */
+#endif
+{
+
+
+ if( strcmp( name, FPATH_STDIN ) == 0 ) /* Standard Input file? */
+ {
+ if( ( mode & O_RDONLY ) == 0 ) return -1;
+ flmod[STDIN] = mode;
+ return STDIN;
+ }
+ else if( strcmp( name, FPATH_STDOUT ) == 0 )/* Standard Output file? */
+ {
+ if( ( mode & O_WRONLY ) == 0 ) return -1;
+ flmod[STDOUT] = mode;
+ return STDOUT;
+ }
+ else if(strcmp(name, FPATH_STDERR ) == 0 ) /* Standard Error file? */
+ {
+ if( ( mode & O_WRONLY ) == 0 ) return -1;
+ flmod[STDERR] = mode;
+ return STDERR;
+ }
+ else return -1; /*Others */
+}
+
+#if defined( __RX )
+long close( long fileno )
+#else
+int close( int fileno )
+#endif
+{
+ return 1;
+}
+
+/**************************************************************************/
+/* write:Data write */
+/* Return value:Number of write characters (Pass) */
+/* -1 (Failure) */
+/**************************************************************************/
+#if defined( __RX )
+long write(long fileno, /* File number */
+ const unsigned char *buf, /* The address of destination buffer */
+ long count) /* The number of chacter to write */
+#else
+int write(int fileno, /* File number */
+ char *buf, /* The address of destination buffer */
+ int count) /* The number of chacter to write */
+#endif
+{
+ long i; /* A variable for counter */
+ unsigned char c; /* An output character */
+
+ /* Checking the mode of file , output each character */
+ /* Checking the attribute for Write-Only, Read-Only or Read-Write */
+ if(flmod[fileno]&O_WRONLY || flmod[fileno]&O_RDWR)
+ {
+ if( fileno == STDIN ) return -1; /* Standard Input */
+ else if( (fileno == STDOUT) || (fileno == STDERR) )
+ /* Standard Error/output */
+ {
+ for( i = count; i > 0; --i )
+ {
+ c = *buf++;
+ charput(c);
+ }
+ return count; /*Return the number of written characters */
+ }
+ else return -1; /* Incorrect file number */
+ }
+ else return -1; /* An error */
+}
+
+#if defined( __RX )
+long read( long fileno, unsigned char *buf, long count )
+#else
+int read( int fileno, char *buf, unsigned int count )
+#endif
+{
+ long i;
+
+ /* Checking the file mode with the file number, each character is input and stored the buffer */
+
+ if((flmod[fileno]&_MOPENR) || (flmod[fileno]&O_RDWR)){
+ for(i = count; i > 0; i--){
+ *buf = charget();
+ if(*buf==CR){ /* Replace the new line character */
+ *buf = LF;
+ }
+ buf++;
+ }
+ return count;
+ }
+ else {
+ return -1;
+ }
+}
+
+#if defined( __RX )
+long lseek( long fileno, long offset, long base )
+#else
+long lseek( int fileno, long offset, int base )
+#endif
+{
+ return -1L;
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h
new file mode 100644
index 000000000..acdbe7725
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp.h
@@ -0,0 +1,53 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp.h
+* H/W Platform : RSKRX111
+* Description : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef PLATFORM_BOARD_RSKRX111
+#define PLATFORM_BOARD_RSKRX111
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef PLATFORM_DEFINED
+#error "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+#include "r_bsp_config.h"
+#include ".\mcu\rx111\iodefine.h"
+#include ".\mcu\rx111\mcu_info.h"
+#include ".\board\rskrx111\rskrx111.h"
+#include ".\board\rskrx111\hwsetup.h"
+#include ".\board\rskrx111\lcd.h"
+#include ".\board\rskrx111\locking.h"
+#include ".\board\rskrx111\vecttbl.h"
+
+#endif /* PLATFORM_BOARD_RSKRX111 */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h
new file mode 100644
index 000000000..da6dc9d1e
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/r_bsp_config_reference.h
@@ -0,0 +1,250 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.c
+* Device(s) : RX111
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 51 11 5 A D FM
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)
+ | | | | | | |______not used = Blank
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________MCU_PART_GROUP = Group name
+ | | | |______________MCU_PART_SERIES = Series name
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FM = 0x0 = LFQFP/64/0.50
+ FK = 0x1 = LQFP/64/0.80
+ LF = 0x2 = TFLGA/64/0.50
+ FL = 0x3 = LFQFP/48/0.50
+ NE = 0x4 = VQFN/48/0.50
+ NC = 0x5 = HWQFN/36/0.50
+ LM = 0x6 = WFLGA/36/0.50
+ SB = 0x7 = SSOP/36/0.80
+*/
+#define MCU_PART_PACKAGE (0x0)
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 5 = 0x5 = 128KB/16KB/8KB
+ 4 = 0x4 = 96KB/16KB/8KB
+ 3 = 0x3 = 64KB/10KB/8KB
+ 1 = 0x1 = 32KB/10KB/8KB
+ J = 0x0 = 16KB/8KB/8KB
+*/
+#define MCU_PART_MEMORY_SIZE (0x5)
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 10 = 0x0 = RX110 Group
+ 11 = 0x1 = RX111 Group
+*/
+#define MCU_PART_GROUP (0x1)
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 51 = 0x0 = RX100 Series
+*/
+#define MCU_PART_SERIES (0x0)
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define MCU_PART_MEMORY_TYPE (0x0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize su=0x400
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize si=0x100
+#endif
+
+/* Heap size in bytes. */
+#define HEAP_BYTES (0x400)
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define RUN_IN_USER_MODE (0)
+
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = RTOS is used.
+*/
+#define RTOS_USED (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define CLOCK_SOURCE (4)
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the
+ settings would be:
+
+ XTAL_HZ = 16000000
+ PLL_DIV = 2
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz
+*/
+/* XTAL - Input clock frequency in Hz */
+#define XTAL_HZ (16000000)
+/* PLL Input Frequency Divider Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /4
+*/
+#define PLL_DIV (2)
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x6, x8
+*/
+#define PLL_MUL (6)
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define ICK_DIV (2)
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKB_DIV (2)
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKD_DIV (2)
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define FCK_DIV (2)
+
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a
+ function to be called when the event occurs. For example, if the user wanted the function
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would
+ do the following:
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+ If the user does not wish to be alerted of these events then they should comment out the macros.
+
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it
+ is executing. For this reason, it is recommended to keep these callback functions short as to not
+ decrease the real-time response of your system.
+*/
+/* Callback for Supervisor Instruction Violation Exception. */
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb
+
+/* Callback for Undefined Instruction Exception. */
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb
+
+/* Callback for Non-maskable Interrupt. */
+//#define NMI_ISR_CALLBACK nmi_cb
+
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source
+ is creating unwanted interrupts. */
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+
+/* Callback for Bus Error Interrupt. */
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb
+
+/* The user has the option of separately choosing little or big endian for the User Application Area */
+
+/* Endian mode for User Application.
+ 0 = Big Endian
+ Else = Little Endian (Default)
+*/
+#define USER_APP_ENDIAN (1)
+
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ OFS0 - Option Function Select Register 0
+ b31:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1) */
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select
+ 0 1 0 0: 3.10 V
+ 0 1 0 1: 3.00 V
+ 0 1 1 0: 2.90 V
+ 0 1 1 1: 2.79 V
+ 1 0 0 0: 2.68 V
+ 1 0 0 1: 2.58 V
+ 1 0 1 0: 2.48 V
+ 1 0 1 1: 2.06 V
+ 1 1 0 0: 1.96 V
+ 1 1 0 1: 1.86 V
+ b3:b2 Reserved (set to 1)
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define IO_LIB_ENABLE (1)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/resetprg.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/resetprg.c
new file mode 100644
index 000000000..8e01db9b0
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/resetprg.c
@@ -0,0 +1,416 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : resetprg.c
+* Device(s) : RX111
+* Description : Defines post-reset routines that are used to configure the MCU prior to the main program starting.
+* This is were the program counter starts on power-up or reset.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Defines machine level functions used in this file */
+#include
+/* Defines MCU configuration functions used in this file */
+#include <_h_c_lib.h>
+/* Defines standard variable types used in this file */
+#include
+#include
+
+/* This macro is here so that the stack will be declared here. This is used to prevent multiplication of stack size. */
+#define BSP_DECLARE_STACK
+/* Define the target platform */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define PSW_init (0x00030000)
+
+/***********************************************************************************************************************
+Pre-processor Directives
+***********************************************************************************************************************/
+/* Declare the contents of the function 'Change_PSW_PM_to_UserMode' as assembler to the compiler */
+#pragma inline_asm Change_PSW_PM_to_UserMode
+
+/* Set this as the entry point from a power-on reset */
+#pragma entry PowerON_Reset_PC
+
+/***********************************************************************************************************************
+External function Prototypes
+***********************************************************************************************************************/
+/* Functions to setup I/O library */
+extern void _INIT_IOLIB(void);
+extern void _CLOSEALL(void);
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+/* Power-on reset function declaration */
+void PowerON_Reset_PC(void);
+
+#if RUN_IN_USER_MODE==1
+ #if __RENESAS_VERSION__ < 0x01010000
+ /* MCU usermode switcher function declaration */
+ static void Change_PSW_PM_to_UserMode(void);
+ #endif
+#endif
+
+/* Main program function delcaration */
+void main(void);
+static void operating_frequency_set(void);
+static void clock_source_select(void);
+
+/***********************************************************************************************************************
+* Function name: PowerON_Reset_PC
+* Description : This function is the MCU's entry point from a power-on reset.
+* The following steps are taken in the startup code:
+* 1. The User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) are both set immediately after entry
+* to this function. The USP and ISP stack sizes are set in the file stacksct.h.
+* Default sizes are USP=4K and ISP=1K.
+* 2. The interrupt vector base register is set to point to the beginning of the relocatable interrupt
+* vector table.
+* 3. The MCU is setup for floating point operations by setting the initial value of the Floating Point
+* Status Word (FPSW).
+* 4. The MCU operating frequency is set by configuring the Clock Generation Circuit (CGC) in
+* operating_frequency_set.
+* 5. Calls are made to functions to setup the C runtime environment which involves initializing all
+* initialed data, zeroing all uninitialized variables, and configuring STDIO if used
+* (calls to _INITSCT and _INIT_IOLIB).
+* 6. Board-specific hardware setup, including configuring I/O pins on the MCU, in hardware_setup.
+* 7. Global interrupts are enabled by setting the I bit in the Program Status Word (PSW), and the stack
+* is switched from the ISP to the USP. The initial Interrupt Priority Level is set to zero, enabling
+* any interrupts with a priority greater than zero to be serviced.
+* 8. The processor is optionally switched to user mode. To run in user mode, set the macro
+* RUN_IN_USER_MODE above to a 1.
+* 9. The bus error interrupt is enabled to catch any accesses to invalid or reserved areas of memory.
+*
+* Once this initialization is complete, the user's main() function is called. It should not return.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+#pragma section ResetPRG // output PowerON_Reset to PResetPRG section
+void PowerON_Reset_PC(void)
+{
+ /* Stack pointers are setup prior to calling this function - see comments above */
+
+ /* Initialise the MCU processor word */
+#if __RENESAS_VERSION__ >= 0x01010000
+ set_intb((void *)__sectop("C$VECT"));
+#else
+ set_intb((unsigned long)__sectop("C$VECT"));
+#endif
+
+#ifdef NMI_ISR_CALLBACK
+ /* Enable NMI interrupt if callback is configured in r_bsp_config.h */
+ ICU.NMIER.BIT.NMIEN = 1;
+#endif
+
+ /* Switch to high-speed operation */
+ operating_frequency_set();
+
+ /* Initialize C runtime environment */
+ _INITSCT();
+
+#if IO_LIB_ENABLE == 1
+ /* Comment this out if not using I/O lib */
+ _INIT_IOLIB();
+#endif
+
+ /* Configure the MCU and YRDK hardware */
+ hardware_setup();
+
+ /* Change the MCU's usermode from supervisor to user */
+ nop();
+ set_psw(PSW_init);
+#if RUN_IN_USER_MODE==1
+ /* Use chg_pmusr() intrinsic if possible. */
+ #if __RENESAS_VERSION__ >= 0x01010000
+ chg_pmusr() ;
+ #else
+ Change_PSW_PM_to_UserMode();
+ #endif
+#endif
+
+ /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */
+ /* The ISR for this interrupt can be found in vecttbl.c in the function "bus_error_isr" */
+ /* Clear any pending interrupts */
+ IR(BSC,BUSERR) = 0;
+ /* Make this the highest priority interrupt (adjust as necessary for your application */
+ IPR(BSC,BUSERR) = 0x0F;
+ /* Enable the interrupt in the ICU*/
+ IEN(BSC,BUSERR) = 1;
+ /* Enable illegal address interrupt in the BSC */
+ BSC.BEREN.BIT.IGAEN = 1;
+
+ /* Call the main program function (should not return) */
+ main();
+
+#if IO_LIB_ENABLE == 1
+ /* Comment this out if not using I/O lib - cleans up open files */
+ _CLOSEALL();
+#endif
+
+ while(1)
+ {
+ /* Infinite loop. Put a breakpoint here if you want to catch an exit of main(). */
+ }
+}
+
+/***********************************************************************************************************************
+* Function name: operating_frequency_set
+* Description : Configures the clock settings for each of the device clocks
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void operating_frequency_set(void)
+{
+ /* Used for constructing value to write to SCKCR and CKOCR registers. */
+ uint32_t temp_clock = 0;
+
+ /*
+ Clock Description Frequency
+ ----------------------------------------
+ Input Clock Frequency............ 16 MHz
+ PLL frequency (x3)............... 48 MHz
+ Internal Clock Frequency......... 24 MHz
+ Peripheral Clock Frequency....... 24 MHz
+ Clock Out Frequency.............. 1 MHz */
+
+ volatile unsigned int i;
+
+ /* Protect off. */
+ SYSTEM.PRCR.WORD = 0xA50B;
+
+ /* Select the clock based upon user's choice. */
+ clock_source_select();
+
+
+ /* Figure out setting for FCK bits. */
+#if FCK_DIV == 1
+ /* Do nothing since FCK bits should be 0. */
+#elif FCK_DIV == 2
+ temp_clock |= 0x10000000;
+#elif FCK_DIV == 4
+ temp_clock |= 0x20000000;
+#elif FCK_DIV == 8
+ temp_clock |= 0x30000000;
+#elif FCK_DIV == 16
+ temp_clock |= 0x40000000;
+#elif FCK_DIV == 32
+ temp_clock |= 0x50000000;
+#elif FCK_DIV == 64
+ temp_clock |= 0x60000000;
+#else
+ #error "Error! Invalid setting for FCK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for ICK bits. */
+#if ICK_DIV == 1
+ /* Do nothing since ICK bits should be 0. */
+#elif ICK_DIV == 2
+ temp_clock |= 0x01000000;
+#elif ICK_DIV == 4
+ temp_clock |= 0x02000000;
+#elif ICK_DIV == 8
+ temp_clock |= 0x03000000;
+#elif ICK_DIV == 16
+ temp_clock |= 0x04000000;
+#elif ICK_DIV == 32
+ temp_clock |= 0x05000000;
+#elif ICK_DIV == 64
+ temp_clock |= 0x06000000;
+#else
+ #error "Error! Invalid setting for ICK_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKB bits. */
+#if PCKB_DIV == 1
+ /* Do nothing since PCKB bits should be 0. */
+#elif PCKB_DIV == 2
+ temp_clock |= 0x00000100;
+#elif PCKB_DIV == 4
+ temp_clock |= 0x00000200;
+#elif PCKB_DIV == 8
+ temp_clock |= 0x00000300;
+#elif PCKB_DIV == 16
+ temp_clock |= 0x00000400;
+#elif PCKB_DIV == 32
+ temp_clock |= 0x00000500;
+#elif PCKB_DIV == 64
+ temp_clock |= 0x00000600;
+#else
+ #error "Error! Invalid setting for PCKB_DIV in r_bsp_config.h"
+#endif
+
+ /* Figure out setting for PCKD bits. */
+#if PCKD_DIV == 1
+ /* Do nothing since PCKD bits should be 0. */
+#elif PCKD_DIV == 2
+ temp_clock |= 0x00000001;
+#elif PCKD_DIV == 4
+ temp_clock |= 0x00000002;
+#elif PCKD_DIV == 8
+ temp_clock |= 0x00000003;
+#elif PCKD_DIV == 16
+ temp_clock |= 0x00000004;
+#elif PCKD_DIV == 32
+ temp_clock |= 0x00000005;
+#elif PCKD_DIV == 64
+ temp_clock |= 0x00000006;
+#else
+ #error "Error! Invalid setting for PCKD_DIV in r_bsp_config.h"
+#endif
+
+ /* Set SCKCR register. */
+ SYSTEM.SCKCR.LONG = temp_clock;
+
+ /* Choose clock source. Default for r_bsp_config.h is PLL. */
+ SYSTEM.SCKCR3.WORD = ((uint16_t)CLOCK_SOURCE) << 8;
+
+ /* Protect on. */
+ SYSTEM.PRCR.WORD = 0xA500;
+}
+
+/***********************************************************************************************************************
+* Function name: clock_source_select
+* Description : Enables and disables clocks as chosen by the user. This function also implements the software delays
+* needed for the clocks to stabilize.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+static void clock_source_select (void)
+{
+ /* Declared volatile for software delay purposes. */
+ volatile unsigned int i;
+
+ /* NOTE: AS OF VERSION 0.50 OF THE RX111 HARDWARE MANUAL, ALL OF THE CLOCK
+ * STABILIZATION TIMES ARE TBD. FOR NOW, WHERE EVER A WAIT COUNT REGISTER
+ * IS AVAILABLE, THE DELAY IS SET TO THE MAX NUMBER OF CYCLES. WHERE EVER
+ * DELAY LOOPS ARE PRESENT, THE VALUES FROM THE 63N ARE RE-USED. KEEP IN
+ * MIND THAT THE 63N RUNS ON A FASTER CRYSTAL.
+ */
+
+#if (CLOCK_SOURCE == 1)
+ /* HOCO is chosen. Start it operating. */
+ SYSTEM.HOCOCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the HOCO has stabilized.*/
+ for(i = 0; i< 28; i++) // tHOCOWT2 is TBD
+ {
+ nop() ;
+ }
+#else
+ /* HOCO is not chosen. Stop the HOCO. */
+ SYSTEM.HOCOCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 2)
+ /* Main clock oscillator is chosen. Start it operating. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock has stabilized. */
+ for(i = 0; i< 140; i++) // tMAINOSCWT is TBD
+ {
+ nop() ;
+ }
+#endif
+
+#if (CLOCK_SOURCE == 3)
+ /* Sub-clock oscillator is chosen. Start it operating. */
+ /* In section 9.8.4, there is a reference to a SOSCWTCR register, but there is no
+ * description for this register in the manual nor reference for it in iodefine.h. */
+
+ /* Set the sub-clock to operating. */
+ SYSTEM.SOSCCR.BYTE = 0x00;
+ /* The delay period needed is to make sure that the sub-clock has stabilized. */
+ for(i = 0; i< 30233; i++) // tSUBOSCWT0 is TBD
+ {
+ nop() ;
+ }
+#else
+ /* Set the sub-clock to stopped. */
+ SYSTEM.SOSCCR.BYTE = 0x01;
+#endif
+
+#if (CLOCK_SOURCE == 4)
+ /* PLL is chosen. Start it operating. Must start main clock as well since PLL uses it. */
+ SYSTEM.MOSCWTCR.BYTE = 0x07; // Wait 65,536 cycles
+ /* Set the main clock to operating. */
+ SYSTEM.MOSCCR.BYTE = 0x00;
+
+ /* Set PLL Input Divisor. */
+ SYSTEM.PLLCR.BIT.PLIDIV = PLL_DIV >> 1;
+
+ /* Set PLL Multiplier. */
+ SYSTEM.PLLCR.BIT.STC = (PLL_MUL * 2) - 1;
+
+ /* Set the PLL to operating. */
+ SYSTEM.PLLCR2.BYTE = 0x00;
+ /* The delay period needed is to make sure that the main clock and PLL have stabilized. */
+ for(i = 0; i< 140; i++) // tPLLWT2 is TBD
+ {
+ nop() ;
+ }
+#endif
+
+ /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn
+ it off until another clock has been enabled and is ready to use. */
+#if (CLOCK_SOURCE == 0)
+ /* LOCO is chosen. This is the default out of reset. */
+ SYSTEM.LOCOCR.BYTE = 0x00;
+#else
+ /* LOCO is not chosen and another clock has already been setup. Turn off the LOCO. */
+ SYSTEM.LOCOCR.BYTE = 0x01;
+#endif
+
+ /* Make sure a valid clock was chosen. */
+#if (CLOCK_SOURCE > 4) || (CLOCK_SOURCE < 0)
+ #error "ERROR - Valid clock source must be chosen in r_bsp_config.h using CLOCK_SOURCE macro."
+#endif
+}
+
+
+/***********************************************************************************************************************
+* Function name: Change_PSW_PM_to_UserMode
+* Description : Assembler function, used to change the MCU's usermode from supervisor to user.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+#if RUN_IN_USER_MODE==1
+ #if __RENESAS_VERSION__ < 0x01010000
+static void Change_PSW_PM_to_UserMode(void)
+{
+ MVFC PSW,R1
+ OR #00100000h,R1
+ PUSH.L R1
+ MVFC PC,R1
+ ADD #10,R1
+ PUSH.L R1
+ RTE
+ NOP
+ NOP
+}
+ #endif
+#endif
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h
new file mode 100644
index 000000000..af3a40058
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/rskrx111.h
@@ -0,0 +1,63 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : rskrx111.h
+* H/W Platform : RSKRX111
+* Description : Board specific definitions for the RSKRX111.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef RSKRX111_H
+#define RSKRX111_H
+
+/* Local defines */
+#define LED_ON (0)
+#define LED_OFF (1)
+#define SET_BIT_HIGH (1)
+#define SET_BIT_LOW (0)
+#define SET_BYTE_HIGH (0xFF)
+#define SET_BYTE_LOW (0x00)
+
+/* Switches */
+#define SW_ACTIVE 0
+#define SW1 PORT3.PIDR.BIT.B0
+#define SW2 PORT3.PIDR.BIT.B1
+#define SW3 PORTE.PIDR.BIT.B4
+#define SW1_PDR PORT3.PDR.BIT.B0
+#define SW2_PDR PORT3.PDR.BIT.B1
+#define SW3_PDR PORTE.PDR.BIT.B4
+#define SW1_PMR PORT3.PMR.BIT.B0
+#define SW2_PMR PORT3.PMR.BIT.B1
+#define SW3_PMR PORTE.PMR.BIT.B4
+
+/* LEDs */
+#define LED0 PORTB.PODR.BIT.B7
+#define LED1 PORTA.PODR.BIT.B0
+#define LED2 PORT5.PODR.BIT.B4
+#define LED3 PORT1.PODR.BIT.B7
+#define LED0_PDR PORTB.PDR.BIT.B7
+#define LED1_PDR PORTA.PDR.BIT.B0
+#define LED2_PDR PORT5.PDR.BIT.B4
+#define LED3_PDR PORT1.PDR.BIT.B7
+
+
+#endif /* RSKRX111_H */
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/sbrk.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/sbrk.c
new file mode 100644
index 000000000..ee808277f
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/sbrk.c
@@ -0,0 +1,96 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : sbrk.c
+* Device(s) : RX
+* Description : Configures the MCU heap memory. The size of the heap is defined by the macro HEAPSIZE below.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 26.10.2011 1.00 First Release
+* : 12.03.2012 1.10 Heap size is now defined in r_bsp_config.h, not sbrk.h.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Provides standard definitions used in this file */
+#include
+/* Defines standard input/output functions used in this file */
+#include
+/* Defines standard variable types used in this file */
+#include
+/* Used for getting HEAP_BYTES macro. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Function Prototypes
+***********************************************************************************************************************/
+/* Memory allocation function prototype declaration */
+int8_t *sbrk(size_t size);
+
+/***********************************************************************************************************************
+Global Variables
+***********************************************************************************************************************/
+//const size_t _sbrk_size= /* Specifies the minimum unit of */
+/* the defined heap area */
+extern int8_t *_s1ptr;
+
+union HEAP_TYPE
+{
+ int32_t dummy; /* Dummy for 4-byte boundary */
+ int8_t heap[HEAP_BYTES]; /* Declaration of the area managed by sbrk*/
+};
+/* Declare memory heap area */
+static union HEAP_TYPE heap_area;
+/* End address allocated by sbrk */
+static int8_t *brk=(int8_t *)&heap_area;
+
+/***********************************************************************************************************************
+* Function name: sbrk
+* Description : This function configures MCU memory area allocation.
+* Arguments : size -
+* assigned area size
+* Return value : Start address of allocated area (pass)
+* -1 (failure)
+***********************************************************************************************************************/
+int8_t *sbrk(size_t size)
+{
+ int8_t *p;
+
+ if (brk+size > heap_area.heap+HEAP_BYTES)
+ {
+ /* Empty area size */
+ p = (int8_t *)-1;
+ }
+ else
+ {
+ /* Area assignment */
+ p = brk;
+
+ /* End address update */
+ brk += size;
+ }
+
+ /* Return result */
+ return p;
+}
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/vecttbl.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/vecttbl.c
new file mode 100644
index 000000000..6dc4b7f1a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/vecttbl.c
@@ -0,0 +1,206 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : vecttbl.c
+* Device(s) : RX11x
+* Description : Definition of the fixed vector table and option setting memory.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed size integers. */
+#include
+/* Used for nop(). */
+#include
+/* BSP configuration. */
+#include "platform.h"
+
+#pragma section IntPRG
+
+/***********************************************************************************************************************
+* Function name: PowerON_Reset_PC
+* Description : The reset vector points to this function. Code execution starts in this function after reset.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+extern void PowerON_Reset_PC(void);
+
+/***********************************************************************************************************************
+* Function name: excep_supervisor_inst_isr
+* Description : Supervisor Instruction Violation ISR
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+#pragma interrupt (excep_supervisor_inst_isr)
+void excep_supervisor_inst_isr(void)
+{
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */
+#if defined(EXCEP_SUPERVISOR_ISR_CALLBACK)
+ EXCEP_SUPERVISOR_ISR_CALLBACK();
+
+ /* If you do not put the MCU in Supervisor mode before returning then it will just execute the same violating
+ instruction again and come back in here. Since the PSW is restored from the stack when returning from the
+ exception, you would need to alter the saved PSW on the stack to change to Supervisor mode. We do not do this
+ here because the only 'safe' way to do this would be to write this function in assembly. Even then most users
+ would probably want to handle this someway instead of just going back to the application. */
+#else
+ brk();
+#endif
+}
+
+/***********************************************************************************************************************
+* Function name: excep_undefined_inst_isr
+* Description : Undefined instruction exception ISR
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+#pragma interrupt (excep_undefined_inst_isr)
+void excep_undefined_inst_isr(void)
+{
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */
+#if defined(EXCEP_UNDEFINED_INSTR_ISR_CALLBACK)
+ EXCEP_UNDEFINED_INSTR_ISR_CALLBACK();
+#else
+ brk();
+#endif
+}
+
+/***********************************************************************************************************************
+* Function name: non_maskable_isr
+* Description : Non-maskable interrupt ISR
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+#pragma interrupt (non_maskable_isr)
+void non_maskable_isr(void)
+{
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */
+#if defined(NMI_ISR_CALLBACK)
+ NMI_ISR_CALLBACK();
+
+ /* Clear NMI flag. */
+ ICU.NMICLR.BIT.NMICLR = 1;
+#else
+ brk();
+#endif
+}
+
+/***********************************************************************************************************************
+* Function name: undefined_interrupt_source_isr
+* Description : All undefined interrupt vectors point to this function.
+* Set a breakpoint in this function to determine which source is creating unwanted interrupts.
+* Arguments : none
+* Return Value : none
+***********************************************************************************************************************/
+#pragma interrupt (undefined_interrupt_source_isr)
+void undefined_interrupt_source_isr(void)
+{
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */
+#if defined(UNDEFINED_INT_ISR_CALLBACK)
+ UNDEFINED_INT_ISR_CALLBACK();
+#else
+ brk();
+#endif
+}
+
+/***********************************************************************************************************************
+* Function name: bus_error_isr
+* Description : By default, this demo code enables the Bus Error Interrupt. This interrupt will fire if the user tries
+* to access code or data from one of the reserved areas in the memory map, including the areas covered
+* by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint
+* during debugging and development, and further handling should be added by the user for their
+* application.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+#pragma interrupt (bus_error_isr(vect=VECT(BSC,BUSERR)))
+void bus_error_isr (void)
+{
+ /* Clear the bus error */
+ BSC.BERCLR.BIT.STSCLR = 1;
+
+ /*
+ To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD. The upper
+ 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units)
+ */
+
+ /* If the user defined a callback function in r_bsp_config.h then it will be called here. */
+#if defined(BUS_ERROR_ISR_CALLBACK)
+ BUS_ERROR_ISR_CALLBACK();
+#else
+ nop();
+#endif
+}
+
+void Dummy( void )
+{
+ brk();
+}
+
+/***********************************************************************************************************************
+* The following array fills in the endian and option function select registers, and the fixed vector table
+* bytes.
+***********************************************************************************************************************/
+#pragma section C FIXEDVECT
+
+void (*const Fixed_Vectors[])(void) = {
+//;0xffffffd0 Exception(Supervisor Instruction)
+ excep_supervisor_inst_isr,
+//;0xffffffd4 Reserved
+ Dummy,
+//;0xffffffd8 Reserved
+ Dummy,
+//;0xffffffdc Exception(Undefined Instruction)
+ undefined_interrupt_source_isr,
+//;0xffffffe0 Reserved
+ Dummy,
+//;0xffffffe4 Reserved
+ Dummy,
+//;0xffffffe8 Reserved
+ Dummy,
+//;0xffffffec Reserved
+ Dummy,
+//;0xfffffff0 Reserved
+ Dummy,
+//;0xfffffff4 Reserved
+ Dummy,
+//;0xfffffff8 NMI
+ non_maskable_isr,
+//;0xfffffffc RESET
+//;<>
+//;Power On Reset PC
+PowerON_Reset_PC
+//;<>
+};
+
+#pragma address _MDEreg=0xffffff80 // MDE register (Single Chip Mode)
+#ifdef __BIG
+ const unsigned long _MDEreg = 0xfffffff8; // big
+#else
+ const unsigned long _MDEreg = 0xffffffff; // little
+#endif
+
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/vecttbl.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/vecttbl.h
new file mode 100644
index 000000000..f8d32629a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/rskrx111/vecttbl.h
@@ -0,0 +1,65 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : vecttbl.h
+* Device(s) : RX111
+* Description : Has function prototypes for exception callback functions.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 1.20 Beta Release.
+***********************************************************************************************************************/
+
+#ifndef VECTTBL_HEADER_INC
+#define VECTTBL_HEADER_INC
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed size integers. */
+#include
+/* Used for nop(). */
+#include
+/* BSP configuration. */
+#include "platform.h"
+
+/***********************************************************************************************************************
+Exported global functions (to be accessed by other files)
+***********************************************************************************************************************/
+#if defined(EXCEP_SUPERVISOR_ISR_CALLBACK)
+void EXCEP_SUPERVISOR_ISR_CALLBACK(void);
+#endif
+
+#if defined(EXCEP_UNDEFINED_INSTR_ISR_CALLBACK)
+void EXCEP_UNDEFINED_INSTR_ISR_CALLBACK(void);
+#endif
+
+#if defined(NMI_ISR_CALLBACK)
+void NMI_ISR_CALLBACK(void);
+#endif
+
+#if defined(UNDEFINED_INT_ISR_CALLBACK)
+void UNDEFINED_INT_ISR_CALLBACK(void);
+#endif
+
+#if defined(BUS_ERROR_ISR_CALLBACK)
+void BUS_ERROR_ISR_CALLBACK(void);
+#endif
+
+#endif /* VECTTBL_HEADER_INC */
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/r_bsp.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/r_bsp.h
new file mode 100644
index 000000000..bd8881cd6
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/board/user/r_bsp.h
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp.h
+* Description : Has the header files that should be included for this platform.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 13.01.2012 1.00 First Release
+* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure.
+***********************************************************************************************************************/
+
+#ifndef PLATFORM_BOARD_USER
+#define PLATFORM_BOARD_USER
+
+/* Make sure that no other platforms have already been defined. Do not touch this! */
+#ifdef PLATFORM_DEFINED
+#error "Error - Multiple platforms defined in platform.h!"
+#else
+#define PLATFORM_DEFINED
+#endif
+
+/***********************************************************************************************************************
+INCLUDE APPROPRIATE MCU AND BOARD FILES
+***********************************************************************************************************************/
+/* This is a user defined board. Start off by:
+ 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group).
+ 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h.
+ 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier.
+ 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h.
+ 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h.
+ You can also add your own include files here as well. */
+#include "r_bsp_config.h"
+#include ".\mcu\*MCU Group*\mcu_info.h"
+
+#endif /* PLATFORM_BOARD_USER */
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/iodefine.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/iodefine.h
new file mode 100644
index 000000000..cd263c632
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/iodefine.h
@@ -0,0 +1,5143 @@
+/********************************************************************************/
+/* */
+/* Device : RX/RX100/RX111 */
+/* File Name : iodefine.h */
+/* Abstract : Definition of I/O Register. */
+/* History : V0.5 (2012-09-25) [Hardware Manual Revision : 0.50] */
+/* Note : This is a typical example. */
+/* */
+/* Copyright(c) 2012 Renesas Electronics Corp. */
+/* And Renesas Solutions Corp. ,All Rights Reserved. */
+/* */
+/********************************************************************************/
+/* */
+/* DESCRIPTION : Definition of ICU Register */
+/* CPU TYPE : RX111 */
+/* */
+/* Usage : IR,DTCER,IER,IPR of ICU Register */
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */
+/* The bit access operation is "Bit_Name(interrupt source,name)". */
+/* A part of the name can be omitted. */
+/* for example : */
+/* IR(MTU0,TGIA0) = 0; expands to : */
+/* ICU.IR[114].BIT.IR = 0; */
+/* */
+/* DTCE(ICU,IRQ0) = 1; expands to : */
+/* ICU.DTCER[64].BIT.DTCE = 1; */
+/* */
+/* IEN(CMT0,CMI0) = 1; expands to : */
+/* ICU.IER[0x03].BIT.IEN4 = 1; */
+/* */
+/* IPR(MTU1,TGIA1) = 2; expands to : */
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */
+/* ICU.IPR[121].BIT.IPR = 2; */
+/* */
+/* IPR(SCI1,ERI1) = 3; expands to : */
+/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */
+/* ICU.IPR[218].BIT.IPR = 3; */
+/* */
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */
+/* The number of vector is "(interrupt source, name)". */
+/* for example : */
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */
+/* #pragma interrupt INT_IRQ0(vect=64) */
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */
+/* */
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */
+/* The bit access operation is "MSTP(name)". */
+/* The name that can be used is a macro name defined with "iodefine.h". */
+/* for example : */
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */
+/* */
+/* */
+/********************************************************************************/
+#ifndef __RX111IODEFINE_HEADER__
+#define __RX111IODEFINE_HEADER__
+#pragma bit_order left
+#pragma unpack
+struct st_bsc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char STSCLR:1;
+ } BIT;
+ } BERCLR;
+ char wk0[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IGAEN:1;
+ } BIT;
+ } BEREN;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MST:3;
+ unsigned char :3;
+ unsigned char IA:1;
+ } BIT;
+ } BERSR1;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADDR:13;
+ } BIT;
+ } BERSR2;
+ char wk3[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short BPFB:2;
+ unsigned short :2;
+ unsigned short BPGB:2;
+ unsigned short BPIB:2;
+ unsigned short BPRO:2;
+ unsigned short BPRA:2;
+ } BIT;
+ } BUSPRI;
+};
+
+struct st_cac {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char CFME:1;
+ } BIT;
+ } CACR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char EDGES:2;
+ unsigned char TCSS:2;
+ unsigned char FMCS:3;
+ unsigned char CACREFE:1;
+ } BIT;
+ } CACR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DFS:2;
+ unsigned char RCDS:2;
+ unsigned char RSCS:3;
+ unsigned char RPS:1;
+ } BIT;
+ } CACR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char OVFFCL:1;
+ unsigned char MENDFCL:1;
+ unsigned char FERRFCL:1;
+ unsigned char :1;
+ unsigned char OVFIE:1;
+ unsigned char MENDIE:1;
+ unsigned char FERRIE:1;
+ } BIT;
+ } CAICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char OVFF:1;
+ unsigned char MENDF:1;
+ unsigned char FERRF:1;
+ } BIT;
+ } CASTR;
+ char wk0[1];
+ unsigned short CAULVR;
+ unsigned short CALLVR;
+ unsigned short CACNTBR;
+};
+
+struct st_cmt {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :14;
+ unsigned short STR1:1;
+ unsigned short STR0:1;
+ } BIT;
+ } CMSTR0;
+};
+
+struct st_cmt0 {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :9;
+ unsigned short CMIE:1;
+ unsigned short :4;
+ unsigned short CKS:2;
+ } BIT;
+ } CMCR;
+ unsigned short CMCNT;
+ unsigned short CMCOR;
+};
+
+struct st_crc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DORCLR:1;
+ unsigned char :4;
+ unsigned char LMS:1;
+ unsigned char GPS:2;
+ } BIT;
+ } CRCCR;
+ unsigned char CRCDIR;
+ unsigned short CRCDOR;
+};
+
+struct st_da {
+ unsigned short DADR0;
+ unsigned short DADR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DAOE1:1;
+ unsigned char DAOE0:1;
+ } BIT;
+ } DACR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DPSEL:1;
+ } BIT;
+ } DADPR;
+};
+
+struct st_doc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char DOPCFCL:1;
+ unsigned char DOPCF:1;
+ unsigned char DOPCIE:1;
+ unsigned char :1;
+ unsigned char DCSEL:1;
+ unsigned char OMS:2;
+ } BIT;
+ } DOCR;
+ char wk0[1];
+ unsigned short DODIR;
+ unsigned short DODSR;
+};
+
+struct st_dtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char RRS:1;
+ } BIT;
+ } DTCCR;
+ char wk0[3];
+ void *DTCVBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SHORT:1;
+ } BIT;
+ } DTCADMOD;
+ char wk1[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DTCST:1;
+ } BIT;
+ } DTCST;
+ char wk2[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ACT:1;
+ unsigned short :7;
+ unsigned short VECN:8;
+ } BIT;
+ } DTCSTS;
+};
+
+struct st_elc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELCON:1;
+ } BIT;
+ } ELCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ELS:8;
+ } BIT;
+ } ELSR[26];
+ char wk0[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTU3MD:2;
+ unsigned char MTU2MD:2;
+ unsigned char MTU1MD:2;
+ } BIT;
+ } ELOPA;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char MTU4MD:2;
+ } BIT;
+ } ELOPB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char CMT1MD:2;
+ } BIT;
+ } ELOPC;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PGR7:1;
+ unsigned char PGR6:1;
+ unsigned char PGR5:1;
+ unsigned char PGR4:1;
+ unsigned char PGR3:1;
+ unsigned char PGR2:1;
+ unsigned char PGR1:1;
+ unsigned char PGR0:1;
+ } BIT;
+ } PGR1;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PGCO:3;
+ unsigned char :1;
+ unsigned char PGCOVE:1;
+ unsigned char PGCI:2;
+ } BIT;
+ } PGC1;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PDBF7:1;
+ unsigned char PDBF6:1;
+ unsigned char PDBF5:1;
+ unsigned char PDBF4:1;
+ unsigned char PDBF3:1;
+ unsigned char PDBF2:1;
+ unsigned char PDBF1:1;
+ unsigned char PDBF0:1;
+ } BIT;
+ } PDBF1;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSM:2;
+ unsigned char PSP:2;
+ unsigned char PSB:3;
+ } BIT;
+ } PEL0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSM:2;
+ unsigned char PSP:2;
+ unsigned char PSB:3;
+ } BIT;
+ } PEL1;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char WI:1;
+ unsigned char WE:1;
+ unsigned char :5;
+ unsigned char SEG:1;
+ } BIT;
+ } ELSEGR;
+};
+
+struct st_flash {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DFLEN:1;
+ } BIT;
+ } DFLCTL;
+};
+
+struct st_icu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IR:1;
+ } BIT;
+ } IR[250];
+ char wk0[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char DTCE:1;
+ } BIT;
+ } DTCER[249];
+ char wk1[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IEN7:1;
+ unsigned char IEN6:1;
+ unsigned char IEN5:1;
+ unsigned char IEN4:1;
+ unsigned char IEN3:1;
+ unsigned char IEN2:1;
+ unsigned char IEN1:1;
+ unsigned char IEN0:1;
+ } BIT;
+ } IER[32];
+ char wk2[192];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SWINT:1;
+ } BIT;
+ } SWINTR;
+ char wk3[15];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FIEN:1;
+ unsigned short :7;
+ unsigned short FVCT:8;
+ } BIT;
+ } FIR;
+ char wk4[14];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char IPR:4;
+ } BIT;
+ } IPR[250];
+ char wk5[262];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char IRQMD:2;
+ } BIT;
+ } IRQCR[8];
+ char wk6[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char FLTEN7:1;
+ unsigned char FLTEN6:1;
+ unsigned char FLTEN5:1;
+ unsigned char FLTEN4:1;
+ unsigned char FLTEN3:1;
+ unsigned char FLTEN2:1;
+ unsigned char FLTEN1:1;
+ unsigned char FLTEN0:1;
+ } BIT;
+ } IRQFLTE0;
+ char wk7[3];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short FCLKSEL7:2;
+ unsigned short FCLKSEL6:2;
+ unsigned short FCLKSEL5:2;
+ unsigned short FCLKSEL4:2;
+ unsigned short FCLKSEL3:2;
+ unsigned short FCLKSEL2:2;
+ unsigned short FCLKSEL1:2;
+ unsigned short FCLKSEL0:2;
+ } BIT;
+ } IRQFLTC0;
+ char wk8[106];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2ST:1;
+ unsigned char LVD1ST:1;
+ unsigned char IWDTST:1;
+ unsigned char :1;
+ unsigned char OSTST:1;
+ unsigned char NMIST:1;
+ } BIT;
+ } NMISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2EN:1;
+ unsigned char LVD1EN:1;
+ unsigned char IWDTEN:1;
+ unsigned char :1;
+ unsigned char OSTEN:1;
+ unsigned char NMIEN:1;
+ } BIT;
+ } NMIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2CLR:1;
+ unsigned char LVD1CLR:1;
+ unsigned char IWDTCLR:1;
+ unsigned char :1;
+ unsigned char OSTCLR:1;
+ unsigned char NMICLR:1;
+ } BIT;
+ } NMICLR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char NMIMD:1;
+ } BIT;
+ } NMICR;
+ char wk9[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char NFLTEN:1;
+ } BIT;
+ } NMIFLTE;
+ char wk10[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char NFCLKSEL:2;
+ } BIT;
+ } NMIFLTC;
+};
+
+struct st_iwdt {
+ unsigned char IWDTRR;
+ char wk0[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :2;
+ unsigned short RPSS:2;
+ unsigned short :2;
+ unsigned short RPES:2;
+ unsigned short CKS:4;
+ unsigned short :2;
+ unsigned short TOPS:2;
+ } BIT;
+ } IWDTCR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short REFEF:1;
+ unsigned short UNDFF:1;
+ unsigned short CNTVAL:14;
+ } BIT;
+ } IWDTSR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTIRQS:1;
+ } BIT;
+ } IWDTRCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SLCSTP:1;
+ } BIT;
+ } IWDTCSTPR;
+};
+
+struct st_mpc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B0WI:1;
+ unsigned char PFSWE:1;
+ } BIT;
+ } PWPR;
+ char wk0[35];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P03PFS;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P05PFS;
+ char wk2[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P14PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P15PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P16PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P17PFS;
+ char wk3[6];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P26PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P27PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P30PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P31PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } P32PFS;
+ char wk4[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ } BIT;
+ } P35PFS;
+ char wk5[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P40PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P41PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P42PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P43PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P44PFS;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } P46PFS;
+ char wk7[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P54PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } P55PFS;
+ char wk8[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA1PFS;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA4PFS;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PA6PFS;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB1PFS;
+ char wk12[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB3PFS;
+ char wk13[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PB7PFS;
+ char wk14[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char PSEL:5;
+ } BIT;
+ } PC7PFS;
+ char wk15[8];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE0PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE1PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE2PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE3PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE4PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE5PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ unsigned char ISEL:1;
+ unsigned char :1;
+ unsigned char PSEL:5;
+ } BIT;
+ } PE7PFS;
+ char wk16[30];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ6PFS;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ASEL:1;
+ } BIT;
+ } PJ7PFS;
+};
+
+struct st_mtu {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char OE4D:1;
+ unsigned char OE4C:1;
+ unsigned char OE3D:1;
+ unsigned char OE4B:1;
+ unsigned char OE4A:1;
+ unsigned char OE3B:1;
+ } BIT;
+ } TOER;
+ char wk0[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char BDC:1;
+ unsigned char N:1;
+ unsigned char P:1;
+ unsigned char FB:1;
+ unsigned char WF:1;
+ unsigned char VF:1;
+ unsigned char UF:1;
+ } BIT;
+ } TGCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PSYE:1;
+ unsigned char :2;
+ unsigned char TOCL:1;
+ unsigned char TOCS:1;
+ unsigned char OLSN:1;
+ unsigned char OLSP:1;
+ } BIT;
+ } TOCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BF:2;
+ unsigned char OLS3N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS1P:1;
+ } BIT;
+ } TOCR2;
+ char wk1[4];
+ unsigned short TCDR;
+ unsigned short TDDR;
+ char wk2[8];
+ unsigned short TCNTS;
+ unsigned short TCBR;
+ char wk3[12];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char T3AEN:1;
+ unsigned char T3ACOR:3;
+ unsigned char T4VEN:1;
+ unsigned char T4VCOR:3;
+ } BIT;
+ } TITCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char T3ACNT:3;
+ unsigned char :1;
+ unsigned char T4VCNT:3;
+ } BIT;
+ } TITCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char BTE:2;
+ } BIT;
+ } TBTER;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char TDER:1;
+ } BIT;
+ } TDER;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char OLS3N:1;
+ unsigned char OLS3P:1;
+ unsigned char OLS2N:1;
+ unsigned char OLS2P:1;
+ unsigned char OLS1N:1;
+ unsigned char OLS1P:1;
+ } BIT;
+ } TOLBR;
+ char wk6[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCE:1;
+ unsigned char :6;
+ unsigned char WRE:1;
+ } BIT;
+ } TWCR;
+ char wk7[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CST4:1;
+ unsigned char CST3:1;
+ unsigned char :3;
+ unsigned char CST2:1;
+ unsigned char CST1:1;
+ unsigned char CST0:1;
+ } BIT;
+ } TSTR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SYNC4:1;
+ unsigned char SYNC3:1;
+ unsigned char :3;
+ unsigned char SYNC2:1;
+ unsigned char SYNC1:1;
+ unsigned char SYNC0:1;
+ } BIT;
+ } TSYR;
+ char wk8[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char RWE:1;
+ } BIT;
+ } TRWER;
+};
+
+struct st_mtu0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk0[111];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char BFE:1;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk1[16];
+ unsigned short TGRE;
+ unsigned short TGRF;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TGIEF:1;
+ unsigned char TGIEE:1;
+ } BIT;
+ } TIER2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+};
+
+struct st_mtu1 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk1[238];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char CCLR:2;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIOR;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :1;
+ unsigned char TCIEU:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk3[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char I2BE:1;
+ unsigned char I2AE:1;
+ unsigned char I1BE:1;
+ unsigned char I1AE:1;
+ } BIT;
+ } TICCR;
+};
+
+struct st_mtu2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+ char wk0[365];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char CCLR:2;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIOR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :1;
+ unsigned char TCIEU:1;
+ unsigned char TCIEV:1;
+ unsigned char :2;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ unsigned short TCNT;
+ unsigned short TGRA;
+ unsigned short TGRB;
+};
+
+struct st_mtu3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char :2;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ char wk3[7];
+ unsigned short TCNT;
+ char wk4[6];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk5[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk6[4];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+ char wk8[90];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu4 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CCLR:3;
+ unsigned char CKEG:2;
+ unsigned char TPSC:3;
+ } BIT;
+ } TCR;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char BFB:1;
+ unsigned char BFA:1;
+ unsigned char MD:4;
+ } BIT;
+ } TMDR;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOB:4;
+ unsigned char IOA:4;
+ } BIT;
+ } TIORH;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IOD:4;
+ unsigned char IOC:4;
+ } BIT;
+ } TIORL;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TTGE:1;
+ unsigned char TTGE2:1;
+ unsigned char :1;
+ unsigned char TCIEV:1;
+ unsigned char TGIED:1;
+ unsigned char TGIEC:1;
+ unsigned char TGIEB:1;
+ unsigned char TGIEA:1;
+ } BIT;
+ } TIER;
+ char wk4[8];
+ unsigned short TCNT;
+ char wk5[8];
+ unsigned short TGRA;
+ unsigned short TGRB;
+ char wk6[8];
+ unsigned short TGRC;
+ unsigned short TGRD;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TCFD:1;
+ } BIT;
+ } TSR;
+ char wk8[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TTSE:1;
+ unsigned char TTSB:1;
+ unsigned char TTSA:1;
+ } BIT;
+ } TBTM;
+ char wk9[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BF:2;
+ unsigned short :6;
+ unsigned short UT4AE:1;
+ unsigned short DT4AE:1;
+ unsigned short UT4BE:1;
+ unsigned short DT4BE:1;
+ unsigned short ITA3AE:1;
+ unsigned short ITA4VE:1;
+ unsigned short ITB3AE:1;
+ unsigned short ITB4VE:1;
+ } BIT;
+ } TADCR;
+ char wk10[2];
+ unsigned short TADCORA;
+ unsigned short TADCORB;
+ unsigned short TADCOBRA;
+ unsigned short TADCOBRB;
+ char wk11[72];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char NFDEN:1;
+ unsigned char NFCEN:1;
+ unsigned char NFBEN:1;
+ unsigned char NFAEN:1;
+ } BIT;
+ } NFCR;
+};
+
+struct st_mtu5 {
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char NFCS:2;
+ unsigned char :1;
+ unsigned char NFWEN:1;
+ unsigned char NFVEN:1;
+ unsigned char NFUEN:1;
+ } BIT;
+ } NFCR;
+ char wk1[490];
+ unsigned short TCNTU;
+ unsigned short TGRU;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRU;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORU;
+ char wk3[9];
+ unsigned short TCNTV;
+ unsigned short TGRV;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRV;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORV;
+ char wk5[9];
+ unsigned short TCNTW;
+ unsigned short TGRW;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char TPSC:2;
+ } BIT;
+ } TCRW;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char IOC:5;
+ } BIT;
+ } TIORW;
+ char wk7[11];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char TGIE5U:1;
+ unsigned char TGIE5V:1;
+ unsigned char TGIE5W:1;
+ } BIT;
+ } TIER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char CSTU5:1;
+ unsigned char CSTV5:1;
+ unsigned char CSTW5:1;
+ } BIT;
+ } TSTR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char CMPCLR5U:1;
+ unsigned char CMPCLR5V:1;
+ unsigned char CMPCLR5W:1;
+ } BIT;
+ } TCNTCMPCLR;
+};
+
+struct st_poe {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char POE3F:1;
+ unsigned char POE2F:1;
+ unsigned char POE1F:1;
+ unsigned char POE0F:1;
+ unsigned char :3;
+ unsigned char PIE1:1;
+ unsigned char POE3M:2;
+ unsigned char POE2M:2;
+ unsigned char POE1M:2;
+ unsigned char POE0M:2;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char OSF1:1;
+ unsigned char :5;
+ unsigned char OCE1:1;
+ unsigned char OIE1:1;
+ } BIT;
+ } OCSR1;
+ char wk0[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char POE8F:1;
+ unsigned char :2;
+ unsigned char POE8E:1;
+ unsigned char PIE2:1;
+ unsigned char :6;
+ unsigned char POE8M:2;
+ } BIT;
+ } ICSR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char CH0HIZ:1;
+ unsigned char CH34HIZ:1;
+ } BIT;
+ } SPOER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PE3ZE:1;
+ unsigned char PE2ZE:1;
+ unsigned char PE1ZE:1;
+ unsigned char PE0ZE:1;
+ } BIT;
+ } POECR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char P1CZEA:1;
+ unsigned char P2CZEA:1;
+ unsigned char P3CZEA:1;
+ } BIT;
+ } POECR2;
+ char wk1[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char H;
+ unsigned char L;
+ } BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char OSTSTF:1;
+ unsigned char :2;
+ unsigned char OSTSTE:1;
+ } BIT;
+ } ICSR3;
+};
+
+struct st_port {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char PSEL5:1;
+ unsigned char :1;
+ unsigned char PSEL3:1;
+ unsigned char :1;
+ unsigned char PSEL1:1;
+ unsigned char PSEL0:1;
+ } BIT;
+ } PSRB;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PSEL7:1;
+ unsigned char PSEL6:1;
+ } BIT;
+ } PSRA;
+};
+
+struct st_port0 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PMR;
+ char wk3[33];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[61];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port2 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ } BIT;
+ } ODR1;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port3 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char :2;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[34];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ char wk4[60];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_port4 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+};
+
+struct st_port5 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PMR;
+ char wk3[95];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porta {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[41];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :3;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char B4:1;
+ unsigned char :3;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[52];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[42];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :3;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ } BIT;
+ } ODR1;
+ char wk4[51];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char :1;
+ unsigned char B3:1;
+ unsigned char :1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_portc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PMR;
+ char wk3[43];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[50];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_porte {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PDR;
+ char wk0[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PODR;
+ char wk1[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PIDR;
+ char wk2[31];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PMR;
+ char wk3[45];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char B6:1;
+ unsigned char :1;
+ unsigned char B4:1;
+ unsigned char :1;
+ unsigned char B2:1;
+ unsigned char :1;
+ unsigned char B0:1;
+ } BIT;
+ } ODR1;
+ char wk4[48];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char B7:1;
+ unsigned char B6:1;
+ unsigned char B5:1;
+ unsigned char B4:1;
+ unsigned char B3:1;
+ unsigned char B2:1;
+ unsigned char B1:1;
+ unsigned char B0:1;
+ } BIT;
+ } PCR;
+};
+
+struct st_riic {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ICE:1;
+ unsigned char IICRST:1;
+ unsigned char CLO:1;
+ unsigned char SOWP:1;
+ unsigned char SCLO:1;
+ unsigned char SDAO:1;
+ unsigned char SCLI:1;
+ unsigned char SDAI:1;
+ } BIT;
+ } ICCR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BBSY:1;
+ unsigned char MST:1;
+ unsigned char TRS:1;
+ unsigned char :1;
+ unsigned char SP:1;
+ unsigned char RS:1;
+ unsigned char ST:1;
+ } BIT;
+ } ICCR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char MTWP:1;
+ unsigned char CKS:3;
+ unsigned char BCWP:1;
+ unsigned char BC:3;
+ } BIT;
+ } ICMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char DLCS:1;
+ unsigned char SDDL:3;
+ unsigned char TMWE:1;
+ unsigned char TMOH:1;
+ unsigned char TMOL:1;
+ unsigned char TMOS:1;
+ } BIT;
+ } ICMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SMBS:1;
+ unsigned char WAIT:1;
+ unsigned char RDRFS:1;
+ unsigned char ACKWP:1;
+ unsigned char ACKBT:1;
+ unsigned char ACKBR:1;
+ unsigned char NF:2;
+ } BIT;
+ } ICMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SCLE:1;
+ unsigned char NFE:1;
+ unsigned char NACKE:1;
+ unsigned char SALE:1;
+ unsigned char NALE:1;
+ unsigned char MALE:1;
+ unsigned char TMOE:1;
+ } BIT;
+ } ICFER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HOAE:1;
+ unsigned char :1;
+ unsigned char DIDE:1;
+ unsigned char :1;
+ unsigned char GCAE:1;
+ unsigned char SAR2E:1;
+ unsigned char SAR1E:1;
+ unsigned char SAR0E:1;
+ } BIT;
+ } ICSER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char TEIE:1;
+ unsigned char RIE:1;
+ unsigned char NAKIE:1;
+ unsigned char SPIE:1;
+ unsigned char STIE:1;
+ unsigned char ALIE:1;
+ unsigned char TMOIE:1;
+ } BIT;
+ } ICIER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char HOA:1;
+ unsigned char :1;
+ unsigned char DID:1;
+ unsigned char :1;
+ unsigned char GCA:1;
+ unsigned char AAS2:1;
+ unsigned char AAS1:1;
+ unsigned char AAS0:1;
+ } BIT;
+ } ICSR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TDRE:1;
+ unsigned char TEND:1;
+ unsigned char RDRF:1;
+ unsigned char NACKF:1;
+ unsigned char STOP:1;
+ unsigned char START:1;
+ unsigned char AL:1;
+ unsigned char TMOF:1;
+ } BIT;
+ } ICSR2;
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTL;
+ };
+ union {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU0;
+ union {
+ unsigned char BYTE;
+ } TMOCNTH;
+ };
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SVA:7;
+ unsigned char SVA0:1;
+ } BIT;
+ } SARL2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SVA:2;
+ unsigned char FS:1;
+ } BIT;
+ } SARU2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char BRL:5;
+ } BIT;
+ } ICBRL;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char BRH:5;
+ } BIT;
+ } ICBRH;
+ unsigned char ICDRT;
+ unsigned char ICDRR;
+};
+
+struct st_rspi {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char SPRIE:1;
+ unsigned char SPE:1;
+ unsigned char SPTIE:1;
+ unsigned char SPEIE:1;
+ unsigned char MSTR:1;
+ unsigned char MODFEN:1;
+ unsigned char TXMD:1;
+ unsigned char SPMS:1;
+ } BIT;
+ } SPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char SSL3P:1;
+ unsigned char SSL2P:1;
+ unsigned char SSL1P:1;
+ unsigned char SSL0P:1;
+ } BIT;
+ } SSLP;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char MOIFE:1;
+ unsigned char MOIFV:1;
+ unsigned char :2;
+ unsigned char SPLP2:1;
+ unsigned char SPLP:1;
+ } BIT;
+ } SPPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PERF:1;
+ unsigned char MODF:1;
+ unsigned char IDLNF:1;
+ unsigned char OVRF:1;
+ } BIT;
+ } SPSR;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned short H;
+ } WORD;
+ } SPDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SPSLN:3;
+ } BIT;
+ } SPSCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SPECM:3;
+ unsigned char :1;
+ unsigned char SPCP:3;
+ } BIT;
+ } SPSSR;
+ unsigned char SPBR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char SPLW:1;
+ unsigned char SPRDTD:1;
+ unsigned char :2;
+ unsigned char SPFC:2;
+ } BIT;
+ } SPDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SCKDL:3;
+ } BIT;
+ } SPCKD;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SLNDL:3;
+ } BIT;
+ } SSLND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SPNDL:3;
+ } BIT;
+ } SPND;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char PTE:1;
+ unsigned char SPIIE:1;
+ unsigned char SPOE:1;
+ unsigned char SPPE:1;
+ } BIT;
+ } SPCR2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD5;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD6;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SCKDEN:1;
+ unsigned short SLNDEN:1;
+ unsigned short SPNDEN:1;
+ unsigned short LSBF:1;
+ unsigned short SPB:4;
+ unsigned short SSLKP:1;
+ unsigned short SSLA:3;
+ unsigned short BRDV:2;
+ unsigned short CPOL:1;
+ unsigned short CPHA:1;
+ } BIT;
+ } SPCMD7;
+};
+
+struct st_rtc {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char F1HZ:1;
+ unsigned char F2HZ:1;
+ unsigned char F4HZ:1;
+ unsigned char F8HZ:1;
+ unsigned char F16HZ:1;
+ unsigned char F32HZ:1;
+ unsigned char F64HZ:1;
+ } BIT;
+ } R64CNT;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char SEC10:3;
+ unsigned char SEC1:4;
+ } BIT;
+ } RSECCNT;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MIN10:3;
+ unsigned char MIN1:4;
+ } BIT;
+ } RMINCNT;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char PM:1;
+ unsigned char HR10:2;
+ unsigned char HR1:4;
+ } BIT;
+ } RHRCNT;
+ char wk3[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char DAYW:3;
+ } BIT;
+ } RWKCNT;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char DATE10:2;
+ unsigned char DATE1:4;
+ } BIT;
+ } RDAYCNT;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char MON10:1;
+ unsigned char MON1:4;
+ } BIT;
+ } RMONCNT;
+ char wk6[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short YR10:4;
+ unsigned short YR1:4;
+ } BIT;
+ } RYRCNT;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char SEC10:3;
+ unsigned char SEC1:4;
+ } BIT;
+ } RSECAR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char MIN10:3;
+ unsigned char MIN1:4;
+ } BIT;
+ } RMINAR;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char PM:1;
+ unsigned char HR10:2;
+ unsigned char HR1:4;
+ } BIT;
+ } RHRAR;
+ char wk9[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :4;
+ unsigned char DAYW:3;
+ } BIT;
+ } RWKAR;
+ char wk10[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :1;
+ unsigned char DATE10:2;
+ unsigned char DATE1:4;
+ } BIT;
+ } RDAYAR;
+ char wk11[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ unsigned char :2;
+ unsigned char MON10:1;
+ unsigned char MON1:4;
+ } BIT;
+ } RMONAR;
+ char wk12[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short YR10:4;
+ unsigned short YR1:4;
+ } BIT;
+ } RYRAR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:1;
+ } BIT;
+ } RYRAREN;
+ char wk13[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PES:4;
+ unsigned char RTCOS:1;
+ unsigned char PIE:1;
+ unsigned char CIE:1;
+ unsigned char AIE:1;
+ } BIT;
+ } RCR1;
+ char wk14[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CNTMD:1;
+ unsigned char HR24:1;
+ unsigned char AADJP:1;
+ unsigned char AADJE:1;
+ unsigned char RTCOE:1;
+ unsigned char ADJ30:1;
+ unsigned char RESET:1;
+ unsigned char START:1;
+ } BIT;
+ } RCR2;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char RTCDV:2;
+ unsigned char RTCEN:1;
+ } BIT;
+ } RCR3;
+ char wk16[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PMADJ:2;
+ unsigned char ADJ:6;
+ } BIT;
+ } RADJ;
+};
+
+struct st_rtcb {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT0;
+ char wk0[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT1;
+ char wk1[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT2;
+ char wk2[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNT:8;
+ } BIT;
+ } BCNT3;
+ char wk3[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT0AR;
+ char wk4[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT1AR;
+ char wk5[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT2AR;
+ char wk6[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCNTAR:8;
+ } BIT;
+ } BCNT3AR;
+ char wk7[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT0AER;
+ char wk8[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT1AER;
+ char wk9[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short ENB:8;
+ } BIT;
+ } BCNT2AER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char ENB:8;
+ } BIT;
+ } BCNT3AER;
+};
+
+struct st_s12ad {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADST:1;
+ unsigned short ADCS:2;
+ unsigned short ADIE:1;
+ unsigned short :1;
+ unsigned short ADHSC:1;
+ unsigned short TRGE:1;
+ unsigned short EXTRG:1;
+ unsigned short DBLE:1;
+ unsigned short GBADIE:1;
+ unsigned short :1;
+ unsigned short DBLANS:5;
+ } BIT;
+ } ADCSR;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSA15:1;
+ unsigned short ANSA14:1;
+ unsigned short ANSA13:1;
+ unsigned short ANSA12:1;
+ unsigned short ANSA11:1;
+ unsigned short ANSA10:1;
+ unsigned short ANSA9:1;
+ unsigned short ANSA8:1;
+ unsigned short :1;
+ unsigned short ANSA6:1;
+ unsigned short :1;
+ unsigned short ANSA4:1;
+ unsigned short ANSA3:1;
+ unsigned short ANSA2:1;
+ unsigned short ANSA1:1;
+ unsigned short ANSA0:1;
+ } BIT;
+ } ADANSA;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADS15:1;
+ unsigned short ADS14:1;
+ unsigned short ADS13:1;
+ unsigned short ADS12:1;
+ unsigned short ADS11:1;
+ unsigned short ADS10:1;
+ unsigned short ADS9:1;
+ unsigned short ADS8:1;
+ unsigned short :1;
+ unsigned short ADS6:1;
+ unsigned short :1;
+ unsigned short ADS4:1;
+ unsigned short ADS3:1;
+ unsigned short ADS2:1;
+ unsigned short ADS1:1;
+ unsigned short ADS0:1;
+ } BIT;
+ } ADADS;
+ char wk2[2];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char ADC:2;
+ } BIT;
+ } ADADC;
+ char wk3[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ADRFMT:1;
+ unsigned short :9;
+ unsigned short ACE:1;
+ } BIT;
+ } ADCER;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short TRSA:4;
+ unsigned short :4;
+ unsigned short TRSB:4;
+ } BIT;
+ } ADSTRGR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short OCS:1;
+ unsigned short TSS:1;
+ unsigned short :6;
+ unsigned short OCSAD:1;
+ } BIT;
+ } ADEXICR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short ANSB15:1;
+ unsigned short ANSB14:1;
+ unsigned short ANSB13:1;
+ unsigned short ANSB12:1;
+ unsigned short ANSB11:1;
+ unsigned short ANSB10:1;
+ unsigned short ANSB9:1;
+ unsigned short ANSB8:1;
+ unsigned short :1;
+ unsigned short ANSB6:1;
+ unsigned short :1;
+ unsigned short ANSB4:1;
+ unsigned short ANSB3:1;
+ unsigned short ANSB2:1;
+ unsigned short ANSB1:1;
+ unsigned short ANSB0:1;
+ } BIT;
+ } ADANSB;
+ char wk4[2];
+ unsigned short ADDBLDR;
+ unsigned short ADTSDR;
+ unsigned short ADOCDR;
+ char wk5[2];
+ unsigned short ADDR0;
+ unsigned short ADDR1;
+ unsigned short ADDR2;
+ unsigned short ADDR3;
+ unsigned short ADDR4;
+ char wk6[2];
+ unsigned short ADDR6;
+ char wk7[2];
+ unsigned short ADDR8;
+ unsigned short ADDR9;
+ unsigned short ADDR10;
+ unsigned short ADDR11;
+ unsigned short ADDR12;
+ unsigned short ADDR13;
+ unsigned short ADDR14;
+ unsigned short ADDR15;
+ char wk8[32];
+ unsigned char ADSSTR0;
+ unsigned char ADSSTRL;
+ char wk9[14];
+ unsigned char ADSSTRT;
+ unsigned char ADSSTRO;
+ char wk10[1];
+ unsigned char ADSSTR1;
+ unsigned char ADSSTR2;
+ unsigned char ADSSTR3;
+ unsigned char ADSSTR4;
+ char wk11[1];
+ unsigned char ADSSTR6;
+};
+
+struct st_sci1 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CM:1;
+ unsigned char CHR:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char STOP:1;
+ unsigned char MP:1;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char FER:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RXDESEL:1;
+ unsigned char :1;
+ unsigned char NFEN:1;
+ unsigned char ABCS:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char NFCS:3;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICDL:5;
+ unsigned char :2;
+ unsigned char IICM:1;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char IICACKT:1;
+ unsigned char :3;
+ unsigned char IICCSC:1;
+ unsigned char IICINTM:1;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSCLS:2;
+ unsigned char IICSDAS:2;
+ unsigned char IICSTIF:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTAREQ:1;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IICACKR:1;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKPH:1;
+ unsigned char CKPOL:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char MSS:1;
+ unsigned char CTSE:1;
+ unsigned char SSE:1;
+ } BIT;
+ } SPMR;
+};
+
+struct st_sci12 {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CM:1;
+ unsigned char CHR:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char STOP:1;
+ unsigned char MP:1;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char FER:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RXDESEL:1;
+ unsigned char :1;
+ unsigned char NFEN:1;
+ unsigned char ABCS:1;
+ } BIT;
+ } SEMR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char NFCS:3;
+ } BIT;
+ } SNFR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICDL:5;
+ unsigned char :2;
+ unsigned char IICM:1;
+ } BIT;
+ } SIMR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char IICACKT:1;
+ unsigned char :3;
+ unsigned char IICCSC:1;
+ unsigned char IICINTM:1;
+ } BIT;
+ } SIMR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char IICSCLS:2;
+ unsigned char IICSDAS:2;
+ unsigned char IICSTIF:1;
+ unsigned char IICSTPREQ:1;
+ unsigned char IICRSTAREQ:1;
+ unsigned char IICSTAREQ:1;
+ } BIT;
+ } SIMR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char IICACKR:1;
+ } BIT;
+ } SISR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CKPH:1;
+ unsigned char CKPOL:1;
+ unsigned char :1;
+ unsigned char MFF:1;
+ unsigned char :1;
+ unsigned char MSS:1;
+ unsigned char CTSE:1;
+ unsigned char SSE:1;
+ } BIT;
+ } SPMR;
+ char wk0[18];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ESME:1;
+ } BIT;
+ } ESMER;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char BRME:1;
+ unsigned char RXDSF:1;
+ unsigned char SFSF:1;
+ } BIT;
+ } CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char PIBS:3;
+ unsigned char PIBE:1;
+ unsigned char CF1DS:2;
+ unsigned char CF0RE:1;
+ unsigned char BFE:1;
+ } BIT;
+ } CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RTS:2;
+ unsigned char BCCS:2;
+ unsigned char :1;
+ unsigned char DFCS:3;
+ } BIT;
+ } CR2;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SDST:1;
+ } BIT;
+ } CR3;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char SHARPS:1;
+ unsigned char :2;
+ unsigned char RXDXPS:1;
+ unsigned char TXDXPS:1;
+ } BIT;
+ } PCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDIE:1;
+ unsigned char BCDIE:1;
+ unsigned char PIBDIE:1;
+ unsigned char CF1MIE:1;
+ unsigned char CF0MIE:1;
+ unsigned char BFDIE:1;
+ } BIT;
+ } ICR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDF:1;
+ unsigned char BCDF:1;
+ unsigned char PIBDF:1;
+ unsigned char CF1MF:1;
+ unsigned char CF0MF:1;
+ unsigned char BFDF:1;
+ } BIT;
+ } STR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char AEDCL:1;
+ unsigned char BCDCL:1;
+ unsigned char PIBDCL:1;
+ unsigned char CF1MCL:1;
+ unsigned char CF0MCL:1;
+ unsigned char BFDCL:1;
+ } BIT;
+ } STCR;
+ unsigned char CF0DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF0CE7:1;
+ unsigned char CF0CE6:1;
+ unsigned char CF0CE5:1;
+ unsigned char CF0CE4:1;
+ unsigned char CF0CE3:1;
+ unsigned char CF0CE2:1;
+ unsigned char CF0CE1:1;
+ unsigned char CF0CE0:1;
+ } BIT;
+ } CF0CR;
+ unsigned char CF0RR;
+ unsigned char PCF1DR;
+ unsigned char SCF1DR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char CF1CE7:1;
+ unsigned char CF1CE6:1;
+ unsigned char CF1CE5:1;
+ unsigned char CF1CE4:1;
+ unsigned char CF1CE3:1;
+ unsigned char CF1CE2:1;
+ unsigned char CF1CE1:1;
+ unsigned char CF1CE0:1;
+ } BIT;
+ } CF1CR;
+ unsigned char CF1RR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char TCST:1;
+ } BIT;
+ } TCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char TCSS:3;
+ unsigned char TWRC:1;
+ unsigned char :1;
+ unsigned char TOMS:2;
+ } BIT;
+ } TMR;
+ unsigned char TPRE;
+ unsigned char TCNT;
+};
+
+struct st_smci {
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char GM:1;
+ unsigned char BLK:1;
+ unsigned char PE:1;
+ unsigned char PM:1;
+ unsigned char BCP:2;
+ unsigned char CKS:2;
+ } BIT;
+ } SMR;
+ unsigned char BRR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char TIE:1;
+ unsigned char RIE:1;
+ unsigned char TE:1;
+ unsigned char RE:1;
+ unsigned char MPIE:1;
+ unsigned char TEIE:1;
+ unsigned char CKE:2;
+ } BIT;
+ } SCR;
+ unsigned char TDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char ORER:1;
+ unsigned char ERS:1;
+ unsigned char PER:1;
+ unsigned char TEND:1;
+ unsigned char MPB:1;
+ unsigned char MPBT:1;
+ } BIT;
+ } SSR;
+ unsigned char RDR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char BCP2:1;
+ unsigned char :3;
+ unsigned char SDIR:1;
+ unsigned char SINV:1;
+ unsigned char :1;
+ unsigned char SMIF:1;
+ } BIT;
+ } SCMR;
+};
+
+struct st_system {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short MD:1;
+ } BIT;
+ } MDMONR;
+ char wk0[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :15;
+ unsigned short RAME:1;
+ } BIT;
+ } SYSCR1;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short SSBY:1;
+ } BIT;
+ } SBYCR;
+ char wk2[2];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :3;
+ unsigned long MSTPA28:1;
+ unsigned long :8;
+ unsigned long MSTPA19:1;
+ unsigned long :1;
+ unsigned long MSTPA17:1;
+ unsigned long :1;
+ unsigned long MSTPA15:1;
+ unsigned long :5;
+ unsigned long MSTPA9:1;
+ } BIT;
+ } MSTPCRA;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long :1;
+ unsigned long MSTPB30:1;
+ unsigned long :3;
+ unsigned long MSTPB26:1;
+ unsigned long :2;
+ unsigned long MSTPB23:1;
+ unsigned long :1;
+ unsigned long MSTPB21:1;
+ unsigned long :1;
+ unsigned long MSTPB19:1;
+ unsigned long :1;
+ unsigned long MSTPB17:1;
+ unsigned long :7;
+ unsigned long MSTPB9:1;
+ unsigned long :2;
+ unsigned long MSTPB6:1;
+ unsigned long :1;
+ unsigned long MSTPB4:1;
+ } BIT;
+ } MSTPCRB;
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long DSLPE:1;
+ unsigned long :11;
+ unsigned long MSTPC19:1;
+ unsigned long :18;
+ unsigned long MSTPC0:1;
+ } BIT;
+ } MSTPCRC;
+ char wk3[4];
+ union {
+ unsigned long LONG;
+ struct {
+ unsigned long FCK:4;
+ unsigned long ICK:4;
+ unsigned long :12;
+ unsigned long PCKB:4;
+ unsigned long :4;
+ unsigned long PCKD:4;
+ } BIT;
+ } SCKCR;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :5;
+ unsigned short CKSEL:3;
+ } BIT;
+ } SCKCR3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :2;
+ unsigned short STC:6;
+ unsigned short :6;
+ unsigned short PLIDIV:2;
+ } BIT;
+ } PLLCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char PLLEN:1;
+ } BIT;
+ } PLLCR2;
+ char wk5[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char MOSTP:1;
+ } BIT;
+ } MOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char SOSTP:1;
+ } BIT;
+ } SOSCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char LCSTP:1;
+ } BIT;
+ } LOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char ILCSTP:1;
+ } BIT;
+ } ILOCOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char HCSTP:1;
+ } BIT;
+ } HOCOCR;
+ char wk6[5];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char HCOVF:1;
+ unsigned char PLOVF:1;
+ unsigned char :1;
+ unsigned char MOOVF:1;
+ } BIT;
+ } OSCOVFSR;
+ char wk7[1];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short CKOSTP:1;
+ unsigned short CKODIV:3;
+ unsigned short :1;
+ unsigned short CKOSEL:3;
+ } BIT;
+ } CKOCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char OSTDE:1;
+ unsigned char :6;
+ unsigned char OSTDIE:1;
+ } BIT;
+ } OSTDCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char OSTDF:1;
+ } BIT;
+ } OSTDSR;
+ char wk8[94];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char OPCMTSF:1;
+ unsigned char :1;
+ unsigned char OPCM:3;
+ } BIT;
+ } OPCCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char RSTCKEN:1;
+ unsigned char :4;
+ unsigned char RSTCKSEL:3;
+ } BIT;
+ } RSTCKCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char MSTS:5;
+ } BIT;
+ } MOSCWTCR;
+ char wk9[7];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :3;
+ unsigned char SOPCMTSF:1;
+ unsigned char :3;
+ unsigned char SOPCM:1;
+ } BIT;
+ } SOPCCR;
+ char wk10[21];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char SWRF:1;
+ unsigned char :1;
+ unsigned char IWDTRF:1;
+ } BIT;
+ } RSTSR2;
+ char wk11[1];
+ unsigned short SWRR;
+ char wk12[28];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char LVD1IRQSEL:1;
+ unsigned char LVD1IDTSEL:2;
+ } BIT;
+ } LVD1CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char LVD1MON:1;
+ unsigned char LVD1DET:1;
+ } BIT;
+ } LVD1SR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :5;
+ unsigned char LVD2IRQSEL:1;
+ unsigned char LVD2IDTSEL:2;
+ } BIT;
+ } LVD2CR1;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :6;
+ unsigned char LVD2MON:1;
+ unsigned char LVD2DET:1;
+ } BIT;
+ } LVD2SR;
+ char wk13[794];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short PRKEY:8;
+ unsigned short :4;
+ unsigned short PRC3:1;
+ unsigned short :1;
+ unsigned short PRC1:1;
+ unsigned short PRC0:1;
+ } BIT;
+ } PRCR;
+ char wk14[48784];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :4;
+ unsigned char LVD2RF:1;
+ unsigned char LVD1RF:1;
+ unsigned char :1;
+ unsigned char PORF:1;
+ } BIT;
+ } RSTSR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :7;
+ unsigned char CWSF:1;
+ } BIT;
+ } RSTSR1;
+ char wk15[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char MOSEL:1;
+ unsigned char MODRV21:1;
+ } BIT;
+ } MOFCR;
+ char wk16[3];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :1;
+ unsigned char LVD2E:1;
+ unsigned char LVD1E:1;
+ unsigned char :1;
+ unsigned char EXVCCINP2:1;
+ } BIT;
+ } LVCMPCR;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char :2;
+ unsigned char LVD2LVL:2;
+ unsigned char LVD1LVL:4;
+ } BIT;
+ } LVDLVLR;
+ char wk17[1];
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD1RN:1;
+ unsigned char LVD1RI:1;
+ unsigned char :3;
+ unsigned char LVD1CMPE:1;
+ unsigned char :1;
+ unsigned char LVD1RIE:1;
+ } BIT;
+ } LVD1CR0;
+ union {
+ unsigned char BYTE;
+ struct {
+ unsigned char LVD2RN:1;
+ unsigned char LVD2RI:1;
+ unsigned char :3;
+ unsigned char LVD2CMPE:1;
+ unsigned char :1;
+ unsigned char LVD2RIE:1;
+ } BIT;
+ } LVD2CR0;
+};
+
+struct st_usb {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :5;
+ unsigned short SCKE:1;
+ unsigned short :1;
+ unsigned short CNEN:1;
+ unsigned short :1;
+ unsigned short DCFM:1;
+ unsigned short DRPD:1;
+ unsigned short DPRPU:1;
+ unsigned short :3;
+ unsigned short USBE:1;
+ } BIT;
+ } SYSCFG;
+ char wk0[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVCMON:2;
+ unsigned short :7;
+ unsigned short HTACT:1;
+ unsigned short :3;
+ unsigned short IDMON:1;
+ unsigned short LNST:2;
+ } BIT;
+ } SYSSTS0;
+ char wk1[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :4;
+ unsigned short HNPBTOA:1;
+ unsigned short EXICEN:1;
+ unsigned short VBUSEN:1;
+ unsigned short WKUP:1;
+ unsigned short RWUPE:1;
+ unsigned short USBRST:1;
+ unsigned short RESUME:1;
+ unsigned short UACT:1;
+ unsigned short :1;
+ unsigned short RHST:3;
+ } BIT;
+ } DVSTCTR0;
+ char wk2[10];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } CFIFO;
+ char wk3[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D0FIFO;
+ char wk4[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned char L;
+ unsigned char H;
+ } BYTE;
+ } D1FIFO;
+ char wk5[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short :3;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :2;
+ unsigned short ISEL:1;
+ unsigned short :1;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } CFIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } CFIFOCTR;
+ char wk6[4];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short DCLRM:1;
+ unsigned short DREQE:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :4;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } D0FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } D0FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short RCNT:1;
+ unsigned short REW:1;
+ unsigned short DCLRM:1;
+ unsigned short DREQE:1;
+ unsigned short :1;
+ unsigned short MBW:1;
+ unsigned short :1;
+ unsigned short BIGEND:1;
+ unsigned short :4;
+ unsigned short CURPIPE:4;
+ } BIT;
+ } D1FIFOSEL;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BVAL:1;
+ unsigned short BCLR:1;
+ unsigned short FRDY:1;
+ unsigned short :4;
+ unsigned short DTLN:9;
+ } BIT;
+ } D1FIFOCTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VBSE:1;
+ unsigned short RSME:1;
+ unsigned short SOFE:1;
+ unsigned short DVSE:1;
+ unsigned short CTRE:1;
+ unsigned short BEMPE:1;
+ unsigned short NRDYE:1;
+ unsigned short BRDYE:1;
+ } BIT;
+ } INTENB0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRCRE:1;
+ unsigned short BCHGE:1;
+ unsigned short :1;
+ unsigned short DTCHE:1;
+ unsigned short ATTCHE:1;
+ unsigned short :4;
+ unsigned short EOFERRE:1;
+ unsigned short SIGNE:1;
+ unsigned short SACKE:1;
+ unsigned short :3;
+ unsigned short PDDETINTE0:1;
+ } BIT;
+ } INTENB1;
+ char wk7[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BRDYE:1;
+ unsigned short PIPE8BRDYE:1;
+ unsigned short PIPE7BRDYE:1;
+ unsigned short PIPE6BRDYE:1;
+ unsigned short PIPE5BRDYE:1;
+ unsigned short PIPE4BRDYE:1;
+ unsigned short PIPE3BRDYE:1;
+ unsigned short PIPE2BRDYE:1;
+ unsigned short PIPE1BRDYE:1;
+ unsigned short PIPE0BRDYE:1;
+ } BIT;
+ } BRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9NRDYE:1;
+ unsigned short PIPE8NRDYE:1;
+ unsigned short PIPE7NRDYE:1;
+ unsigned short PIPE6NRDYE:1;
+ unsigned short PIPE5NRDYE:1;
+ unsigned short PIPE4NRDYE:1;
+ unsigned short PIPE3NRDYE:1;
+ unsigned short PIPE2NRDYE:1;
+ unsigned short PIPE1NRDYE:1;
+ unsigned short PIPE0NRDYE:1;
+ } BIT;
+ } NRDYENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BEMPE:1;
+ unsigned short PIPE8BEMPE:1;
+ unsigned short PIPE7BEMPE:1;
+ unsigned short PIPE6BEMPE:1;
+ unsigned short PIPE5BEMPE:1;
+ unsigned short PIPE4BEMPE:1;
+ unsigned short PIPE3BEMPE:1;
+ unsigned short PIPE2BEMPE:1;
+ unsigned short PIPE1BEMPE:1;
+ unsigned short PIPE0BEMPE:1;
+ } BIT;
+ } BEMPENB;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :7;
+ unsigned short TRNENSEL:1;
+ unsigned short :1;
+ unsigned short BRDYM:1;
+ unsigned short :1;
+ unsigned short EDGESTS:1;
+ } BIT;
+ } SOFCFG;
+ char wk8[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short VBINT:1;
+ unsigned short RESM:1;
+ unsigned short SOFR:1;
+ unsigned short DVST:1;
+ unsigned short CTRT:1;
+ unsigned short BEMP:1;
+ unsigned short NRDY:1;
+ unsigned short BRDY:1;
+ unsigned short VBSTS:1;
+ unsigned short DVSQ:3;
+ unsigned short VALID:1;
+ unsigned short CTSQ:3;
+ } BIT;
+ } INTSTS0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRCR:1;
+ unsigned short BCHG:1;
+ unsigned short :1;
+ unsigned short DTCH:1;
+ unsigned short ATTCH:1;
+ unsigned short :4;
+ unsigned short EOFERR:1;
+ unsigned short SIGN:1;
+ unsigned short SACK:1;
+ unsigned short :3;
+ unsigned short PDDETINT0:1;
+ } BIT;
+ } INTSTS1;
+ char wk9[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BRDY:1;
+ unsigned short PIPE8BRDY:1;
+ unsigned short PIPE7BRDY:1;
+ unsigned short PIPE6BRDY:1;
+ unsigned short PIPE5BRDY:1;
+ unsigned short PIPE4BRDY:1;
+ unsigned short PIPE3BRDY:1;
+ unsigned short PIPE2BRDY:1;
+ unsigned short PIPE1BRDY:1;
+ unsigned short PIPE0BRDY:1;
+ } BIT;
+ } BRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9NRDY:1;
+ unsigned short PIPE8NRDY:1;
+ unsigned short PIPE7NRDY:1;
+ unsigned short PIPE6NRDY:1;
+ unsigned short PIPE5NRDY:1;
+ unsigned short PIPE4NRDY:1;
+ unsigned short PIPE3NRDY:1;
+ unsigned short PIPE2NRDY:1;
+ unsigned short PIPE1NRDY:1;
+ unsigned short PIPE0NRDY:1;
+ } BIT;
+ } NRDYSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PIPE9BEMP:1;
+ unsigned short PIPE8BEMP:1;
+ unsigned short PIPE7BEMP:1;
+ unsigned short PIPE6BEMP:1;
+ unsigned short PIPE5BEMP:1;
+ unsigned short PIPE4BEMP:1;
+ unsigned short PIPE3BEMP:1;
+ unsigned short PIPE2BEMP:1;
+ unsigned short PIPE1BEMP:1;
+ unsigned short PIPE0BEMP:1;
+ } BIT;
+ } BEMPSTS;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short OVRN:1;
+ unsigned short CRCE:1;
+ unsigned short :3;
+ unsigned short FRNM:11;
+ } BIT;
+ } FRMNUM;
+ char wk10[6];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BREQUEST:8;
+ unsigned short BMREQUESTTYPE:8;
+ } BIT;
+ } USBREQ;
+ unsigned short USBVAL;
+ unsigned short USBINDX;
+ unsigned short USBLENG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short SHTNAK:1;
+ unsigned short :2;
+ unsigned short DIR:1;
+ } BIT;
+ } DCPCFG;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DEVSEL:4;
+ unsigned short :5;
+ unsigned short MXPS:7;
+ } BIT;
+ } DCPMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short SUREQ:1;
+ unsigned short :2;
+ unsigned short SUREQCLR:1;
+ unsigned short :2;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :2;
+ unsigned short CCPL:1;
+ unsigned short PID:2;
+ } BIT;
+ } DCPCTR;
+ char wk11[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :12;
+ unsigned short PIPESEL:4;
+ } BIT;
+ } PIPESEL;
+ char wk12[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short TYPE:2;
+ unsigned short :3;
+ unsigned short BFRE:1;
+ unsigned short DBLB:1;
+ unsigned short :1;
+ unsigned short SHTNAK:1;
+ unsigned short :2;
+ unsigned short DIR:1;
+ unsigned short EPNUM:4;
+ } BIT;
+ } PIPECFG;
+ char wk13[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short DEVSEL:4;
+ unsigned short :3;
+ unsigned short MXPS:9;
+ } BIT;
+ } PIPEMAXP;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :3;
+ unsigned short IFIS:1;
+ unsigned short :9;
+ unsigned short IITV:3;
+ } BIT;
+ } PIPEPERI;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE1CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE2CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE3CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE4CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short INBUFM:1;
+ unsigned short :3;
+ unsigned short ATREPM:1;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE5CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE6CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE7CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE8CTR;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short BSTS:1;
+ unsigned short :5;
+ unsigned short ACLRM:1;
+ unsigned short SQCLR:1;
+ unsigned short SQSET:1;
+ unsigned short SQMON:1;
+ unsigned short PBUSY:1;
+ unsigned short :3;
+ unsigned short PID:2;
+ } BIT;
+ } PIPE9CTR;
+ char wk14[14];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE1TRE;
+ unsigned short PIPE1TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE2TRE;
+ unsigned short PIPE2TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE3TRE;
+ unsigned short PIPE3TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE4TRE;
+ unsigned short PIPE4TRN;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short TRENB:1;
+ unsigned short TRCLR:1;
+ } BIT;
+ } PIPE5TRE;
+ unsigned short PIPE5TRN;
+ char wk15[12];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :6;
+ unsigned short PDDETSTS0:1;
+ unsigned short CHGDETSTS0:1;
+ unsigned short BATCHGE0:1;
+ unsigned short DCPMODE0:1;
+ unsigned short VDMSRCE0:1;
+ unsigned short IDPSINKE0:1;
+ unsigned short VDPSRCE0:1;
+ unsigned short IDMSINKE0:1;
+ unsigned short IDPSRCE0:1;
+ unsigned short RPDME0:1;
+ } BIT;
+ } USBBCCTRL0;
+ char wk16[26];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short VBRPDCUT:1;
+ unsigned short :6;
+ unsigned short VDDUSBE:1;
+ } BIT;
+ } USBMC;
+ char wk17[2];
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD0;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD1;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD2;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD3;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD4;
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short :8;
+ unsigned short USBSPD:2;
+ } BIT;
+ } DEVADD5;
+};
+
+enum enum_ir {
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,
+IR_CMT0_CMI0,
+IR_CMT1_CMI1,
+IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF,
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,
+IR_DOC_DOPCF=57,
+IR_RTC_CUP=63,
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,
+IR_LVD_LVD1=88,IR_LVD_LVD2,
+IR_USB0_USBR0,
+IR_RTC_ALM=92,IR_RTC_PRD,
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,
+IR_ELC_ELSR18I=106,
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,
+IR_POE_OEI1=170,IR_POE_OEI2,
+IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,
+IR_SCI12_ERI12=238,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0
+};
+
+enum enum_dtce {
+DTCE_ICU_SWINT=27,
+DTCE_CMT0_CMI0,
+DTCE_CMT1_CMI1,
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,
+DTCE_ELC_ELSR18I=106,
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0
+};
+
+enum enum_ier {
+IER_BSC_BUSERR=0x02,
+IER_ICU_SWINT=0x03,
+IER_CMT0_CMI0=0x03,
+IER_CMT1_CMI1=0x03,
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,
+IER_DOC_DOPCF=0x07,
+IER_RTC_CUP=0x07,
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,
+IER_USB0_USBR0=0x0B,
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,
+IER_ELC_ELSR18I=0x0D,
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F
+};
+
+enum enum_ipr {
+IPR_BSC_BUSERR=0,
+IPR_ICU_SWINT=3,
+IPR_CMT0_CMI0=4,
+IPR_CMT1_CMI1=5,
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,
+IPR_DOC_DOPCF=57,
+IPR_RTC_CUP=63,
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,
+IPR_USB0_USBR0=90,
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,
+IPR_ELC_ELSR18I=106,
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249,
+IPR_BSC_=0,
+IPR_CMT0_=4,
+IPR_CMT1_=5,
+IPR_RSPI0_=44,
+IPR_DOC_=57,
+IPR_ELC_=106,
+IPR_MTU1_TGI=121,
+IPR_MTU1_TCI=123,
+IPR_MTU2_TGI=125,
+IPR_MTU2_TCI=127,
+IPR_MTU3_TGI=129,
+IPR_MTU4_TGI=134,
+IPR_MTU5_=139,
+IPR_MTU5_TGI=139,
+IPR_SCI1_=218,
+IPR_SCI5_=222
+};
+
+#define IEN_BSC_BUSERR IEN0
+#define IEN_ICU_SWINT IEN3
+#define IEN_CMT0_CMI0 IEN4
+#define IEN_CMT1_CMI1 IEN5
+#define IEN_CAC_FERRF IEN0
+#define IEN_CAC_MENDF IEN1
+#define IEN_CAC_OVFF IEN2
+#define IEN_USB0_D0FIFO0 IEN4
+#define IEN_USB0_D1FIFO0 IEN5
+#define IEN_USB0_USBI0 IEN6
+#define IEN_RSPI0_SPEI0 IEN4
+#define IEN_RSPI0_SPRI0 IEN5
+#define IEN_RSPI0_SPTI0 IEN6
+#define IEN_RSPI0_SPII0 IEN7
+#define IEN_DOC_DOPCF IEN1
+#define IEN_RTC_CUP IEN7
+#define IEN_ICU_IRQ0 IEN0
+#define IEN_ICU_IRQ1 IEN1
+#define IEN_ICU_IRQ2 IEN2
+#define IEN_ICU_IRQ3 IEN3
+#define IEN_ICU_IRQ4 IEN4
+#define IEN_ICU_IRQ5 IEN5
+#define IEN_ICU_IRQ6 IEN6
+#define IEN_ICU_IRQ7 IEN7
+#define IEN_LVD_LVD1 IEN0
+#define IEN_LVD_LVD2 IEN1
+#define IEN_USB0_USBR0 IEN2
+#define IEN_RTC_ALM IEN4
+#define IEN_RTC_PRD IEN5
+#define IEN_S12AD_S12ADI0 IEN6
+#define IEN_S12AD_GBADI IEN7
+#define IEN_ELC_ELSR18I IEN2
+#define IEN_MTU0_TGIA0 IEN2
+#define IEN_MTU0_TGIB0 IEN3
+#define IEN_MTU0_TGIC0 IEN4
+#define IEN_MTU0_TGID0 IEN5
+#define IEN_MTU0_TCIV0 IEN6
+#define IEN_MTU0_TGIE0 IEN7
+#define IEN_MTU0_TGIF0 IEN0
+#define IEN_MTU1_TGIA1 IEN1
+#define IEN_MTU1_TGIB1 IEN2
+#define IEN_MTU1_TCIV1 IEN3
+#define IEN_MTU1_TCIU1 IEN4
+#define IEN_MTU2_TGIA2 IEN5
+#define IEN_MTU2_TGIB2 IEN6
+#define IEN_MTU2_TCIV2 IEN7
+#define IEN_MTU2_TCIU2 IEN0
+#define IEN_MTU3_TGIA3 IEN1
+#define IEN_MTU3_TGIB3 IEN2
+#define IEN_MTU3_TGIC3 IEN3
+#define IEN_MTU3_TGID3 IEN4
+#define IEN_MTU3_TCIV3 IEN5
+#define IEN_MTU4_TGIA4 IEN6
+#define IEN_MTU4_TGIB4 IEN7
+#define IEN_MTU4_TGIC4 IEN0
+#define IEN_MTU4_TGID4 IEN1
+#define IEN_MTU4_TCIV4 IEN2
+#define IEN_MTU5_TGIU5 IEN3
+#define IEN_MTU5_TGIV5 IEN4
+#define IEN_MTU5_TGIW5 IEN5
+#define IEN_POE_OEI1 IEN2
+#define IEN_POE_OEI2 IEN3
+#define IEN_SCI1_ERI1 IEN2
+#define IEN_SCI1_RXI1 IEN3
+#define IEN_SCI1_TXI1 IEN4
+#define IEN_SCI1_TEI1 IEN5
+#define IEN_SCI5_ERI5 IEN6
+#define IEN_SCI5_RXI5 IEN7
+#define IEN_SCI5_TXI5 IEN0
+#define IEN_SCI5_TEI5 IEN1
+#define IEN_SCI12_ERI12 IEN6
+#define IEN_SCI12_RXI12 IEN7
+#define IEN_SCI12_TXI12 IEN0
+#define IEN_SCI12_TEI12 IEN1
+#define IEN_SCI12_SCIX0 IEN2
+#define IEN_SCI12_SCIX1 IEN3
+#define IEN_SCI12_SCIX2 IEN4
+#define IEN_SCI12_SCIX3 IEN5
+#define IEN_RIIC0_EEI0 IEN6
+#define IEN_RIIC0_RXI0 IEN7
+#define IEN_RIIC0_TXI0 IEN0
+#define IEN_RIIC0_TEI0 IEN1
+
+#define VECT_BSC_BUSERR 16
+#define VECT_ICU_SWINT 27
+#define VECT_CMT0_CMI0 28
+#define VECT_CMT1_CMI1 29
+#define VECT_CAC_FERRF 32
+#define VECT_CAC_MENDF 33
+#define VECT_CAC_OVFF 34
+#define VECT_USB0_D0FIFO0 36
+#define VECT_USB0_D1FIFO0 37
+#define VECT_USB0_USBI0 38
+#define VECT_RSPI0_SPEI0 44
+#define VECT_RSPI0_SPRI0 45
+#define VECT_RSPI0_SPTI0 46
+#define VECT_RSPI0_SPII0 47
+#define VECT_DOC_DOPCF 57
+#define VECT_RTC_CUP 63
+#define VECT_ICU_IRQ0 64
+#define VECT_ICU_IRQ1 65
+#define VECT_ICU_IRQ2 66
+#define VECT_ICU_IRQ3 67
+#define VECT_ICU_IRQ4 68
+#define VECT_ICU_IRQ5 69
+#define VECT_ICU_IRQ6 70
+#define VECT_ICU_IRQ7 71
+#define VECT_LVD_LVD1 88
+#define VECT_LVD_LVD2 89
+#define VECT_USB0_USBR0 90
+#define VECT_RTC_ALM 92
+#define VECT_RTC_PRD 93
+#define VECT_S12AD_S12ADI0 102
+#define VECT_S12AD_GBADI 103
+#define VECT_ELC_ELSR18I 106
+#define VECT_MTU0_TGIA0 114
+#define VECT_MTU0_TGIB0 115
+#define VECT_MTU0_TGIC0 116
+#define VECT_MTU0_TGID0 117
+#define VECT_MTU0_TCIV0 118
+#define VECT_MTU0_TGIE0 119
+#define VECT_MTU0_TGIF0 120
+#define VECT_MTU1_TGIA1 121
+#define VECT_MTU1_TGIB1 122
+#define VECT_MTU1_TCIV1 123
+#define VECT_MTU1_TCIU1 124
+#define VECT_MTU2_TGIA2 125
+#define VECT_MTU2_TGIB2 126
+#define VECT_MTU2_TCIV2 127
+#define VECT_MTU2_TCIU2 128
+#define VECT_MTU3_TGIA3 129
+#define VECT_MTU3_TGIB3 130
+#define VECT_MTU3_TGIC3 131
+#define VECT_MTU3_TGID3 132
+#define VECT_MTU3_TCIV3 133
+#define VECT_MTU4_TGIA4 134
+#define VECT_MTU4_TGIB4 135
+#define VECT_MTU4_TGIC4 136
+#define VECT_MTU4_TGID4 137
+#define VECT_MTU4_TCIV4 138
+#define VECT_MTU5_TGIU5 139
+#define VECT_MTU5_TGIV5 140
+#define VECT_MTU5_TGIW5 141
+#define VECT_POE_OEI1 170
+#define VECT_POE_OEI2 171
+#define VECT_SCI1_ERI1 218
+#define VECT_SCI1_RXI1 219
+#define VECT_SCI1_TXI1 220
+#define VECT_SCI1_TEI1 221
+#define VECT_SCI5_ERI5 222
+#define VECT_SCI5_RXI5 223
+#define VECT_SCI5_TXI5 224
+#define VECT_SCI5_TEI5 225
+#define VECT_SCI12_ERI12 238
+#define VECT_SCI12_RXI12 239
+#define VECT_SCI12_TXI12 240
+#define VECT_SCI12_TEI12 241
+#define VECT_SCI12_SCIX0 242
+#define VECT_SCI12_SCIX1 243
+#define VECT_SCI12_SCIX2 244
+#define VECT_SCI12_SCIX3 245
+#define VECT_RIIC0_EEI0 246
+#define VECT_RIIC0_RXI0 247
+#define VECT_RIIC0_TXI0 248
+#define VECT_RIIC0_TEI0 249
+
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17
+#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0
+
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR
+#define _IR( x ) __IR( x )
+#define IR( x , y ) _IR( _ ## x ## _ ## y )
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE
+#define _DTCE( x ) __DTCE( x )
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x
+#define _IEN( x ) __IEN( x )
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR
+#define _IPR( x ) __IPR( x )
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )
+#define __VECT( x ) VECT ## x
+#define _VECT( x ) __VECT( x )
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )
+#define __MSTP( x ) MSTP ## x
+#define _MSTP( x ) __MSTP( x )
+#define MSTP( x ) _MSTP( _ ## x )
+
+#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300)
+#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000)
+#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000)
+#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002)
+#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008)
+#define CRC (*(volatile struct st_crc __evenaccess *)0x88280)
+#define DA (*(volatile struct st_da __evenaccess *)0x880C0)
+#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080)
+#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400)
+#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100)
+#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090)
+#define ICU (*(volatile struct st_icu __evenaccess *)0x87000)
+#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030)
+#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C11F)
+#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A)
+#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690)
+#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690)
+#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692)
+#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600)
+#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600)
+#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694)
+#define POE (*(volatile struct st_poe __evenaccess *)0x88900)
+#define PORT (*(volatile struct st_port __evenaccess *)0x8C120)
+#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000)
+#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001)
+#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002)
+#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003)
+#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004)
+#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005)
+#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A)
+#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B)
+#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C)
+#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)
+#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300)
+#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380)
+#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400)
+#define RTCB (*(volatile struct st_rtcb __evenaccess *)0x8C402)
+#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000)
+#define SCI1 (*(volatile struct st_sci1 __evenaccess *)0x8A020)
+#define SCI5 (*(volatile struct st_sci1 __evenaccess *)0x8A0A0)
+#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300)
+#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020)
+#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0)
+#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300)
+#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000)
+#define USB0 (*(volatile struct st_usb __evenaccess *)0xA0000)
+#pragma bit_order
+#pragma packoption
+#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h
new file mode 100644
index 000000000..6ed672bf5
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/mcu/rx111/mcu_info.h
@@ -0,0 +1,112 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : mcu_info.h
+* Device(s) : RX111
+* Description : Information about the MCU on this board (RSKRX111).
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 08.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+
+#ifndef _MCU_INFO
+#define _MCU_INFO
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Gets MCU configuration information. */
+#include "r_bsp_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* MCU Series. */
+#if MCU_PART_SERIES == 0x0
+ #define MCU_SERIES_RX100 (1)
+#else
+ #error "ERROR - MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h"
+#endif
+
+/* MCU Group name. */
+#if MCU_PART_GROUP == 0x1
+ #define MCU_RX111 (1)
+ #define MCU_RX11x (1)
+#else
+ #error "ERROR - MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h"
+#endif
+
+/* Package. */
+#if MCU_PART_PACKAGE == 0x0
+ #define PACKAGE_LFQFP64 (1)
+#elif MCU_PART_PACKAGE == 0x1
+ #define PACKAGE_LQFP64 (1)
+#elif MCU_PART_PACKAGE == 0x2
+ #define PACKAGE_TFLGA64 (1)
+#elif MCU_PART_PACKAGE == 0x3
+ #define PACKAGE_LFQFP48 (1)
+#elif MCU_PART_PACKAGE == 0x4
+ #define PACKAGE_VQFN48 (1)
+#elif MCU_PART_PACKAGE == 0x5
+ #define PACKAGE_HWQFN36 (1)
+#elif MCU_PART_PACKAGE == 0x6
+ #define PACKAGE_WFLGA36 (1)
+#elif MCU_PART_PACKAGE == 0x7
+ #define PACKAGE_SSOP36 (1)
+#else
+ #error "ERROR - MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h"
+#endif
+
+/* Memory size of your MCU. */
+#if MCU_PART_MEMORY_SIZE == 0x0 // "J" parts
+ #define ROM_SIZE_BYTES (16384)
+ #define RAM_SIZE_BYTES (8192)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x1
+ #define ROM_SIZE_BYTES (32768)
+ #define RAM_SIZE_BYTES (10240)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x3
+ #define ROM_SIZE_BYTES (65536)
+ #define RAM_SIZE_BYTES (10240)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x4
+ #define ROM_SIZE_BYTES (98304)
+ #define RAM_SIZE_BYTES (16384)
+ #define DF_SIZE_BYTES (8192)
+#elif MCU_PART_MEMORY_SIZE == 0x5
+ #define ROM_SIZE_BYTES (131072)
+ #define RAM_SIZE_BYTES (16384)
+ #define DF_SIZE_BYTES (8192)
+#else
+ #error "ERROR - MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h"
+#endif
+
+/* System clock speed in Hz. */
+#define ICLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV)
+/* Peripheral Module Clock B speed in Hz. */
+#define PCLKB_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV)
+/* Peripheral Module Clock D speed in Hz. */
+#define PCLKD_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV)
+/* FlashIF clock speed in Hz. */
+#define FCLK_HZ (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV)
+
+#endif /* _MCU_INFO */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/platform.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/platform.h
new file mode 100644
index 000000000..3427aab94
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/platform.h
@@ -0,0 +1,88 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : platform.h
+* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using
+* is not listed below, please add your own or use the default 'User Board'.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 30.11.2011 1.00 First Release
+* : 13.01.2012 1.10 Moved from having platform defined using macro defintion, to having platform defined
+* by choosing an include path. This makes this file simpler and cleans up the issue
+* where HEW shows all header files for all platforms under 'Dependencies'.
+* : 14.02.2012 1.20 Added RX210 BSP.
+* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding
+* locking.c and locking.h in board folders. Also, r_bsp can now be configured through
+* r_bsp_config.h.
+* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using
+* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort
+* to remove any extra files that the user would need to touch. Removed the flash_options.c
+* file and put its contents in vecttbl.c.
+* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT
+* macro options in r_bsp_config.h. Added some extra code to handle exceptions in
+* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks.
+* : 08.11.2012 1.60 Added RX111 BSP
+***********************************************************************************************************************/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+/***********************************************************************************************************************
+DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING.
+***********************************************************************************************************************/
+/* RSKRX610 */
+//#include "./board/rskrx610/r_bsp.h"
+
+/* RSKRX62N */
+//#include "./board/rskrx62n/r_bsp.h"
+
+/* RSKRX62T */
+//#include "./board/rskrx62t/r_bsp.h"
+
+/* RDKRX62N */
+//#include "./board/rdkrx62n/r_bsp.h"
+
+/* RSKRX630 */
+//#include "./board/rskrx630/r_bsp.h"
+
+/* RSKRX63N */
+//#include "./board/rskrx63n/r_bsp.h"
+
+/* RDKRX63N */
+//#include "./board/rdkrx63n/r_bsp.h"
+
+/* RSKRX210 */
+//#include "./board/rskrx210/r_bsp.h"
+
+/* RSKRX111 */
+#include "./board/rskrx111/r_bsp.h"
+
+/* User Board - Define your own board here. */
+//#include "./board/user/r_bsp.h"
+
+/***********************************************************************************************************************
+MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT
+***********************************************************************************************************************/
+#ifndef PLATFORM_DEFINED
+#error "Error - No platform defined in platform.h!"
+#endif
+
+#endif /* _PLATFORM_H_ */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/r_bsp_config.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/r_bsp_config.h
new file mode 100644
index 000000000..537479e8a
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/r_bsp_config.h
@@ -0,0 +1,250 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_bsp_config_reference.c
+* Device(s) : RX111
+* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included
+* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h)
+* is just a reference file that the user can use to make their own r_bsp_config.h file.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 07.11.2012 0.01 Beta Release
+***********************************************************************************************************************/
+#ifndef R_BSP_CONFIG_REF_HEADER_FILE
+#define R_BSP_CONFIG_REF_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such
+ as package and memory size.
+ To help parse this information, the part number will be defined using multiple macros.
+ R 5 F 51 11 5 A D FM
+ | | | | | | | | | Macro Name Description
+ | | | | | | | | |__MCU_PART_PACKAGE = Package type, number of pins, and pin pitch
+ | | | | | | | |____not used = Products with wide temperature range (D: -40 to 85C G: -40 to 105C)
+ | | | | | | |______not used = Blank
+ | | | | | |________MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity
+ | | | | |___________MCU_PART_GROUP = Group name
+ | | | |______________MCU_PART_SERIES = Series name
+ | | |________________MCU_PART_MEMORY_TYPE = Type of memory (Flash)
+ | |__________________not used = Renesas MCU
+ |____________________not used = Renesas semiconductor product.
+ */
+
+/* Package type. Set the macro definition based on values below:
+ Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch
+ FM = 0x0 = LFQFP/64/0.50
+ FK = 0x1 = LQFP/64/0.80
+ LF = 0x2 = TFLGA/64/0.50
+ FL = 0x3 = LFQFP/48/0.50
+ NE = 0x4 = VQFN/48/0.50
+ NC = 0x5 = HWQFN/36/0.50
+ LM = 0x6 = WFLGA/36/0.50
+ SB = 0x7 = SSOP/36/0.80
+*/
+#define MCU_PART_PACKAGE (0x0)
+
+/* ROM, RAM, and Data Flash Capacity.
+ Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size
+ 5 = 0x5 = 128KB/16KB/8KB
+ 4 = 0x4 = 96KB/16KB/8KB
+ 3 = 0x3 = 64KB/10KB/8KB
+ 1 = 0x1 = 32KB/10KB/8KB
+ J = 0x0 = 16KB/8KB/8KB
+*/
+#define MCU_PART_MEMORY_SIZE (0x5)
+
+/* Group name.
+ Character(s) = Value for macro = Description
+ 10 = 0x0 = RX110 Group
+ 11 = 0x1 = RX111 Group
+*/
+#define MCU_PART_GROUP (0x1)
+
+/* Series name.
+ Character(s) = Value for macro = Description
+ 51 = 0x0 = RX100 Series
+*/
+#define MCU_PART_SERIES (0x0)
+
+/* Memory type.
+ Character(s) = Value for macro = Description
+ F = 0x0 = Flash memory version
+*/
+#define MCU_PART_MEMORY_TYPE (0x0)
+
+/* The 'BSP_DECLARE_STACK' macro is checked so that the stack is only declared in one place (resetprg.c). Every time a
+ '#pragma stacksize' is encountered, the stack size is increased. This prevents multiplication of stack size. */
+#if defined(BSP_DECLARE_STACK)
+/* User Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize su=0x400
+/* Interrupt Stack size in bytes. The Renesas RX toolchain sets the stack size using the #pragma stacksize directive. */
+#pragma stacksize si=0x100
+#endif
+
+/* Heap size in bytes. */
+#define HEAP_BYTES (0x001)
+
+/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information
+ on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual.
+ 0 = Stay in Supervisor mode.
+ 1 = Switch to User mode.
+*/
+#define RUN_IN_USER_MODE (0)
+
+
+/* This macro lets other modules no if a RTOS is being used.
+ 0 = RTOS is not used.
+ 1 = RTOS is used.
+*/
+#define RTOS_USED (0)
+
+/* Clock source select (CKSEL).
+ 0 = Low Speed On-Chip Oscillator (LOCO)
+ 1 = High Speed On-Chip Oscillator (HOCO)
+ 2 = Main Clock Oscillator
+ 3 = Sub-Clock Oscillator
+ 4 = PLL Circuit
+*/
+#define CLOCK_SOURCE (4) // GI org 4
+
+/* Clock configuration options.
+ The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The
+ multiplier settings are used to set the clock registers in resetprg.c. If a 16MHz clock is used and the
+ ICLK is 24MHz, PCLKB is 24MHz, FCLK is 24MHz, PCLKD is 24MHz, and CKO is 1MHz then the
+ settings would be:
+
+ XTAL_HZ = 16000000
+ PLL_DIV = 2
+ PLL_MUL = 6 (16MHz x 3 = 48MHz)
+ ICK_DIV = 2 : System Clock (ICLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / ICK_DIV) = 24MHz
+ PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKB_DIV) = 24MHz
+ PCKD_DIV = 2 : Peripheral Clock D (PCLKD) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / PCKD_DIV) = 24MHz
+ FCK_DIV = 2 : Flash IF Clock (FCLK) = (((XTAL_HZ/PLL_DIV) * PLL_MUL) / FCK_DIV) = 24MHz
+*/
+/* XTAL - Input clock frequency in Hz */
+#define XTAL_HZ (16000000)
+/* PLL Input Frequency Divider Select (PLIDIV).
+ Available divisors = /1 (no division), /2, /4
+*/
+#define PLL_DIV (2) // GI org 2
+/* PLL Frequency Multiplication Factor Select (STC).
+ Available multipliers = x6, x8
+*/
+#define PLL_MUL (6) // GI org 6
+/* System Clock Divider (ICK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define ICK_DIV (2) // NOTE: ICLK CANNOT BE SLOWER THAN PCLK!
+/* Peripheral Module Clock B Divider (PCKB).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKB_DIV (2) // GI org 2
+/* Peripheral Module Clock D Divider (PCKD).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define PCKD_DIV (2)
+/* Flash IF Clock Divider (FCK).
+ Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64
+*/
+#define FCK_DIV (2)
+
+/* Below are callback functions that can be used for detecting MCU exceptions, undefined interrupt sources, and
+ bus errors. If the user wishes to be alerted of these events then they will need to define the macro as a
+ function to be called when the event occurs. For example, if the user wanted the function
+ excep_undefined_instr_isr() to be called when an undefined interrupt source ISR is triggered then they would
+ do the following:
+ #define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+ If the user does not wish to be alerted of these events then they should comment out the macros.
+
+ NOTE: When a callback function is called it will be called from within a ISR. This means that the function
+ will essentially be an interrupt and will hold off other interrupts that occur in the system while it
+ is executing. For this reason, it is recommended to keep these callback functions short as to not
+ decrease the real-time response of your system.
+*/
+/* Callback for Supervisor Instruction Violation Exception. */
+//#define EXCEP_SUPERVISOR_ISR_CALLBACK supervisor_instr_cb
+
+/* Callback for Undefined Instruction Exception. */
+//#define EXCEP_UNDEFINED_INSTR_ISR_CALLBACK undefined_instr_cb
+
+/* Callback for Non-maskable Interrupt. */
+//#define NMI_ISR_CALLBACK nmi_cb
+
+/* Callback for all undefined interrupt vectors. User can set a breakpoint in this function to determine which source
+ is creating unwanted interrupts. */
+//#define UNDEFINED_INT_ISR_CALLBACK undefined_interrupt_cb
+
+/* Callback for Bus Error Interrupt. */
+//#define BUS_ERROR_ISR_CALLBACK bus_error_cb
+
+/* The user has the option of separately choosing little or big endian for the User Application Area */
+
+/* Endian mode for User Application.
+ 0 = Big Endian
+ Else = Little Endian (Default)
+*/
+#define USER_APP_ENDIAN (1)
+
+
+/* Configure WDT and IWDT settings.
+ OFS0 - Option Function Select Register 0
+ OFS0 - Option Function Select Register 0
+ b31:b15 Reserved (set to 1)
+ b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes)
+ b13 Reserved (set to 1)
+ b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU)
+ b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use)
+ b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use)
+ b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256)
+ b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048)
+ b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset)
+ b0 Reserved (set to 1) */
+#define OFS0_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset.
+ OFS1 - Option Function Select Register 1
+ b31:b9 Reserved (set to 1)
+ b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable)
+ b7:b4 STUPLVD1LVL - Startup Voltage Monitoring 1 Reset Detection Level Select
+ 0 1 0 0: 3.10 V
+ 0 1 0 1: 3.00 V
+ 0 1 1 0: 2.90 V
+ 0 1 1 1: 2.79 V
+ 1 0 0 0: 2.68 V
+ 1 0 0 1: 2.58 V
+ 1 0 1 0: 2.48 V
+ 1 0 1 1: 2.06 V
+ 1 1 0 0: 1.96 V
+ 1 1 0 1: 1.86 V
+ b3:b2 Reserved (set to 1)
+ b2 STUPLVD1REN - Startup Voltage Monitoring 1 Reset Enable (1=monitoring disabled)
+ b0 FASTSTUP - Power-On Fast Startup Time (1=normal; read only) */
+#define OFS1_REG_VALUE (0xFFFFFFFF) //Disable by default
+
+/* Initializes C input & output library functions.
+ 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value.
+ 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. */
+#define IO_LIB_ENABLE (0)
+
+#endif /* R_BSP_CONFIG_REF_HEADER_FILE */
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/readme.txt b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/readme.txt
new file mode 100644
index 000000000..c7ee2b751
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_bsp/readme.txt
@@ -0,0 +1,100 @@
+r_bsp Package
+=============
+
+Document Number
+---------------
+N/A
+
+Version
+-------
+v1.60
+
+Overview
+--------
+The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU
+information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder has iodefine
+files and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board
+and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help
+configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each
+supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which
+board they are using by uncommenting the include path that applies to their board. For example, if you are using the
+RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add
+their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a
+reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it
+to r_bsp_config.h, and use the options inside the file to configure the BSP for their project.
+
+Features
+--------
+* Provides foundation to build code on top of.
+* Provides MCU startup code.
+* Provides SFR access through iodefine.h
+* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware.
+* Easily configure BSP through r_bsp_config.h.
+* Choose MCU easily by inputting part number details in r_bsp_config.h.
+* Provides callbacks for MCU exceptions and the bus error interrupt.
+
+Limitations
+-----------
+N/A
+
+Peripherals Used Directly
+-------------------------
+N/A
+
+Required Packages
+-----------------
+* r_glyph [required if you want to use LCD for RDK boards]
+* r_rspi_rx [required if you want to use LCD for RDK boards]
+
+How to add to your project
+--------------------------
+* Copy the r_bsp folder to your project.
+* Add an include path to the 'r_bsp' directory.
+* Add all of the source files for your board from the 'r_bsp\board\--YOUR_BOARD--' directory to your project.
+* Uncomment the include path for your board in 'platform.h' which is located in the 'r_bsp' directory.
+* Copy the file r_bsp_config_reference.h from the 'r_bsp\board\--YOUR_BOARD--' directory and copy it to your project's
+ source code directory. Rename the file r_bsp_config.h.
+* Open r_bsp_config.h and use the macros to configure the BSP for your project.
+
+File Structure
+--------------
+r_bsp
+| platform.h (choose which board is being used)
+| readme.txt
+|
++---board (contains supported boards)
+| +---rdkrx62n (contains BSP source and header files)
+| |
+| +---rdkrx63n
+| |
+| +---rskrx111
+| |
+| +---rskrx210
+| |
+| +---rskrx610
+| |
+| +---rskrx62n
+| |
+| +---rskrx62t
+| |
+| +---rskrx630
+| |
+| +---rskrx63n
+| |
+| \---user
+|
+\---mcu
+ +---rx111 (contains common files to this MCU group, e.g. iodefine.h)
+ |
+ +---rx210
+ |
+ +---rx610
+ |
+ +---rx62n
+ |
+ +---rx62t
+ |
+ +---rx630
+ |
+ \---rx63n
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/doc/r_switches.docx b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/doc/r_switches.docx
new file mode 100644
index 000000000..6fe7e86e5
Binary files /dev/null and b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/doc/r_switches.docx differ
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_config.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_config.h
new file mode 100644
index 000000000..834de6bfd
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_config.h
@@ -0,0 +1,59 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_config.c
+* Description : Configures the switches code
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+#ifndef SWITCHES_CONFIG_HEADER_FILE
+#define SWITCHES_CONFIG_HEADER_FILE
+
+/***********************************************************************************************************************
+Configuration Options
+***********************************************************************************************************************/
+/* This macro sets whether interrupts or polling is used for detecting switch presses. The benefit of using interrupts
+ is that no extra processing is used for polling and the use of a system timer tick is not a requirement. The downside
+ of using interrupts is that callback functions are called from within an interrupt so if your ISR is long then it can
+ degrade the real-time response of your system. The benefit of polling is that functions are called at the application
+ level and debouncing is supported. The downside to polling is that your system must call the R_SWITCHES_Update() on a
+ regular basis which requires extra processing.
+
+ 0 = Use interrupts
+ 1 = Use polling
+ */
+#define SWITCHES_DETECTION_MODE (0)
+
+/* The definition for these macros should be the name of the function that you want called when a switch is
+ pressed. It is very important that the user recognize that this function will be called from the interrupt service
+ routine. This means that code inside of the function should be kept short to ensure it does not hold up the rest of
+ the system.
+
+ Example: If SW1_CALLBACK_FUNCTION is defined to be sw1_callback then the sw1_callback function will be called when
+ switch 1 is pressed.
+*/
+#define SW1_CALLBACK_FUNCTION (vButtonInterruptCallback)
+#define SW2_CALLBACK_FUNCTION (vButtonInterruptCallback)
+#define SW3_CALLBACK_FUNCTION (vButtonInterruptCallback)
+
+#endif /* SWITCHES_CONFIG_HEADER_FILE */
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_if.h b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_if.h
new file mode 100644
index 000000000..613bcf5e3
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/r_switches_if.h
@@ -0,0 +1,74 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches_if.h
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+***********************************************************************************************************************/
+
+#ifndef SWITCHES_API_HEADER_FILE
+#define SWITCHES_API_HEADER_FILE
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Fixed width integer support. */
+#include
+/* bool support */
+#include
+/* Used for configuring the code */
+#include "r_switches_config.h"
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Version Number of API. */
+#define SWITCHES_VERSION_MAJOR (1)
+#define SWITCHES_VERSION_MINOR (0)
+/* The process of getting the version number is done through the macro below. The version number is encoded where the
+ top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example,
+ Version 4.25 would be returned as 0x00040019. */
+#define R_SWITCHES_GetVersion() ((((uint32_t)SWITCHES_VERSION_MAJOR) << 16) | (uint32_t)SWITCHES_VERSION_MINOR)
+
+/***********************************************************************************************************************
+Public Functions
+***********************************************************************************************************************/
+void R_SWITCHES_Init(uint32_t detection_hz, uint32_t debounce_counts);
+void R_SWITCHES_Update(void);
+
+/* Callback prototypes. */
+#if defined(SW1_CALLBACK_FUNCTION)
+void SW1_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW2_CALLBACK_FUNCTION)
+void SW2_CALLBACK_FUNCTION(void);
+#endif
+
+#if defined(SW3_CALLBACK_FUNCTION)
+void SW3_CALLBACK_FUNCTION(void);
+#endif
+
+#endif /* SWITCHES_API_HEADER_FILE */
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/readme.txt b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/readme.txt
new file mode 100644
index 000000000..d1e1e40fb
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/readme.txt
@@ -0,0 +1,83 @@
+PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION
+
+Switches
+========
+
+Document Number
+---------------
+N/A
+
+Version
+-------
+v1.40
+
+Overview
+--------
+Configures port pins for switches and calls user defined function on switch press. Switch presses can be detected using
+IRQ interrupts or by polling. The benefit of using interrupts is that no extra processing is used for polling and the
+use of a system timer tick is not a requirement. The downside of using interrupts is that callback functions are called
+from within an interrupt so if your ISR is long then it can degrade the real-time response of your system. The benefit
+of polling is that functions are called at the application level and debouncing is supported. The downside to polling is
+that your system must call the R_SWITCHES_Update() on a regular basis which requires extra processing.
+
+Features
+--------
+* Call one function to setup switches.
+* Define function to call when switch is pressed.
+* Can be configured to be interrupt or poll driven.
+
+Supported MCUs
+--------------
+* RX610 Group
+* RX621, RX62N Group
+* RX62T Group
+* RX630 Group
+* RX631, RX63N Group
+* RX210 Group
+* RX111 Group
+
+Boards Tested On
+----------------
+* RSKRX610
+* RSK+RX62N
+* RSKRX62T
+* RDKRX62N
+* RSKRX630
+* RSKRX63N
+* RDKRX63N
+* RSKRX111
+
+Limitations
+-----------
+* None
+
+Peripherals Used Directly
+-------------------------
+* None
+
+Required Packages
+-----------------
+* None
+
+How to add to your project
+--------------------------
+* Add src\r_switches.c to your project.
+* Add an include path to the 'r_switches' directory.
+* Add an include path to the 'r_switches\src' directory.
+* Configure middleware through r_switches_config.h.
+* Add a #include for r_switches_if.h to files that need to use this package.
+
+Toolchain(s) Used
+-----------------
+* Renesas RX v1.02
+
+File Structure
+--------------
+r_switches
+| readme.txt
+| r_switches_config.h
+| r_switches_if.h
+|
+\---src
+ r_switches.c
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/src/r_switches.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/src/r_switches.c
new file mode 100644
index 000000000..813c43677
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/Renesas_Files/r_switches/src/r_switches.c
@@ -0,0 +1,483 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* File Name : r_switches.c
+* Description : Functions for using switches with callback functions.
+************************************************************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 17.01.2012 1.00 First Release
+* : 17.02.2012 1.10 Added RSKRX210 support.
+* : 08.03.2012 1.20 Added GetVersion() function (though it's really a macro).
+* : 04.06.2012 1.30 Code can now be interrupt or poll driven.
+* : 07.11.2012 1.40 Added support for RSKRX111
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes , "Project Includes"
+***********************************************************************************************************************/
+/* Board and MCU support. */
+#include "platform.h"
+/* Switches prototypes. */
+#include "r_switches_if.h"
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* This helps reduce the amount of unique code for each supported board. */
+#define X_IRQ( x ) XX_IRQ( x )
+#define XX_IRQ( x ) _ICU_IRQ##x
+
+/* These macros define which IRQ pins are used for the switches. Note that these defintions cannot have parentheses
+ around them. */
+#if defined(PLATFORM_BOARD_RDKRX63N)
+ #define SW1_IRQ_NUMBER 8
+ #define SW2_IRQ_NUMBER 9
+ #define SW3_IRQ_NUMBER 12
+#elif defined(PLATFORM_BOARD_RSKRX63N)
+ #define SW1_IRQ_NUMBER 2
+ #define SW2_IRQ_NUMBER 8
+ #define SW3_IRQ_NUMBER 15
+#elif defined(PLATFORM_BOARD_RSKRX630)
+ #define SW1_IRQ_NUMBER 2
+ #define SW2_IRQ_NUMBER 12
+ #define SW3_IRQ_NUMBER 15
+#elif defined(PLATFORM_BOARD_RSKRX62N)
+ #define SW1_IRQ_NUMBER 8
+ #define SW2_IRQ_NUMBER 9
+ #define SW3_IRQ_NUMBER 15
+#elif defined(PLATFORM_BOARD_RDKRX62N)
+ #define SW1_IRQ_NUMBER 8
+ #define SW2_IRQ_NUMBER 9
+ #define SW3_IRQ_NUMBER 10
+#elif defined(PLATFORM_BOARD_RSKRX62T)
+ #define SW1_IRQ_NUMBER 0
+ #define SW2_IRQ_NUMBER 1
+ #define SW3_IRQ_NUMBER 3
+#elif defined(PLATFORM_BOARD_RSKRX610)
+ #define SW1_IRQ_NUMBER 8
+ #define SW2_IRQ_NUMBER 9
+ #define SW3_IRQ_NUMBER 3
+#elif defined(PLATFORM_BOARD_RSKRX210)
+ #define SW1_IRQ_NUMBER 1
+ #define SW2_IRQ_NUMBER 3
+ #define SW3_IRQ_NUMBER 4
+#elif defined(PLATFORM_BOARD_RSKRX111)
+ #define SW1_IRQ_NUMBER 0
+ #define SW2_IRQ_NUMBER 1
+ #define SW3_IRQ_NUMBER 4
+#endif
+
+/* Number of switches on this board. */
+#define SWITCHES_NUM (3)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef struct
+{
+ bool active;
+ int32_t debounce_cnt;
+} switch_t;
+
+/***********************************************************************************************************************
+Private global variables and functions
+***********************************************************************************************************************/
+#if SWITCHES_DETECTION_MODE == 1
+/* Update Hz */
+static uint32_t g_sw_debounce_cnts;
+/* Used for debounce. */
+switch_t g_switches[SWITCHES_NUM];
+#endif
+
+/***********************************************************************************************************************
+* Function Name: R_SWITCHES_Init
+* Description : Initializes pins to be input and interrupt on switch presses.
+* Arguments : detection_hz -
+* The times per second that the user will call R_SWITCHES_Update(). NOTE: this is only when using
+* polling mode. If you are using interrupt mode, then this argument will be ignored.
+* debouce_counts -
+* The number of times to check the port value before accepting the change. The slower the rate at
+* which R_SWITCHES_Update() will likely lower this number.
+* Return Value : none
+***********************************************************************************************************************/
+void R_SWITCHES_Init (uint32_t detection_hz, uint32_t debounce_counts)
+{
+ uint32_t i;
+
+ /* The SW#_XXX defintions are common macros amongst different boards. To see the definitions for these macros
+ see the board defintion file. For example, this file for the RSKRX63N is rskrx63n.h. */
+
+#if defined(MCU_RX62N) || defined(MCU_RX62T) || defined(MCU_RX621) || defined(MCU_RX610)
+
+ /* Make switch pins inputs. */
+ SW1_DDR = 0;
+ SW2_DDR = 0;
+ SW3_DDR = 0;
+
+ /* Enable input buffer control registers. */
+ SW1_ICR = 1;
+ SW2_ICR = 1;
+ SW3_ICR = 1;
+
+#elif defined(MCU_RX63N) || defined(MCU_RX630) || defined(MCU_RX631) || defined(MCU_RX210) || defined(MCU_RX111)
+
+ /* Unlock protection register */
+ MPC.PWPR.BIT.B0WI = 0 ;
+ /* Unlock MPC registers */
+ MPC.PWPR.BIT.PFSWE = 1 ;
+
+ /* Make switch pins inputs. */
+ SW1_PDR = 0;
+ SW2_PDR = 0;
+ SW3_PDR = 0;
+
+ /* Set port mode registers for switches. */
+ SW1_PMR = 0;
+ SW2_PMR = 0;
+ SW3_PMR = 0;
+
+#endif
+
+#if SWITCHES_DETECTION_MODE == 0
+
+ #if defined(PLATFORM_BOARD_RDKRX63N)
+
+ /* The switches on the RDKRX63N are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P4.0 IRQ8
+ SW2 P4.1 IRQ9
+ SW3 P4.4 IRQ12
+ */
+
+ MPC.P40PFS.BYTE = 0x40; /* P40 is used as IRQ pin */
+ MPC.P41PFS.BYTE = 0x40; /* P40 is used as IRQ pin */
+ MPC.P44PFS.BYTE = 0x40; /* P40 is used as IRQ pin */
+
+ #elif defined(PLATFORM_BOARD_RSKRX63N)
+
+ /* The switches on the RSKRX63N are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P3.2 IRQ2
+ SW2 P0.0 IRQ8
+ SW3 P0.7 IRQ15
+ */
+
+ MPC.P32PFS.BYTE = 0x40; /* P32 is used as IRQ pin */
+ MPC.P00PFS.BYTE = 0x40; /* P00 is used as IRQ pin */
+ MPC.P07PFS.BYTE = 0x40; /* P07 is used as IRQ pin */
+
+ #elif defined(PLATFORM_BOARD_RSKRX630)
+
+ /* The switches on the RSKRX630 are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P3.2 IRQ2
+ SW2 P4.4 IRQ12
+ SW3 P0.7 IRQ15
+ */
+
+ MPC.P32PFS.BYTE = 0x40; /* P32 is used as IRQ pin */
+ MPC.P44PFS.BYTE = 0x40; /* P44 is used as IRQ pin */
+ MPC.P07PFS.BYTE = 0x40; /* P07 is used as IRQ pin */
+
+ #elif defined(PLATFORM_BOARD_RSKRX62N)
+
+ /* The switches on the RSKRX62N are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P0.0 IRQ8-A
+ SW2 P0.1 IRQ9-A
+ SW3 P0.7 IRQ15-A
+ */
+
+ IOPORT.PF8IRQ.BIT.ITS8 = 0; /* IRQ8-A pin is used. */
+ IOPORT.PF8IRQ.BIT.ITS9 = 0; /* IRQ9-A pin is used. */
+ IOPORT.PF8IRQ.BIT.ITS15 = 0; /* IRQ15-A pin is used. */
+
+ #elif defined(PLATFORM_BOARD_RDKRX62N)
+
+ /* The switches on the RDKRX62N are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P4.0 IRQ8
+ SW2 P4.1 IRQ9
+ SW3 P4.2 IRQ10
+ */
+
+ /* Nothing else needed to do here since RDK has 100-pin package and there are no alternate pins to choose. */
+
+ #elif defined(PLATFORM_BOARD_RSKRX62T)
+
+ /* The switches on the RSKRX62T are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 PE.5 IRQ0-B
+ SW2 PE.4 IRQ1-B
+ SW3 PB.4 IRQ3
+ */
+
+ IOPORT.PF8IRQ.BIT.ITS0 = 1; /* IRQ0-B pin is used. */
+ IOPORT.PF8IRQ.BIT.ITS1 = 1; /* IRQ1-B pin is used. */
+ /* IRQ3 is only on 1 pin. */
+
+ #elif defined(PLATFORM_BOARD_RSKRX610)
+
+ /* The switches on the RSKRX610 are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P0.0 IRQ8-A
+ SW2 P0.1 IRQ9-A
+ SW3 P1.3 IRQ3-B
+ */
+
+ IOPORT.PFCR8.BIT.ITS8 = 0; /* IRQ8-A pin is used. */
+ IOPORT.PFCR8.BIT.ITS9 = 0; /* IRQ9-A pin is used. */
+ IOPORT.PFCR9.BIT.ITS3 = 1; /* IRQ3-B pin is used. */
+
+ /* Enable IRQ detection. */
+ ICU.IRQER[SW1_IRQ_NUMBER].BIT.IRQEN = 1;
+ ICU.IRQER[SW2_IRQ_NUMBER].BIT.IRQEN = 1;
+ ICU.IRQER[SW3_IRQ_NUMBER].BIT.IRQEN = 1;
+
+ #elif defined(PLATFORM_BOARD_RSKRX210)
+
+ /* The switches on the RSKRX210 are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P3.1 IRQ1
+ SW2 P3.3 IRQ3
+ SW3 P3.4 IRQ4
+ */
+
+ MPC.P31PFS.BYTE = 0x40; /* P31 is used as IRQ pin */
+ MPC.P33PFS.BYTE = 0x40; /* P33 is used as IRQ pin */
+ MPC.P34PFS.BYTE = 0x40; /* P34 is used as IRQ pin */
+
+#elif defined(PLATFORM_BOARD_RSKRX111)
+
+ /* The switches on the RSKRX210 are connected to the following pins/IRQ's
+ Switch Port IRQ
+ ------ ---- ----
+ SW1 P3.0 IRQ0
+ SW2 P3.1 IRQ1
+ SW3 PE.4 IRQ4
+ */
+
+ MPC.P30PFS.BYTE = 0x40; /* P30 is used as IRQ pin */
+ MPC.P31PFS.BYTE = 0x40; /* P31 is used as IRQ pin */
+ MPC.PE4PFS.BYTE = 0x40; /* PE4 is used as IRQ pin */
+
+ #endif
+
+
+ /* Set IRQ type (falling edge) */
+ ICU.IRQCR[SW1_IRQ_NUMBER].BIT.IRQMD = 0x01;
+ ICU.IRQCR[SW2_IRQ_NUMBER].BIT.IRQMD = 0x01;
+ ICU.IRQCR[SW3_IRQ_NUMBER].BIT.IRQMD = 0x01;
+
+ /* Set interrupt priorities which muse be below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ _IPR( X_IRQ(SW1_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+ _IPR( X_IRQ(SW2_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+ _IPR( X_IRQ(SW3_IRQ_NUMBER) ) = configKERNEL_INTERRUPT_PRIORITY;
+
+ /* Clear any pending interrupts */
+ _IR( X_IRQ(SW1_IRQ_NUMBER) ) = 0;
+ _IR( X_IRQ(SW2_IRQ_NUMBER) ) = 0;
+ _IR( X_IRQ(SW3_IRQ_NUMBER) ) = 0;
+
+ /* Enable the interrupts */
+ _IEN( X_IRQ(SW1_IRQ_NUMBER) ) = 1;
+ _IEN( X_IRQ(SW2_IRQ_NUMBER) ) = 1;
+ _IEN( X_IRQ(SW3_IRQ_NUMBER) ) = 1;
+
+#else
+
+ /* This is based upon having 3 counts at 10Hz. */
+ g_sw_debounce_cnts = debounce_counts;
+
+ /* Init debounce structures. */
+ for (i = 0; i < SWITCHES_NUM; i++)
+ {
+ g_switches[i].active = false;
+ g_switches[i].debounce_cnt = 0;
+ }
+
+#endif /* SWITCHES_DETECTION_MODE */
+
+}
+
+/* Only define interrupts in interrupt detection mode. */
+#if SWITCHES_DETECTION_MODE == 0
+
+ #if defined(SW1_CALLBACK_FUNCTION)
+/***********************************************************************************************************************
+* Function name: sw1_isr
+* Description : Sample ISR for switch 1 input (must do hardware setup first!)
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+#pragma interrupt (sw1_isr (vect=_VECT(X_IRQ(SW1_IRQ_NUMBER))))
+static void sw1_isr (void)
+{
+ /* TODO: Add some debouncing! */
+
+ /* Call callback function. */
+ SW1_CALLBACK_FUNCTION();
+}
+ #endif /* SW1_CALLBACK_FUNCTION */
+
+ #if defined(SW2_CALLBACK_FUNCTION)
+/***********************************************************************************************************************
+* Function name: sw2_isr
+* Description : Sample ISR for switch 2 input (must do hardware setup first!)
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+#pragma interrupt (sw2_isr (vect=_VECT(X_IRQ(SW2_IRQ_NUMBER))))
+static void sw2_isr (void)
+{
+ /* TODO: Add some debouncing! */
+
+ /* Call callback function. */
+ SW2_CALLBACK_FUNCTION();
+}
+ #endif /* SW2_CALLBACK_FUNCTION */
+
+ #if defined(SW3_CALLBACK_FUNCTION)
+/***********************************************************************************************************************
+* Function name: sw3_isr
+* Description : Sample ISR for switch 3 input (must do hardware setup first!)
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+#pragma interrupt (sw3_isr (vect=_VECT(X_IRQ(SW3_IRQ_NUMBER))))
+static void sw3_isr (void)
+{
+ /* TODO: Add some debouncing! */
+
+ /* Call callback function. */
+ SW3_CALLBACK_FUNCTION();
+}
+ #endif /* SW3_CALLBACK_FUNCTION */
+
+#endif
+
+/* If using polling then the user must call the update function. */
+
+/***********************************************************************************************************************
+* Function name: R_SWITCHES_Update
+* Description : Polls switches and calls callback functions as needed. If you are using IRQ mode then this function
+* is not needed and can be removed if desired. It is left in so that code will not fail when switching
+* between polling or IRQ mode.
+* Arguments : none
+* Return value : none
+***********************************************************************************************************************/
+void R_SWITCHES_Update (void)
+{
+#if SWITCHES_DETECTION_MODE == 1
+ /* This code is only needed for polling mode. */
+ /* Check switch 1. */
+ if (SW1 == SW_ACTIVE)
+ {
+ if (g_switches[0].active != true)
+ {
+ if (++g_switches[0].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[0].active = true;
+
+ /* Call callback function. */
+ SW1_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[0].debounce_cnt)
+ {
+ g_switches[0].active = false;
+ }
+ else
+ {
+ g_switches[0].debounce_cnt--;
+ }
+ }
+
+ /* Check switch 2. */
+ if (SW2 == SW_ACTIVE)
+ {
+ if (g_switches[1].active != true)
+ {
+ if (++g_switches[1].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[1].active = true;
+
+ /* Call callback function. */
+ SW2_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[1].debounce_cnt)
+ {
+ g_switches[1].active = false;
+ }
+ else
+ {
+ g_switches[1].debounce_cnt--;
+ }
+ }
+
+ /* Check switch 3. */
+ if (SW3 == SW_ACTIVE)
+ {
+ if (g_switches[2].active != true)
+ {
+ if (++g_switches[2].debounce_cnt >= g_sw_debounce_cnts)
+ {
+ /* Set this to true so we only call the callback function once per press. */
+ g_switches[2].active = true;
+
+ /* Call callback function. */
+ SW3_CALLBACK_FUNCTION();
+ }
+ }
+ }
+ else
+ {
+ if (0 == g_switches[2].debounce_cnt)
+ {
+ g_switches[2].active = false;
+ }
+ else
+ {
+ g_switches[2].debounce_cnt--;
+ }
+ }
+#endif /* SWITCHES_DETECTION_MODE */
+}
+
+
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c
new file mode 100644
index 000000000..b3a8ad895
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main.c
@@ -0,0 +1,204 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ * This project provides two demo applications. A low power project that
+ * demonstrates the FreeRTOS tickless mode, and a more comprehensive test and
+ * demo application. The configCREATE_LOW_POWER_DEMO setting (defined at the
+ * top of FreeRTOSConfig.h) is used to select between the two. The low power
+ * demo is implemented and described in main_low_power.c. The more
+ * comprehensive test and demo application is implemented and described in
+ * main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Platform includes. */
+#include "lcd.h"
+
+/*-----------------------------------------------------------*/
+
+/*
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.
+ */
+extern void main_low_power( void );
+extern void main_full( void );
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file. */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* See the documentation page for this demo on the FreeRTOS.org web site for
+full information - including hardware setup requirements. */
+
+void main( void )
+{
+ lcd_initialize();
+ lcd_display( LCD_LINE1, "FreeRTOS" );
+
+ /* The configCREATE_LOW_POWER_DEMO setting is described in FreeRTOSConfig.h. */
+ #if configCREATE_LOW_POWER_DEMO == 1
+ {
+ lcd_display( LCD_LINE2, "LP Demo" );
+ main_low_power();
+ }
+ #else
+ {
+ lcd_display( LCD_LINE2, "Ful Demo" );
+ main_full();
+ }
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the size
+ of the heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE
+ in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
+ called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* This function will be called by each tick interrupt if
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
+ added here, but the tick hook is called from an interrupt context, so
+ code must not attempt to block, and only the interrupt safe FreeRTOS API
+ functions can be used (those that end in FromISR()). */
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile unsigned long ul = 0;
+
+ taskENTER_CRITICAL();
+ {
+ /* Set ul to a non-zero value using the debugger to step out of this
+ function. */
+ while( ul == 0 )
+ {
+ nop();
+ }
+ }
+ taskEXIT_CRITICAL();
+}
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c
new file mode 100644
index 000000000..a6dd16a8f
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_full.c
@@ -0,0 +1,531 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* ****************************************************************************
+ * This project includes a lot of tasks and tests and is therefore complex.
+ * If you would prefer a much simpler project to get started with then select
+ * the 'low power' demo by setting configCREATE_LOW_POWER_DEMO to 1 in
+ * FreeRTOSConfig.h. When configCREATE_LOW_POWER_DEMO is set to 1 main() will
+ * call main_low_power() instead of main_full().
+ * ****************************************************************************
+ *
+ * Creates all the demo application tasks, then starts the scheduler. The web
+ * documentation provides more details of the standard demo application tasks,
+ * which provide no particular functionality but do provide a good example of
+ * how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill the registers with known values, then
+ * repeatedly check that each register still contains its expected value for
+ * the lifetime of the tasks. Each task uses different values. The tasks run
+ * with very low priority so get preempted very frequently. A check variable
+ * is incremented on each iteration of the test loop. A register containing an
+ * unexpected value is indicative of an error in the context switching
+ * mechanism and will result in a branch to a null loop - which in turn will
+ * prevent the check variable from incrementing any further and allow the check
+ * timer (described below) to determine that an error has occurred. The nature
+ * of the reg test tasks necessitates that they are written in assembly code.
+ *
+ * "Check Timer" and Callback Function - The check timer period is initially
+ * set to three seconds. The check timer callback function checks that all the
+ * standard demo tasks are not only still executing, but are executing without
+ * reporting any errors. If the check timer discovers that a task has either
+ * stalled, or reported an error, then it changes its own period from the
+ * initial three seconds, to just 200ms. The check timer callback function
+ * also toggles LED 0 each time it is called. This provides a visual
+ * indication of the system status: If the LED toggles every three seconds,
+ * then no issues have been discovered. If the LED toggles every 200ms, then
+ * an issue has been discovered with at least one task.
+ *
+ * *NOTE 1* The CPU must be in Supervisor mode when the scheduler is started.
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.
+*/
+
+/* Standard includes. */
+#include
+
+/* Hardware specific includes. */
+#include "iodefine.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo includes. */
+#include "partest.h"
+#include "death.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+
+/* The code in this file is only built when configCREATE_LOW_POWER_DEMO is set
+to 0, otherwise the code in main_low_power.c is used. */
+#if configCREATE_LOW_POWER_DEMO == 0
+
+
+/* Values that are passed into the reg test tasks using the task parameter.
+The tasks check that the values are passed in correctly. */
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )
+
+/* Priorities at which the standard demo tasks are created. */
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+
+/* The LED toggled by the check timer. */
+#define mainCHECK_LED ( 0 )
+
+/* The period at which the check timer will expire, in ms, provided no errors
+have been reported by any of the standard demo tasks. ms are converted to the
+equivalent in ticks using the portTICK_RATE_MS constant. */
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
+
+/* The period at which the check timer will expire, in ms, if an error has been
+reported in one of the standard demo tasks. ms are converted to the equivalent
+in ticks using the portTICK_RATE_MS constant. */
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
+
+/* A block time of zero simple means "Don't Block". */
+#define mainDONT_BLOCK ( 0UL )
+
+/*
+ * The reg test tasks as described at the top of this file.
+ */
+static void prvRegTest1Task( void *pvParameters );
+static void prvRegTest2Task( void *pvParameters );
+
+/*
+ * The actual implementation of the reg test functionality, which, because of
+ * the direct register access, have to be in assembly.
+ */
+static void prvRegTest1Implementation( void );
+static void prvRegTest2Implementation( void );
+
+/*
+ * The check timer callback function, as described at the top of this file.
+ */
+static void prvCheckTimerCallback( xTimerHandle xTimer );
+
+
+/*-----------------------------------------------------------*/
+
+/* Variables that are incremented on each iteration of the reg test tasks -
+provided the tasks have not reported any errors. The check timer inspects these
+variables to ensure they are still incrementing as expected. If a variable
+stops incrementing then it is likely that its associated task has stalled. */
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;
+
+/* The check timer. This uses prvCheckTimerCallback() as its callback
+function. */
+static xTimerHandle xCheckTimer = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+ /* Start the reg test tasks which test the context switching mechanism. */
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+ /* Create the standard demo tasks. */
+ vCreateBlockTimeTasks();
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
+ vStartRecursiveMutexTasks();
+
+ /* The suicide tasks must be created last as they need to know how many
+ tasks were running prior to their creation in order to ascertain whether
+ or not the correct/expected number of tasks are running at any given time. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Create the software timer that performs the 'check' functionality,
+ as described at the top of this file. */
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
+ );
+
+ configASSERT( xCheckTimer );
+
+ /* Start the check timer. It will actually start when the scheduler is
+ started. */
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );
+
+ /* Start the tasks running. */
+ vTaskStartScheduler();
+
+ /* If all is well execution will never reach here as the scheduler will be
+ running. If this null loop is reached then it is likely there was
+ insufficient FreeRTOS heap available for the idle task and/or timer task to
+ be created. See http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTimerCallback( xTimerHandle xTimer )
+{
+static long lChangedTimerPeriodAlready = pdFALSE, lErrorStatus = pdPASS;
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;
+
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) xTimer;
+
+ /* Check the standard demo tasks are running without error. */
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ /* Check the reg test tasks are still cycling. They will stop incrementing
+ their loop counters if they encounter an error. */
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )
+ {
+ lErrorStatus = pdFAIL;
+ }
+
+ /* Remember the loop counter values this time around so they can be checked
+ again the next time this callback function executes. */
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;
+
+ /* Toggle the check LED to give an indication of the system status. If
+ the LED toggles every three seconds then everything is ok. A faster toggle
+ indicates an error. */
+ vParTestToggleLED( mainCHECK_LED );
+
+ /* Was an error detected this time through the callback execution? */
+ if( lErrorStatus != pdPASS )
+ {
+ if( lChangedTimerPeriodAlready == pdFALSE )
+ {
+ lChangedTimerPeriodAlready = pdTRUE;
+
+ /* This call to xTimerChangePeriod() uses a zero block time.
+ Functions called from inside of a timer callback function must
+ *never* attempt to block. */
+ xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest1Task( void *pvParameters )
+{
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )
+ {
+ /* The parameter did not contain the expected value. */
+ for( ;; )
+ {
+ /* Stop the tick interrupt so its obvious something has gone wrong. */
+ taskDISABLE_INTERRUPTS();
+ }
+ }
+
+ /* This is an inline asm function that never returns. */
+ prvRegTest1Implementation();
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+static void prvRegTest2Task( void *pvParameters )
+{
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )
+ {
+ /* The parameter did not contain the expected value. */
+ for( ;; )
+ {
+ /* Stop the tick interrupt so its obvious something has gone wrong. */
+ taskDISABLE_INTERRUPTS();
+ }
+ }
+
+ /* This is an inline asm function that never returns. */
+ prvRegTest2Implementation();
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+#pragma inline_asm prvRegTest1Implementation
+static void prvRegTest1Implementation( void )
+{
+ ; Put a known value in each register.
+ MOV.L #11111111H, R15
+ MVTACHI R15
+ MOV.L #22222222H, R15
+ MVTACLO R15
+ MOV.L #1, R1
+ MOV.L #2, R2
+ MOV.L #3, R3
+ MOV.L #4, R4
+ MOV.L #5, R5
+ MOV.L #6, R6
+ MOV.L #7, R7
+ MOV.L #8, R8
+ MOV.L #9, R9
+ MOV.L #10, R10
+ MOV.L #11, R11
+ MOV.L #12, R12
+ MOV.L #13, R13
+ MOV.L #14, R14
+ MOV.L #15, R15
+
+ ; Loop, checking each iteration that each register still contains the
+ ; expected value.
+TestLoop1:
+
+ ; Push the registers that are going to get clobbered.
+ PUSHM R14-R15
+
+ ; Increment the loop counter to show this task is still getting CPU time.
+ MOV.L #_ulRegTest1CycleCount, R14
+ MOV.L [ R14 ], R15
+ ADD #1, R15
+ MOV.L R15, [ R14 ]
+
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.
+ MOV.L #1, R14
+ MOV.L #0872E0H, R15
+ MOV.B R14, [R15]
+ NOP
+ NOP
+
+ ;Check the accumulator value.
+ MVFACHI R15
+ CMP #11111111H, R15
+ BNE RegTest2Error
+ MVFACMI R15
+ CMP #11112222H, R15
+ BNE RegTest2Error
+
+ ; Restore the clobbered registers.
+ POPM R14-R15
+
+ ; Now compare each register to ensure it still contains the value that was
+ ; set before this loop was entered.
+ CMP #1, R1
+ BNE RegTest1Error
+ CMP #2, R2
+ BNE RegTest1Error
+ CMP #3, R3
+ BNE RegTest1Error
+ CMP #4, R4
+ BNE RegTest1Error
+ CMP #5, R5
+ BNE RegTest1Error
+ CMP #6, R6
+ BNE RegTest1Error
+ CMP #7, R7
+ BNE RegTest1Error
+ CMP #8, R8
+ BNE RegTest1Error
+ CMP #9, R9
+ BNE RegTest1Error
+ CMP #10, R10
+ BNE RegTest1Error
+ CMP #11, R11
+ BNE RegTest1Error
+ CMP #12, R12
+ BNE RegTest1Error
+ CMP #13, R13
+ BNE RegTest1Error
+ CMP #14, R14
+ BNE RegTest1Error
+ CMP #15, R15
+ BNE RegTest1Error
+
+ ; All comparisons passed, start a new iteration of this loop.
+ BRA TestLoop1
+
+RegTest1Error:
+ ; A compare failed, just loop here so the loop counter stops incrementing
+ ; causing the check timer to indicate the error.
+ BRA RegTest1Error
+}
+/*-----------------------------------------------------------*/
+
+/* This function is explained in the comments at the top of this file. */
+#pragma inline_asm prvRegTest2Implementation
+static void prvRegTest2Implementation( void )
+{
+ ; Put a known value in each register.
+ MOV.L #33333333H, R15
+ MVTACHI R15
+ MOV.L #44444444H, R15
+ MVTACLO R15
+ MOV.L #10, R1
+ MOV.L #20, R2
+ MOV.L #30, R3
+ MOV.L #40, R4
+ MOV.L #50, R5
+ MOV.L #60, R6
+ MOV.L #70, R7
+ MOV.L #80, R8
+ MOV.L #90, R9
+ MOV.L #100, R10
+ MOV.L #110, R11
+ MOV.L #120, R12
+ MOV.L #130, R13
+ MOV.L #140, R14
+ MOV.L #150, R15
+
+ ; Loop, checking on each iteration that each register still contains the
+ ; expected value.
+TestLoop2:
+
+ ; Push the registers that are going to get clobbered.
+ PUSHM R14-R15
+
+ ; Increment the loop counter to show this task is still getting CPU time.
+ MOV.L #_ulRegTest2CycleCount, R14
+ MOV.L [ R14 ], R15
+ ADD #1, R15
+ MOV.L R15, [ R14 ]
+
+ ;Check the accumulator value.
+ MVFACHI R15
+ CMP #33333333H, R15
+ BNE RegTest2Error
+ MVFACMI R15
+ CMP #33334444H, R15
+ BNE RegTest2Error
+
+ ; Restore the clobbered registers.
+ POPM R14-R15
+
+ CMP #10, R1
+ BNE RegTest2Error
+ CMP #20, R2
+ BNE RegTest2Error
+ CMP #30, R3
+ BNE RegTest2Error
+ CMP #40, R4
+ BNE RegTest2Error
+ CMP #50, R5
+ BNE RegTest2Error
+ CMP #60, R6
+ BNE RegTest2Error
+ CMP #70, R7
+ BNE RegTest2Error
+ CMP #80, R8
+ BNE RegTest2Error
+ CMP #90, R9
+ BNE RegTest2Error
+ CMP #100, R10
+ BNE RegTest2Error
+ CMP #110, R11
+ BNE RegTest2Error
+ CMP #120, R12
+ BNE RegTest2Error
+ CMP #130, R13
+ BNE RegTest2Error
+ CMP #140, R14
+ BNE RegTest2Error
+ CMP #150, R15
+ BNE RegTest2Error
+
+ ; All comparisons passed, start a new itteratio of this loop.
+ BRA TestLoop2
+
+RegTest2Error:
+ ; A compare failed, just loop here so the loop counter stops incrementing
+ ; - causing the check timer to indicate the error.
+ BRA RegTest2Error
+}
+/*-----------------------------------------------------------*/
+
+#endif /* configCREATE_LOW_POWER_DEMO */
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c
new file mode 100644
index 000000000..989f4c302
--- /dev/null
+++ b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/RTOSDemo/main_low_power.c
@@ -0,0 +1,436 @@
+/*
+ FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ details. You should have received a copy of the GNU General Public License
+ and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+ viewed here: http://www.freertos.org/a00114.html and also obtained by
+ writing to Real Time Engineers Ltd., contact details for whom are available
+ on the FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new
+ fully thread aware and reentrant UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems, who sell the code with commercial support,
+ indemnification and middleware, under the OpenRTOS brand.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+*/
+
+/* ****************************************************************************
+ * When configCREATE_LOW_POWER_DEMO is set to 1 in FreeRTOSConfig.h main() will
+ * call main_low_power(), which is defined in this file. main_low_power()
+ * demonstrates FreeRTOS tick suppression being used to allow the MCU to be
+ * placed into both the low power deep sleep mode and the low power software
+ * standby mode. When configCREATE_LOW_POWER_DEMO is set to 0 main will
+ * instead call main_full(), which is a more comprehensive RTOS demonstration.
+ * ****************************************************************************
+ *
+ * This application demonstrates the FreeRTOS tickless idle mode (tick
+ * suppression). See http://www.freertos.org/low-power-tickless-rtos.html
+ * The demo is configured to execute on the Renesas RX100 RSK.
+ *
+ * Functionality:
+ *
+ * + Two tasks are created, an Rx task and a Tx task.
+ *
+ * + The Rx task repeatedly blocks on a queue to wait for data. The Rx task
+ * toggles LED 0 each time is receives a value from the queue.
+ *
+ * + The Tx task repeatedly enters the Blocked state for an amount of time
+ * that is set by the position of the potentiometer. On exiting the blocked
+ * state the Tx task sends a value through the queue to the Rx task (causing
+ * the Rx task to exit the blocked state and toggle LED 0).
+ *
+ * If the value read from the potentiometer is less than or equal to
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks for the equivalent
+ * number of milliseconds. For example, if the sampled analog value is
+ * 2000, then the Tx task blocks for 2000ms. Blocking for a finite period
+ * allows the kernel to stop the tick interrupt and place the RX100 into
+ * deep sleep mode.
+ *
+ * If the value read form the potentiometer is greater than
+ * mainSOFTWARE_STANDBY_DELAY then the Tx task blocks on a semaphore with
+ * an infinite timeout. Blocking with an infinite timeout allows the kernel
+ * to stop the tick interrupt and place the RX100 into software standby
+ * mode. Pressing a button will generate an interrupt that causes the RX100
+ * to exit software standby mode. The interrupt service routine 'gives' the
+ * semaphore to unblock the Tx task.
+ *
+ *
+ * Using the Demo and Observed Behaviour:
+ *
+ * 1) Turn the potentiometer completely counter clockwise.
+ *
+ * 2) Program the RX100 with the application, then disconnect the programming/
+ * debugging hardware to ensure power readings are not effected by any
+ * connected interfaces.
+ *
+ * 3) Start the application running. LED 0 will toggle quickly because the
+ * potentiometer is turned to its lowest value. LED 1 will be illuminated
+ * when the RX100 is not in a power saving mode, but will appear to be off
+ * because most execution time is spent in a sleep mode. Led 2 will be
+ * illuminated when the RX100 is in deep sleep mode, and will appear to be
+ * always on, again because most execution time is spent in deep sleep mode.
+ * The LEDs are turned on and off by the application defined pre and post
+ * sleep macros (see the definitions of configPRE_SLEEP_PROCESSING() and
+ * configPOST_SLEEP_PROCESSING() in FreeRTOSConfig.h).
+ *
+ * 4) Slowly turn the potentiometer in the clockwise direction. This will
+ * increase the value read from the potentiometer, which will increase the
+ * time the Tx task spends in the Blocked state, which will therefore
+ * decrease the frequency at which the Tx task sends data to the queue (and
+ * the rate at which LED 0 is toggled).
+ *
+ * 5) Keep turning the potentiometer in the clockwise direction. Eventually
+ * the value read from the potentiometer will go above
+ * mainSOFTWARE_STANDBY_DELAY, causing the Tx task to block on the semaphore
+ * with an infinite timeout. LED 0 will stop toggling because the Tx task is
+ * no longer sending to the queue. LED 1 and LED 2 will both be off because
+ * the RX100 is neither running or in deep sleep mode (it is in software
+ * standby mode).
+ *
+ * 6) Turn the potentiometer counter clockwise again to ensure its value goes
+ * back below mainSOFTWARE_STANDBY_DELAY.
+ *
+ * 7) Press any of the three buttons to generate an interrupt. The interrupt
+ * will take the RX100 out of software standby mode, and the interrupt
+ * service routine will unblock the Tx task by 'giving' the semaphore. LED 0
+ * will then start to toggle again.
+ *
+ */
+
+
+/* Hardware specific includes. */
+#include "platform.h"
+#include "r_switches_if.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Common demo includes. */
+#include "partest.h"
+
+/* Priorities at which the Rx and Tx tasks are created. */
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+
+/* The number of items the queue can hold. This is 1 as the Rx task will
+remove items as they are added so the Tx task should always find the queue
+empty. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/* The LED used to indicate that a value has been received on the queue. */
+#define mainQUEUE_LED ( 0 )
+
+/* The LED used to indicate that full power is being used (the MCU is not in
+deep sleep or software standby mode). */
+#define mainFULL_POWER_LED ( 1 )
+
+/* The LED used to indicate that deep sleep mode is being used. */
+#define mainDEEP_SLEEP_LED ( 2 )
+
+/* The Tx task sends to the queue with a frequency that is set by the value
+read from the potentiometer until the value goes above that set by the
+mainSOFTWARE_STANDBY_DELAY constant - at which time the Tx task instead blocks
+indefinitely on a semaphore. */
+#define mainSOFTWARE_STANDBY_DELAY ( 3000UL )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK ( 0 )
+
+/* The value that is sent from the Tx task to the Rx task on the queue. */
+#define mainQUEUED_VALUE ( 100UL )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The Rx and Tx tasks as described at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Reads and returns the value of the ADC connected to the potentiometer built
+ * onto the RSK.
+ */
+static unsigned short prvReadPOT( void );
+
+/*
+ * The handler for the interrupt generated when any of the buttons are pressed.
+ */
+void vButtonInterruptCallback( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue to pass data from the Tx task to the Rx task. */
+static xQueueHandle xQueue = NULL;
+
+/* The semaphore that is 'given' by interrupts generated from button pushes. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_low_power( void )
+{
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+ configASSERT( xQueue );
+
+ /* Create the semaphore that is 'given' by an interrupt generated from a
+ button push. */
+ vSemaphoreCreateBinary( xSemaphore );
+ configASSERT( xSemaphore );
+
+ /* Make sure the semaphore starts in the expected state - no button pushes
+ have yet occurred. A block time of zero can be used as it is guaranteed
+ that the semaphore will be available because it has just been created. */
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );
+
+ /* Start the two tasks as described at the top of this file. */
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* The CPU is currently running, not sleeping, so turn on the LED that
+ shows the CPU is not in a sleep mode. */
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );
+
+ /* Start the scheduler running running. */
+ vTaskStartScheduler();
+
+ /* If all is well the next line of code will not be reached as the
+ scheduler will be running. If the next line is reached then it is likely
+ there was insufficient FreeRTOS heap available for the idle task and/or
+ timer task to be created. See http://www.freertos.org/a00111.html. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xDelay;
+const unsigned long ulValueToSend = mainQUEUED_VALUE;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* The delay period between successive sends to the queue is set by
+ the potentiometer reading. */
+ xDelay = ( portTickType ) prvReadPOT();
+
+ /* If the block time is greater than 3000 milliseconds then block
+ indefinitely waiting for a button push. */
+ if( xDelay > mainSOFTWARE_STANDBY_DELAY )
+ {
+ /* As this is an indefinite delay the kernel will place the CPU
+ into software standby mode the next time the idle task runs. */
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );
+ }
+ else
+ {
+ /* Convert a time in milliseconds to a time in ticks. */
+ xDelay /= portTICK_RATE_MS;
+
+ /* Place this task in the blocked state until it is time to run
+ again. As this is not an indefinite sleep the kernel will place
+ the CPU into the deep sleep state when the idle task next runs. */
+ vTaskDelay( xDelay );
+ }
+
+ /* Send to the queue - causing the queue receive task to flash its LED.
+ It should not be necessary to block on the queue send because the Rx
+ task will have removed the last queued item. */
+ xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have arrived, but is it the expected
+ value? If it is, toggle the LED. */
+ if( ulReceivedValue == mainQUEUED_VALUE )
+ {
+ vParTestToggleLED( mainQUEUE_LED );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPreSleepProcessing( unsigned long ulExpectedIdleTime )
+{
+ /* Called by the kernel before it places the MCU into a sleep mode because
+ configPRE_SLEEP_PROCESSING() is #defined to vPreSleepProcessing().
+
+ NOTE: Additional actions can be taken here to get the power consumption
+ even lower. For example, the ADC input used by this demo could be turned
+ off here, and then back on again in the power sleep processing function.
+ For maximum power saving ensure all unused pins are in their lowest power
+ state. */
+
+ /* Avoid compiler warnings about the unused parameter. */
+ ( void ) ulExpectedIdleTime;
+
+ /* Is the MCU about to enter deep sleep mode or software standby mode? */
+ if( SYSTEM.SBYCR.BIT.SSBY == 0 )
+ {
+ /* Turn on the LED that indicates deep sleep mode is being entered. */
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdTRUE );
+ }
+ else
+ {
+ /* Software standby mode is being used, so no LEDs are illuminated to
+ ensure minimum power readings are obtained. Ensure the Queue LED is
+ also off. */
+ vParTestSetLED( mainQUEUE_LED, pdFALSE );
+ }
+
+ /* Turn off the LED that indicates full power is being used. */
+ vParTestSetLED( mainFULL_POWER_LED, pdFALSE );
+}
+/*-----------------------------------------------------------*/
+
+void vPostSleepProcessing( unsigned long ulExpectedIdleTime )
+{
+ /* Called by the kernel when the MCU exits a sleep mode because
+ configPOST_SLEEP_PROCESSING is #defined to vPostSleepProcessing(). */
+
+ /* Avoid compiler warnings about the unused parameter. */
+ ( void ) ulExpectedIdleTime;
+
+ /* Turn off the LED that indicates deep sleep mode, and turn on the LED
+ that indicates full power is being used. */
+ vParTestSetLED( mainDEEP_SLEEP_LED, pdFALSE );
+ vParTestSetLED( mainFULL_POWER_LED, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+static unsigned short prvReadPOT( void )
+{
+unsigned short usADCValue;
+const unsigned short usMinADCValue = 128;
+
+ /* Start an ADC scan. */
+ S12AD.ADCSR.BIT.ADST = 1;
+ while( S12AD.ADCSR.BIT.ADST == 1 )
+ {
+ /* Just waiting for the ADC scan to complete. Inefficient
+ polling! */
+ }
+
+ usADCValue = S12AD.ADDR4;
+
+ /* Don't let the ADC value get too small as the LED behaviour will look
+ erratic. */
+ if( usADCValue < usMinADCValue )
+ {
+ usADCValue = usMinADCValue;
+ }
+
+ return usADCValue;
+}
+/*-----------------------------------------------------------*/
+
+void vButtonInterruptCallback( void )
+{
+long lHigherPriorityTaskWoken = pdFALSE;
+
+ /* The semaphore is only created when the build is configured to create the
+ low power demo. */
+ if( xSemaphore != NULL )
+ {
+ /* This interrupt will bring the CPU out of deep sleep and software
+ standby modes. Give the semaphore that was used to place the Tx task
+ into an indefinite sleep. */
+ if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )
+ {
+ xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );
+ }
+ else
+ {
+ /* The semaphore was already available, so the task is not blocked
+ on it and there is no point giving it. */
+ }
+
+ /* If giving the semaphore caused a task to leave the Blocked state,
+ and the task that left the Blocked state has a priority equal to or
+ above the priority of the task that this interrupt interrupted, then
+ lHigherPriorityTaskWoken will have been set to pdTRUE inside the call
+ to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause
+ a context switch to the unblocked task. */
+ portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
+ }
+}
+
diff --git a/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/custom.bat b/FreeRTOS/Demo/RX100-RSK_Renesas_e2studio/custom.bat
new file mode 100644
index 000000000..e69de29bb