len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2026-02-22 18:15:29 -05:00
Code Issues Projects Releases Packages Wiki Activity

Update Cortex-A port layers to ensure the ICCRPR and ICCPMR registers are always accessed as 32-bit values.

Browse source
This commit is contained in:
Richard Barry 2014-03-25 17:12:31 +00:00
parent d59bf60ff9
commit 29a08b5e24
6 changed files with 20 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

10
FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
View file

@ -123,7 +123,7 @@ this value. */
/* In all GICs 255 can be written to the priority mask register to unmask all
(but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFF )
#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
floating point context after they have been created. A variable is stored as
@ -344,7 +344,7 @@ void FreeRTOS_Tick_Handler( void )
handler runs at the lowest priority, so interrupts cannot already be masked,
so there is no need to save and restore the current mask value. */
__disable_irq();
portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm( "DSB \n"
"ISB \n" );
__enable_irq();
@ -388,7 +388,7 @@ uint32_t ulPortSetInterruptMask( void )
uint32_t ulReturn;
__disable_irq();
if( portICCPMR_PRIORITY_MASK_REGISTER == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
ulReturn = pdTRUE;
@ -396,7 +396,7 @@ uint32_t ulReturn;
else
{
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm( "DSB \n"
"ISB \n" );
}
@ -428,7 +428,7 @@ uint32_t ulReturn;
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
that define each interrupt's priority to be split between bits that