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Baseline new GCC and Renesas compiler projects for RX71M and RX113 before adding IAR projects.

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Richard Barry 2015-09-22 08:45:15 +00:00
parent b71bb46a5b
commit 27ff871a37
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148
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.HardwareDebuglinker Normal file
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<stringAttribute key="com.renesas.hardwaredebug.e1.hook_start_func" value="0x0"/>
<intAttribute key="com.renesas.hardwaredebug.e1.hook_work_ram_Addr" value="4096"/>
<intAttribute key="com.renesas.hardwaredebug.e1.hook_work_ram_Size" value="560"/>
<booleanAttribute key="com.renesas.hardwaredebug.e1.hw_break" value="true"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.inputclock" value="27.0000"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.clock.freq" value="16.5"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.or.fine" value="0"/>
<booleanAttribute key="com.renesas.hardwaredebug.e1.le" value="true"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.mode" value="0"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.mode_pin" value="0"/>
<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_dflash" value="false"/>
<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_irom" value="false"/>
<stringAttribute key="com.renesas.hardwaredebug.e1.serial_number" value=""/>
<stringAttribute key="com.renesas.hardwaredebug.e1.supply.voltage" value="3.3V"/>
<intAttribute key="com.renesas.hardwaredebug.e1.timer_clock" value="120000000"/>
<intAttribute key="com.renesas.hardwaredebug.e1.work_ram_start" value="4096"/>
<booleanAttribute key="com.renesas.hardwaredebug.e20.le" value="true"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_GCC_e2studio\HardwareDebug\RTOSDemo.x"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_GCC_e2studio\HardwareDebug\RTOSDemo.x"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${eclipse_home}../DebugComp/rx-elf-gdb --rx-force-64bit-double -rx-force-v2"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="HardwareDebug\RTOSDemo.x"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.363159113"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RTOSDemo"/>
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<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
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<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

0
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas Normal file
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0
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/custom.bat Normal file
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5
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/makefile.init Normal file
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@ -0,0 +1,5 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
PATH := $(PATH):C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\bin;C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\libexec\gcc\rx-elf\4.8-GNURX_v15.01

235
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c Normal file
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@ -0,0 +1,235 @@
/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles an LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Kernel includes. */
#include <rskrx71mdef.h>
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Renesas includes. */
#include "r_cg_macrodriver.h"
#include "r_cg_userdefine.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_PERIOD_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/*
* Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
* main.c.
*/
void main_blinky( void );
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
const unsigned long ulExpectedValue = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
LED0 = !LED0;
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

182
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h Normal file
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@ -0,0 +1,182 @@
/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* Renesas hardware definition header. */
#include "iodefine.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess*/
#define configPERIPHERAL_CLOCK_HZ ( 60000000UL ) /*_RB_ guess*/
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 12 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_CO_ROUTINES 0
#define configUSE_MUTEXES 1
#define configGENERATE_RUN_TIME_STATS 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_QUEUE_SETS 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configMAX_PRIORITIES ( 7 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* The interrupt priority used by the kernel itself for the tick interrupt and
the pended interrupt. This would normally be the lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY 1
/* The maximum interrupt priority from which FreeRTOS API calls can be made.
Interrupts that use a priority above this will not be effected by anything the
kernel is doing. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
/* The peripheral used to generate the tick interrupt is configured as part of
the application code. This constant should be set to the vector number of the
peripheral chosen. As supplied this is CMT0. */
#define configTICK_VECTOR _CMT0_CMI0
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
void vAssertCalled( void );
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Override some of the priorities set in the common demo tasks. This is
required to ensure flase positive timing errors are not reported. */
#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 )
#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 )
/*-----------------------------------------------------------
* Ethernet configuration.
*-----------------------------------------------------------*/
/* MAC address configuration. */
#define configMAC_ADDR0 0x00
#define configMAC_ADDR1 0x12
#define configMAC_ADDR2 0x13
#define configMAC_ADDR3 0x10
#define configMAC_ADDR4 0x15
#define configMAC_ADDR5 0x11
/* IP address configuration. */
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR3 200
/* Netmask configuration. */
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
#endif /* FREERTOS_CONFIG_H */

188
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c Normal file
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@ -0,0 +1,188 @@
/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
* This file contains the non-portable and therefore RX62N specific parts of
* the IntQueue standard demo task - namely the configuration of the timers
* that generate the interrupts and the interrupt entry points.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo includes. */
#include "IntQueueTimer.h"
#include "IntQueue.h"
/* Hardware specifics. */
#include "iodefine.h"
#define IPR_PERIB_INTB128 128
#define IPR_PERIB_INTB129 129
#define IER_PERIB_INTB128 0x10
#define IER_PERIB_INTB129 0x10
#define IEN_PERIB_INTB128 IEN0
#define IEN_PERIB_INTB129 IEN1
#define IR_PERIB_INTB128 128
#define IR_PERIB_INTB129 129
void vIntQTimerISR0( void ) __attribute__ ((interrupt));
void vIntQTimerISR1( void ) __attribute__ ((interrupt));
#define tmrTIMER_0_1_FREQUENCY ( 2000UL )
#define tmrTIMER_2_3_FREQUENCY ( 2001UL )
void vInitialiseTimerForIntQueueTest( void )
{
/* Ensure interrupts do not start until full configuration is complete. */
portENTER_CRITICAL();
{
/* Give write access. */
SYSTEM.PRCR.WORD = 0xa502;
/* Cascade two 8bit timer channels to generate the interrupts.
8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
utilised for this test. */
/* Enable the timers. */
SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
/* Enable compare match A interrupt request. */
TMR0.TCR.BIT.CMIEA = 1;
TMR2.TCR.BIT.CMIEA = 1;
/* Clear the timer on compare match A. */
TMR0.TCR.BIT.CCLR = 1;
TMR2.TCR.BIT.CCLR = 1;
/* Set the compare match value. */
TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
/* 16 bit operation ( count from timer 1,2 ). */
TMR0.TCCR.BIT.CSS = 3;
TMR2.TCCR.BIT.CSS = 3;
/* Use PCLK as the input. */
TMR1.TCCR.BIT.CSS = 1;
TMR3.TCCR.BIT.CSS = 1;
/* Divide PCLK by 8. */
TMR1.TCCR.BIT.CKS = 2;
TMR3.TCCR.BIT.CKS = 2;
/* Enable TMR 0, 2 interrupts. */
TMR0.TCR.BIT.CMIEA = 1;
TMR2.TCR.BIT.CMIEA = 1;
/* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set
priority above the kernel's priority, but below the max syscall
priority. */
ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
IEN( PERIB, INTB128 ) = 1;
/* Ensure that the flag is set to 0, otherwise the interrupt will not be
accepted. */
IR( PERIB, INTB128 ) = 0;
/* Do the same for TMR2, but to vector 129. */
ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
IEN( PERIB, INTB129 ) = 1;
IR( PERIB, INTB129 ) = 0;
}
portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
/* On vector 128. */
void vIntQTimerISR0( void )
{
/* Enable interrupts to allow interrupt nesting. */
__asm volatile( "setpsw i" );
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
/*-----------------------------------------------------------*/
/* On vector 129. */
void vIntQTimerISR1( void )
{
/* Enable interrupts to allow interrupt nesting. */
__asm volatile( "setpsw i" );
portYIELD_FROM_ISR( xSecondTimerHandler() );
}

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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef INT_QUEUE_TIMER_H
#define INT_QUEUE_TIMER_H
void vInitialiseTimerForIntQueueTest( void );
portBASE_TYPE xTimer0Handler( void );
portBASE_TYPE xTimer1Handler( void );
#endif

302
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;/*
; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
; All rights reserved
;
; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
;
; ***************************************************************************
; * *
; * FreeRTOS provides completely free yet professionally developed, *
; * robust, strictly quality controlled, supported, and cross *
; * platform software that has become a de facto standard. *
; * *
; * Help yourself get started quickly and support the FreeRTOS *
; * project by purchasing a FreeRTOS tutorial book, reference *
; * manual, or both from: http://www.FreeRTOS.org/Documentation *
; * *
; * Thank you! *
; * *
; ***************************************************************************
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
;
; >>! NOTE: The modification to the GPL is included to allow you to distribute
; >>! a combined work that includes FreeRTOS without being obliged to provide
; >>! the source code for proprietary components outside of the FreeRTOS
; >>! kernel.
;
; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
; FOR A PARTICULAR PURPOSE. Full license text is available from the following
; link: http://www.freertos.org/a00114.html
;
; 1 tab == 4 spaces!
;
; ***************************************************************************
; * *
; * Having a problem? Start by reading the FAQ "My application does *
; * not run, what could be wrong?" *
; * *
; * http://www.FreeRTOS.org/FAQHelp.html *
; * *
; ***************************************************************************
;
; http://www.FreeRTOS.org - Documentation, books, training, latest versions,
; license and Real Time Engineers Ltd. contact details.;
;
; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
; including FreeRTOS+Trace - an indispensable productivity tool, a DOS
; compatible FAT file system, and our tiny thread aware UDP/IP stack.
;
; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
; licenses offer ticketed support, indemnification and middleware.
;
; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
; engineered and independently SIL3 certified version for use in safety and
; mission critical applications that require provable dependability.
;
; 1 tab == 4 spaces!
;*/
.global _vRegTest1Implementation
.global _vRegTest2Implementation
.extern _ulRegTest1LoopCounter
.extern _ulRegTest2LoopCounter
.text
;/* This function is explained in the comments at the top of main.c. */
_vRegTest1Implementation:
;/* Put a known value in the guard byte of the accumulators. */
MOV.L #10, R1
MVTACGU R1, A0
MOV.L #20, R1
MVTACGU R1, A1
;/* Put a known value in each register. */
MOV.L #1, R1
MOV.L #2, R2
MOV.L #3, R3
MOV.L #4, R4
MOV.L #5, R5
MOV.L #6, R6
MOV.L #7, R7
MOV.L #8, R8
MOV.L #9, R9
MOV.L #10, R10
MOV.L #11, R11
MOV.L #12, R12
MOV.L #13, R13
MOV.L #14, R14
MOV.L #15, R15
;/* Put a known value in the hi and low of the accumulators. */
MVTACHI R1, A0
MVTACLO R2, A0
MVTACHI R3, A1
MVTACLO R4, A1
;/* Loop, checking each itteration that each register still contains the
;expected value. */
TestLoop1:
;/* Push the registers that are going to get clobbered. */
PUSHM R14-R15
;/* Increment the loop counter to show this task is still getting CPU time. */
MOV.L #_ulRegTest1LoopCounter, R14
MOV.L [ R14 ], R15
ADD #1, R15
MOV.L R15, [ R14 ]
;/* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */
MOV.L #1, R14
MOV.L #0872E0H, R15
MOV.B R14, [R15]
NOP
NOP
;/* Check accumulators. */
MVFACHI #0, A0, R15
CMP #1, R15
BNE RegTest1Error
MVFACLO #0, A0, R15
CMP #2, R15
BNE RegTest1Error
MVFACGU #0, A0, R15
CMP #10, R15
BNE RegTest1Error
MVFACHI #0, A1, R15
CMP #3, R15
BNE RegTest1Error
MVFACLO #0, A1, R15
CMP #4, R15
BNE RegTest1Error
MVFACGU #0, A1, R15
CMP #20, R15
BNE RegTest1Error
;/* Restore the clobbered registers. */
POPM R14-R15
;/* Now compare each register to ensure it still contains the value that was
;set before this loop was entered. */
CMP #1, R1
BNE RegTest1Error
CMP #2, R2
BNE RegTest1Error
CMP #3, R3
BNE RegTest1Error
CMP #4, R4
BNE RegTest1Error
CMP #5, R5
BNE RegTest1Error
CMP #6, R6
BNE RegTest1Error
CMP #7, R7
BNE RegTest1Error
CMP #8, R8
BNE RegTest1Error
CMP #9, R9
BNE RegTest1Error
CMP #10, R10
BNE RegTest1Error
CMP #11, R11
BNE RegTest1Error
CMP #12, R12
BNE RegTest1Error
CMP #13, R13
BNE RegTest1Error
CMP #14, R14
BNE RegTest1Error
CMP #15, R15
BNE RegTest1Error
;/* All comparisons passed, start a new itteratio of this loop. */
BRA TestLoop1
RegTest1Error:
;/* A compare failed, just loop here so the loop counter stops incrementing
;- causing the check task to indicate the error. */
BRA RegTest1Error
;/*-----------------------------------------------------------*/
;/* This function is explained in the comments at the top of main.c. */
_vRegTest2Implementation:
;/* Put a known value in the guard byte of the accumulators. */
MOV.L #1H, R1
MVTACGU R1, A0
MOV.L #2H, R1
MVTACGU R1, A1
;/* Put a known value in each general purpose register. */
MOV.L #10H, R1
MOV.L #20H, R2
MOV.L #30H, R3
MOV.L #40H, R4
MOV.L #50H, R5
MOV.L #60H, R6
MOV.L #70H, R7
MOV.L #80H, R8
MOV.L #90H, R9
MOV.L #100H, R10
MOV.L #110H, R11
MOV.L #120H, R12
MOV.L #130H, R13
MOV.L #140H, R14
MOV.L #150H, R15
;/* Put a known value in the hi and low of the accumulators. */
MVTACHI R1, A0
MVTACLO R2, A0
MVTACHI R3, A1
MVTACLO R4, A1
;/* Loop, checking each itteration that each register still contains the
;expected value. */
TestLoop2:
;/* Push the registers that are going to get clobbered. */
PUSHM R14-R15
;/* Increment the loop counter to show this task is still getting CPU time. */
MOV.L #_ulRegTest2LoopCounter, R14
MOV.L [ R14 ], R15
ADD #1, R15
MOV.L R15, [ R14 ]
;/* Check accumulators. */
MVFACHI #0, A0, R15
CMP #10H, R15
BNE RegTest1Error
MVFACLO #0, A0, R15
CMP #20H, R15
BNE RegTest1Error
MVFACGU #0, A0, R15
CMP #1H, R15
BNE RegTest1Error
MVFACHI #0, A1, R15
CMP #30H, R15
BNE RegTest1Error
MVFACLO #0, A1, R15
CMP #40H, R15
BNE RegTest1Error
MVFACGU #0, A1, R15
CMP #2H, R15
BNE RegTest1Error
;/* Restore the clobbered registers. */
POPM R14-R15
;/* Now compare each register to ensure it still contains the value that was
;set before this loop was entered. */
CMP #10H, R1
BNE RegTest2Error
CMP #20H, R2
BNE RegTest2Error
CMP #30H, R3
BNE RegTest2Error
CMP #40H, R4
BNE RegTest2Error
CMP #50H, R5
BNE RegTest2Error
CMP #60H, R6
BNE RegTest2Error
CMP #70H, R7
BNE RegTest2Error
CMP #80H, R8
BNE RegTest2Error
CMP #90H, R9
BNE RegTest2Error
CMP #100H, R10
BNE RegTest2Error
CMP #110H, R11
BNE RegTest2Error
CMP #120H, R12
BNE RegTest2Error
CMP #130H, R13
BNE RegTest2Error
CMP #140H, R14
BNE RegTest2Error
CMP #150H, R15
BNE RegTest2Error
;/* All comparisons passed, start a new itteratio of this loop. */
BRA TestLoop2
RegTest2Error:
;/* A compare failed, just loop here so the loop counter stops incrementing
;- causing the check task to indicate the error. */
BRA RegTest2Error
.END

504
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to
* select between the two. See the notes on using
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the
* comprehensive version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" task - The check task period is initially set to three seconds. The
* task checks that all the standard demo tasks, and the register check tasks,
* are not only still executing, but are executing without reporting any errors.
* If the check task discovers that a task has either stalled, or reported an
* error, then it changes its own execution period from the initial three
* seconds, to just 200ms. The check task also toggles an LED each time it is
* called. This provides a visual indication of the system status: If the LED
* toggles every three seconds, then no issues have been discovered. If the LED
* toggles every 200ms, then an issue has been discovered with at least one
* task.
*/
/* Standard includes. */
#include <rskrx71mdef.h>
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "semtest.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "death.h"
#include "partest.h"
#include "comtest2.h"
#include "serial.h"
#include "TimerDemo.h"
#include "QueueOverwrite.h"
#include "IntQueue.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
/* Renesas includes. */
#include "r_cg_macrodriver.h"
#include "r_cg_userdefine.h"
/* Priorities for the demo application tasks. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
/* The priority used by the UART command console task. */
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_PERIOD_MS constant. */
#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_PERIOD_MS constant. */
#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )
#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
/*-----------------------------------------------------------*/
/*
* Entry point for the comprehensive demo (as opposed to the simple blinky
* demo).
*/
void main_full( void );
/*
* The full demo includes some functionality called from the tick hook.
*/
void vFullDemoTickHook( void );
/*
* The check task, as described at the top of this file.
*/
static void prvCheckTask( void *pvParameters );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the registers, as described at the top of this file. The nature of these
* files necessitates that they are written in assembly, but the entry points
* are kept in the C file for the convenience of checking the task parameter.
*/
static void prvRegTest1Task( void *pvParameters );
static void prvRegTest2Task( void *pvParameters );
void vRegTest1Implementation( void );
void vRegTest2Implementation( void );
/*
* A high priority task that does nothing other than execute at a pseudo random
* time to ensure the other test tasks don't just execute in a repeating
* pattern.
*/
static void prvPseudoRandomiser( void *pvParameters );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check task. If the variables keep incrementing,
then the register check tasks have not discovered any errors. If a variable
stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/* String for display in the web server. It is set to an error message if the
check task detects an error. */
const char *pcStatusMessage = "All tasks running without error";
/*-----------------------------------------------------------*/
void main_full( void )
{
/* Start all the other standard demo/test tasks. They have no particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartInterruptQueueTasks();
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
/* Create the register check tasks, as described at the top of this file */
xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that just adds a little random behaviour. */
xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* The set of tasks created by the following function call have to be
created last as they keep account of the number of tasks they expect to see
running. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The onboard LED is toggled on each iteration.
If an error is detected then the delay period is decreased from
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
effect of increasing the rate at which the onboard LED toggles, and in so
doing gives visual feedback of the system status. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 0UL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 1UL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 2UL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 3UL;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 4UL;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 5UL;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 6UL;
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 7UL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 8UL;
}
if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )
{
ulErrorFound |= 1UL << 9UL;
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 10UL;
}
if( xIsQueueOverwriteTaskStillRunning() != pdPASS )
{
ulErrorFound |= 1UL << 11UL;
}
if( xAreEventGroupTasksStillRunning() != pdPASS )
{
ulErrorFound |= 1UL << 12UL;
}
if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 13UL;
}
if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 14UL;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound |= 1UL << 15UL;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound |= 1UL << 16UL;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
everything is ok. A faster toggle indicates an error. */
LED0 = !LED0;
if( ulErrorFound != pdFALSE )
{
/* An error has been detected in one of the tasks - flash the LED
at a higher frequency to give visible feedback that something has
gone wrong (it might just be that the loop back connector required
by the comtest tasks has not been fitted). */
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
pcStatusMessage = "Error found in at least one task.";
}
}
}
/*-----------------------------------------------------------*/
static void prvPseudoRandomiser( void *pvParameters )
{
const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );
volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;
/* This task does nothing other than ensure there is a little bit of
disruption in the scheduling pattern of the other tasks. Normally this is
done by generating interrupts at pseudo random times. */
for( ;; )
{
ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;
ulValue = ( ulNextRand >> 16UL ) & 0xffUL;
if( ulValue < ulMinDelay )
{
ulValue = ulMinDelay;
}
vTaskDelay( ulValue );
while( ulValue > 0 )
{
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
ulValue--;
}
}
}
/*-----------------------------------------------------------*/
void vFullDemoTickHook( void )
{
/* The full demo includes a software timer demo/test that requires
prodding periodically from the tick interrupt. */
vTimerPeriodicISRTests();
/* Call the periodic queue overwrite from ISR demo. */
vQueueOverwritePeriodicISRDemo();
/* Call the periodic event group from ISR demo. */
vPeriodicEventGroupsProcessing();
/* Use task notifications from an interrupt. */
xNotifyTaskFromISR();
/* Use mutexes from interrupts. */
vInterruptSemaphorePeriodicTest();
}
/*-----------------------------------------------------------*/
/* This function is explained in the comments at the top of this file. */
static void prvRegTest1Task( void *pvParameters )
{
if( pvParameters != mainREG_TEST_1_PARAMETER )
{
/* The parameter did not contain the expected value. */
for( ;; )
{
/* Stop the tick interrupt so its obvious something has gone wrong. */
taskDISABLE_INTERRUPTS();
}
}
/* This is an inline asm function that never returns. */
vRegTest1Implementation();
}
/*-----------------------------------------------------------*/
/* This function is explained in the comments at the top of this file. */
static void prvRegTest2Task( void *pvParameters )
{
if( pvParameters != mainREG_TEST_2_PARAMETER )
{
/* The parameter did not contain the expected value. */
for( ;; )
{
/* Stop the tick interrupt so its obvious something has gone wrong. */
taskDISABLE_INTERRUPTS();
}
}
/* This is an inline asm function that never returns. */
vRegTest2Implementation();
}
/*-----------------------------------------------------------*/

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@ -0,0 +1,764 @@
/***************************************************************/
/* */
/* PROJECT NAME : RTOSDemo */
/* FILE : interrupt_handlers.c */
/* DESCRIPTION : Interrupt Handler */
/* CPU SERIES : RX700 */
/* CPU TYPE : RX71M */
/* */
/* This file is generated by e2 studio. */
/* */
/***************************************************************/
/************************************************************************/
/* File Version: V1.00 */
/* Date Generated: 18/12/2014 */
/************************************************************************/
#include "interrupt_handlers.h"
// Exception(Supervisor Instruction)
void INT_Excep_SuperVisorInst(void){/* brk(); */}
// Exception(Access Instruction)
void INT_Excep_AccessInst(void){/* brk(); */}
// Exception(Undefined Instruction)
void INT_Excep_UndefinedInst(void){/* brk(); */}
// Exception(Floating Point)
void INT_Excep_FloatingPoint(void){/* brk(); */}
// NMI
void INT_NonMaskableInterrupt(void){/* brk(); */}
// Dummy
void Dummy(void){/* brk(); */}
// BRK
void INT_Excep_BRK(void){ /*wait();*/ }
//;0x0000 Reserved
//;0x0004 Reserved
//;0x0008 Reserved
//;0x000C Reserved
//;0x0010 Reserved
//;0x0014 Reserved
//;0x0018 Reserved
//;0x001C Reserved
//;0x0020 Reserved
//;0x0024 Reserved
//;0x0028 Reserved
//;0x002C Reserved
//;0x0030 Reserved
//;0x0034 Reserved
//;0x0038 Reserved
//;0x003C Reserved
//;0x0040 BUSERR
void INT_Excep_BSC_BUSERR(void){ }
//;0x0044 Reserved
//;0x0048 RAMERR
void INT_Excep_RAM_RAMERR(void){ }
//;0x004C Reserved
//;0x0050 Reserved
//;0x0054 FIFERR
void INT_Excep_FCU_FIFERR(void){ }
//;0x0058 Reserved
//;0x005C FRDYI
void INT_Excep_FCU_FRDYI(void){ }
//;0x0060 Reserved
//;0x0064 Reserved
//;0x0068 SWINT2
void INT_Excep_ICU_SWINT2(void){ }
//;0x006C SWINT
void INT_Excep_ICU_SWINT(void){ }
//;0x0070 CMI0
void INT_Excep_CMT0_CMI0(void){ }
//;0x0074 CMI1
void INT_Excep_CMT1_CMI1(void){ }
//;0x0078 CMWI0
void INT_Excep_CMTW0_CMWI0(void){ }
//;0x007C CMWI1
void INT_Excep_CMTW1_CMWI1(void){ }
//;0x0080 D0FIFO2
void INT_Excep_USBA_D0FIFO2(void){ }
//;0x0084 D1FIFO2
void INT_Excep_USBA_D1FIFO2(void){ }
//;0x0088 D0FIFO0
void INT_Excep_USB0_D0FIFO0(void){ }
//;0x008C D1FIFO0
void INT_Excep_USB0_D1FIFO0(void){ }
//;0x0090 Reserved
//;0x0094 Reserved
//;0x0098 SPRI0
void INT_Excep_RSPI0_SPRI0(void){ }
//;0x009C SPTI0
void INT_Excep_RSPI0_SPTI0(void){ }
//;0x00A0 SPRI1
void INT_Excep_RSPI1_SPRI1(void){ }
//;0x00A4 SPTI1
void INT_Excep_RSPI1_SPTI1(void){ }
//;0x00A8 SPRI
void INT_Excep_QSPI_SPRI(void){ }
//;0x00AC SPTI
void INT_Excep_QSPI_SPTI(void){ }
//;0x00B0 SBFAI
void INT_Excep_SDHI_SBFAI(void){ }
//;0x00B4 MBFAI
void INT_Excep_MMCIF_MBFAI(void){ }
//;0x00B8 SSITX0
void INT_Excep_SSI0_SSITXI0(void){ }
//;0x00BC SSIRX0
void INT_Excep_SSI0_SSIRXI0(void){ }
//;0x00C0 SSIRTI1
void INT_Excep_SSI1_SSIRTI1(void){ }
//;0x00C4 Reserved
//;0x00C8 IDEI
void INT_Excep_SRC_IDEI(void){ }
//;0x00CC ODFI
void INT_Excep_SRC_ODFI(void){ }
//;0x00D0 RXI0
void INT_Excep_RIIC0_RXI0(void){ }
//;0x00D4C TXI0
void INT_Excep_RIIC0_TXI0(void){ }
//;0x00D8 RXI2
void INT_Excep_RIIC2_RXI2(void){ }
//;0x00DC TXI2
void INT_Excep_RIIC2_TXI2(void){ }
//;0x00E0 Reserved
//;0x00E4 Reserved
//;0x00E8 RXI0
void INT_Excep_SCI0_RXI0(void){ }
//;0x00EC TXI0
void INT_Excep_SCI0_TXI0(void){ }
//;0x00F0 RXI1
void INT_Excep_SCI1_RXI1(void){ }
//;0x00F4 TXI1
void INT_Excep_SCI1_TXI1(void){ }
//;0x00F8 RXI2
void INT_Excep_SCI2_RXI2(void){ }
//;0x00FC TXI2
void INT_Excep_SCI2_TXI2(void){ }
//;0x0100 IRQ0
void INT_Excep_ICU_IRQ0(void){ }
//;0x0104 IRQ1
void INT_Excep_ICU_IRQ1(void){ }
//;0x0108 IRQ2
void INT_Excep_ICU_IRQ2(void){ }
//;0x010C IRQ3
void INT_Excep_ICU_IRQ3(void){ }
//;0x0110 IRQ4
void INT_Excep_ICU_IRQ4(void){ }
//;0x0114 IRQ5
void INT_Excep_ICU_IRQ5(void){ }
//;0x0118 IRQ6
void INT_Excep_ICU_IRQ6(void){ }
//;0x011C IRQ7
void INT_Excep_ICU_IRQ7(void){ }
//;0x0120 IRQ8
void INT_Excep_ICU_IRQ8(void){ }
//;0x0124 IRQ9
void INT_Excep_ICU_IRQ9(void){ }
//;0x0128 IRQ10
void INT_Excep_ICU_IRQ10(void){ }
//;0x012C IRQ11
void INT_Excep_ICU_IRQ11(void){ }
//;0x0130 IRQ12
void INT_Excep_ICU_IRQ12(void){ }
//;0x0134 IRQ13
void INT_Excep_ICU_IRQ13(void){ }
//;0x0138 IRQ14
void INT_Excep_ICU_IRQ14(void){ }
//;0x013C IRQ15
void INT_Excep_ICU_IRQ15(void){ }
//;0x0140 RXI3
void INT_Excep_SCI3_RXI3(void){ }
//;0x0144 TXI3
void INT_Excep_SCI3_TXI3(void){ }
//;0x0148 RXI4
void INT_Excep_SCI4_RXI4(void){ }
//;0x014C TXI4
void INT_Excep_SCI4_TXI4(void){ }
//;0x0150 RXI5
void INT_Excep_SCI5_RXI5(void){ }
//;0x0154 TXI5
void INT_Excep_SCI5_TXI5(void){ }
//;0x0158 RXI6
void INT_Excep_SCI6_RXI6(void){ }
//;0x015C TXI6
void INT_Excep_SCI6_TXI6(void){ }
//;0x0160 COMPA1
void INT_Excep_LVD1_LVD1(void){ }
//;0x0164 COMPA2
void INT_Excep_LVD2_LVD2(void){ }
//;0x0168 USBR0
void INT_Excep_USB0_USBR0(void){ }
//;0x016C Reserved
//;0x0170 ALM
void INT_Excep_RTC_ALM(void){ }
//;0x0174 PRD
void INT_Excep_RTC_PRD(void){ }
//;0x0178 HSUSBR
void INT_Excep_USBA_USBAR(void){ }
//;0x017C IWUNI
void INT_Excep_IWDT_IWUNI(void){ }
//;0x0180 WUNI
void INT_Excep_WDT_WUNI(void){ }
//;0x0184 PCDFI
void INT_Excep_PDC_PCDFI(void){ }
//;0x0188 RXI7
void INT_Excep_SCI7_RXI7(void){ }
//;0x018C TXI7
void INT_Excep_SCI7_TXI7(void){ }
//;0x0190 RXIF8
void INT_Excep_SCIFA8_RXIF8(void){ }
//;0x0194 TXIF8
void INT_Excep_SCIFA8_TXIF8(void){ }
//;0x0198 RXIF9
void INT_Excep_SCIFA9_RXIF9(void){ }
//;0x019C TXIF9
void INT_Excep_SCIFA9_TXIF9(void){ }
//;0x01A0 RXIF10
void INT_Excep_SCIFA10_RXIF10(void){ }
//;0x01A4 TXIF10
void INT_Excep_SCIFA10_TXIF10(void){ }
//;0x01A8 GROUPBE0
void INT_Excep_ICU_GROUPBE0(void){ }
//;0x01AC Reserved
//;0x01B0 Reserved
//;0x01B4 Reserved
//;0x01B8 GROUPBL0
void INT_Excep_ICU_GROUPBL0(void){ }
//;0x01BC GROUPBL1
void INT_Excep_ICU_GROUPBL1(void){ }
//;0x01C0 GROUPAL0
void INT_Excep_ICU_GROUPAL0(void){ }
//;0x01C4 GROUPAL1
void INT_Excep_ICU_GROUPAL1(void){ }
//;0x01C8 RXIF11
void INT_Excep_SCIFA11_RXIF11(void){ }
//;0x01CC TXIF11
void INT_Excep_SCIFA11_TXIF11(void){ }
//;0x01D0 RXIF12
void INT_Excep_SCI12_RXI12(void){ }
//;0x01D4 TXIF12
void INT_Excep_SCI12_TXI12(void){ }
//;0x01D8 Reserved
//;0x01DC Reserved
//;0x01E0 DMAC0I
void INT_Excep_DMAC_DMAC0I(void){ }
//;0x01E4 DMAC1I
void INT_Excep_DMAC_DMAC1I(void){ }
//;0x01E8 DMAC2I
void INT_Excep_DMAC_DMAC2I(void){ }
//;0x01EC DMAC3I
void INT_Excep_DMAC_DMAC3I(void){ }
//;0x01F0 DMAC74I
void INT_Excep_DMAC_DMAC74I(void){ }
//;0x01F4 OST
void INT_Excep_OST_OST(void){ }
//;0x01F8 EXDMAC0I
void INT_Excep_EXDMAC_EXDMAC0I(void){ }
//;0x01FC EXDMAC1I
void INT_Excep_EXDMAC_EXDMAC1I(void){ }
//;0x0200 INTB128
void INT_Excep_PERIB_INTB128(void){ }
//;0x0204 INTB129
void INT_Excep_PERIB_INTB129(void){ }
//;0x0208 INTB130
void INT_Excep_PERIB_INTB130(void){ }
//;0x020C INTB131
void INT_Excep_PERIB_INTB131(void){ }
//;0x0210 INTB132
void INT_Excep_PERIB_INTB132(void){ }
//;0x0214 INTB133
void INT_Excep_PERIB_INTB133(void){ }
//;0x0218 INTB134
void INT_Excep_PERIB_INTB134(void){ }
//;0x021C INTB135
void INT_Excep_PERIB_INTB135(void){ }
//;0x0220 INTB136
void INT_Excep_PERIB_INTB136(void){ }
//;0x0224 INTB137
void INT_Excep_PERIB_INTB137(void){ }
//;0x0228 INTB138
void INT_Excep_PERIB_INTB138(void){ }
//;0x022C INTB139
void INT_Excep_PERIB_INTB139(void){ }
//;0x0230 INTB140
void INT_Excep_PERIB_INTB140(void){ }
//;0x0234 INTB141
void INT_Excep_PERIB_INTB141(void){ }
//;0x0238 INTB142
void INT_Excep_PERIB_INTB142(void){ }
//;0x023C INTB143
void INT_Excep_PERIB_INTB143(void){ }
//;0x0240 INTB144
void INT_Excep_PERIB_INTB144(void){ }
//;0x0244 INTB145
void INT_Excep_PERIB_INTB145(void){ }
//;0x0248 INTB146
void INT_Excep_PERIB_INTB146(void){ }
//;0x024C INTB147
void INT_Excep_PERIB_INTB147(void){ }
//;0x0250 INTB148
void INT_Excep_PERIB_INTB148(void){ }
//;0x02540 INTB149
void INT_Excep_PERIB_INTB149(void){ }
//;0x0258 INTB150
void INT_Excep_PERIB_INTB150(void){ }
//;0x025C INTB151
void INT_Excep_PERIB_INTB151(void){ }
//;0x0260 INTB152
void INT_Excep_PERIB_INTB152(void){ }
//;0x0264 INTB153
void INT_Excep_PERIB_INTB153(void){ }
//;0x0268 INTB154
void INT_Excep_PERIB_INTB154(void){ }
//;0x026C INTB155
void INT_Excep_PERIB_INTB155(void){ }
//;0x0270 INTB156
void INT_Excep_PERIB_INTB156(void){ }
//;0x0274 INTB157
void INT_Excep_PERIB_INTB157(void){ }
//;0x0278 INTB158
void INT_Excep_PERIB_INTB158(void){ }
//;0x027C INTB159
void INT_Excep_PERIB_INTB159(void){ }
//;0x0280 INTB160
void INT_Excep_PERIB_INTB160(void){ }
//;0x0284 INTB161
void INT_Excep_PERIB_INTB161(void){ }
//;0x0288 INTB162
void INT_Excep_PERIB_INTB162(void){ }
//;0x028C INTB163
void INT_Excep_PERIB_INTB163(void){ }
//;0x0290 INTB164
void INT_Excep_PERIB_INTB164(void){ }
//;0x0294 PERIB INTB165
void INT_Excep_PERIB_INTB165(void){ }
//;0x0298 PERIB INTB166
void INT_Excep_PERIB_INTB166(void){ }
//;0x029C PERIB INTB167
void INT_Excep_PERIB_INTB167(void){ }
//;0x02A0 PERIB INTB168
void INT_Excep_PERIB_INTB168(void){ }
//;0x02A4 PERIB INTB169
void INT_Excep_PERIB_INTB169(void){ }
//;0x02A8 PERIB INTB170
void INT_Excep_PERIB_INTB170(void){ }
//;0x02AC PERIB INTB171
void INT_Excep_PERIB_INTB171(void){ }
//;0x02B0 PERIB INTB172
void INT_Excep_PERIB_INTB172(void){ }
//;0x02B4 PERIB INTB173
void INT_Excep_PERIB_INTB173(void){ }
//;0x02B8 PERIB INTB174
void INT_Excep_PERIB_INTB174(void){ }
//;0x02BC PERIB INTB175
void INT_Excep_PERIB_INTB175(void){ }
//;0x02C0 PERIB INTB176
void INT_Excep_PERIB_INTB176(void){ }
//;0x02C4 PERIB INTB177
void INT_Excep_PERIB_INTB177(void){ }
//;0x02C8 PERIB INTB178
void INT_Excep_PERIB_INTB178(void){ }
//;0x02CC PERIB INTB179
void INT_Excep_PERIB_INTB179(void){ }
//;0x02D0 PERIB INTB180
void INT_Excep_PERIB_INTB180(void){ }
//;0x02D4 PERIB INTB181
void INT_Excep_PERIB_INTB181(void){ }
//;0x02D8 PERIB INTB182
void INT_Excep_PERIB_INTB182(void){ }
//;0x02DC PERIB INTB183
void INT_Excep_PERIB_INTB183(void){ }
//;0x02E0 PERIB INTB184
void INT_Excep_PERIB_INTB184(void){ }
//;0x02E4 PERIB INTB185
void INT_Excep_PERIB_INTB185(void){ }
//;0x02E8 PERIB INTB186
void INT_Excep_PERIB_INTB186(void){ }
//;0x02EC PERIB INTB187
void INT_Excep_PERIB_INTB187(void){ }
//;0x02F0 PERIB INTB188
void INT_Excep_PERIB_INTB188(void){ }
//;0x02F4 PERIB INTB189
void INT_Excep_PERIB_INTB189(void){ }
//;0x02F8 PERIB INTB190
void INT_Excep_PERIB_INTB190(void){ }
//;0x02FC PERIB INTB191
void INT_Excep_PERIB_INTB191(void){ }
//;0x0300 PERIB INTB192
void INT_Excep_PERIB_INTB192(void){ }
//;0x0304 PERIB INTB193
void INT_Excep_PERIB_INTB193(void){ }
//;0x0308 PERIB INTB194
void INT_Excep_PERIB_INTB194(void){ }
//;0x030C PERIB INTB195
void INT_Excep_PERIB_INTB195(void){ }
//;0x0310 PERIB INTB196
void INT_Excep_PERIB_INTB196(void){ }
//;0x0314 PERIB INTB197
void INT_Excep_PERIB_INTB197(void){ }
//;0x0318 PERIB INTB198
void INT_Excep_PERIB_INTB198(void){ }
//;0x031C PERIB INTB199
void INT_Excep_PERIB_INTB199(void){ }
//;0x0320 PERIB INTB200
void INT_Excep_PERIB_INTB200(void){ }
//;0x0324 PERIB INTB201
void INT_Excep_PERIB_INTB201(void){ }
//;0x0328 PERIB INTB202
void INT_Excep_PERIB_INTB202(void){ }
//;0x032C PERIB INTB203
void INT_Excep_PERIB_INTB203(void){ }
//;0x0320 PERIB INTB204
void INT_Excep_PERIB_INTB204(void){ }
//;0x0334 PERIB INTB205
void INT_Excep_PERIB_INTB205(void){ }
//;0x0338 PERIB INTB206
void INT_Excep_PERIB_INTB206(void){ }
//;0x033C PERIB INTB207
void INT_Excep_PERIB_INTB207(void){ }
//;0x0340 PERIA INTA208
void INT_Excep_PERIA_INTA208(void){ }
//;0x0344 PERIA INTA209
void INT_Excep_PERIA_INTA209(void){ }
//;0x0348 PERIA INTA210
void INT_Excep_PERIA_INTA210(void){ }
//;0x034C PERIA INTA211
void INT_Excep_PERIA_INTA211(void){ }
//;0x0350 PERIA INTA212
void INT_Excep_PERIA_INTA212(void){ }
//;0x0354 PERIA INTA213
void INT_Excep_PERIA_INTA213(void){ }
//;0x0358 PERIA INTA214
void INT_Excep_PERIA_INTA214(void){ }
//;0x035C PERIA INTA215
void INT_Excep_PERIA_INTA215(void){ }
//;0x0360 PERIA INTA216
void INT_Excep_PERIA_INTA216(void){ }
//;0x0364 PERIA INTA217
void INT_Excep_PERIA_INTA217(void){ }
//;0x0368 PERIA INTA218
void INT_Excep_PERIA_INTA218(void){ }
//;0x036C PERIA INTA219
void INT_Excep_PERIA_INTA219(void){ }
//;0x0370 PERIA INTA220
void INT_Excep_PERIA_INTA220(void){ }
//;0x0374 PERIA INTA221
void INT_Excep_PERIA_INTA221(void){ }
//;0x0378 PERIA INTA222
void INT_Excep_PERIA_INTA222(void){ }
//;0x037C PERIA INTA223
void INT_Excep_PERIA_INTA223(void){ }
//;0x0380 PERIA INTA224
void INT_Excep_PERIA_INTA224(void){ }
//;0x0384 PERIA INTA225
void INT_Excep_PERIA_INTA225(void){ }
//;0x0388 PERIA INTA226
void INT_Excep_PERIA_INTA226(void){ }
//;0x038C PERIA INTA227
void INT_Excep_PERIA_INTA227(void){ }
//;0x0390 PERIA INTA228
void INT_Excep_PERIA_INTA228(void){ }
//;0x0394 PERIA INTA229
void INT_Excep_PERIA_INTA229(void){ }
//;0x0398 PERIA INTA230
void INT_Excep_PERIA_INTA230(void){ }
//;0x039C PERIA INTA231
void INT_Excep_PERIA_INTA231(void){ }
//;0x03A0 PERIA INTA232
void INT_Excep_PERIA_INTA232(void){ }
//;0x03A4 PERIA INTA233
void INT_Excep_PERIA_INTA233(void){ }
//;0x03A8 PERIA INTA234
void INT_Excep_PERIA_INTA234(void){ }
//;0x03AC PERIA INTA235
void INT_Excep_PERIA_INTA235(void){ }
//;0x03B0 PERIA INTA236
void INT_Excep_PERIA_INTA236(void){ }
//;0x04B4 PERIA INTA237
void INT_Excep_PERIA_INTA237(void){ }
//;0x03B8 PERIA INTA238
void INT_Excep_PERIA_INTA238(void){ }
//;0x03BC PERIA INTA239
void INT_Excep_PERIA_INTA239(void){ }
//;0x03C0 PERIA INTA240
void INT_Excep_PERIA_INTA240(void){ }
//;0x03C4 PERIA INTA241
void INT_Excep_PERIA_INTA241(void){ }
//;0x03C8 PERIA INTA242
void INT_Excep_PERIA_INTA242(void){ }
//;0x03CC PERIA INTA243
void INT_Excep_PERIA_INTA243(void){ }
//;0x03D0 PERIA INTA244
void INT_Excep_PERIA_INTA244(void){ }
//;0x03D4 PERIA INTA245
void INT_Excep_PERIA_INTA245(void){ }
//;0x03D8 PERIA INTA246
void INT_Excep_PERIA_INTA246(void){ }
//;0x03DC PERIA INTA247
void INT_Excep_PERIA_INTA247(void){ }
//;0x03E0 PERIA INTA248
void INT_Excep_PERIA_INTA248(void){ }
//;0x03E4 PERIA INTA249
void INT_Excep_PERIA_INTA249(void){ }
//;0x03E8 PERIA INTA250
void INT_Excep_PERIA_INTA250(void){ }
//;0x03EC PERIA INTA251
void INT_Excep_PERIA_INTA251(void){ }
//;0x03F0 PERIA INTA252
void INT_Excep_PERIA_INTA252(void){ }
//;0x03F4 PERIA INTA253
void INT_Excep_PERIA_INTA253(void){ }
//;0x03F8 PERIA INTA254
void INT_Excep_PERIA_INTA254(void){ }
//;0x03FC PERIA INTA255
void INT_Excep_PERIA_INTA255(void){ }

776
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/interrupt_handlers.h Normal file
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@ -0,0 +1,776 @@
/***************************************************************/
/* */
/* PROJECT NAME : RTOSDemo */
/* FILE : interrupt_handlers.h */
/* DESCRIPTION : Interrupt Handler Declarations */
/* CPU SERIES : RX700 */
/* CPU TYPE : RX71M */
/* */
/* This file is generated by e2 studio. */
/* */
/***************************************************************/
/************************************************************************/
/* File Version: V1.00 */
/* Date Modified: 18/12/2014 */
/************************************************************************/
#ifndef INTERRUPT_HANDLERS_H
#define INTERRUPT_HANDLERS_H
// Exception(Supervisor Instruction)
void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt));
// Exception(Access Instruction)
void INT_Excep_AccessInst(void) __attribute__ ((interrupt));
// Exception(Undefined Instruction)
void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt));
// Exception(Floating Point)
void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt));
// NMI
void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt));
// Dummy
void Dummy(void) __attribute__ ((interrupt));
// BRK
void INT_Excep_BRK(void) __attribute__ ((interrupt));
//;0x0000 Reserved
//;0x0004 Reserved
//;0x0008 Reserved
//;0x000C Reserved
//;0x0010 Reserved
//;0x0014 Reserved
//;0x0018 Reserved
//;0x001C Reserved
//;0x0020 Reserved
//;0x0024 Reserved
//;0x0028 Reserved
//;0x002C Reserved
//;0x0030 Reserved
//;0x0034 Reserved
//;0x0038 Reserved
//;0x003C Reserved
//;0x0040 BUSERR
void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt));
//;0x0044 Reserved
//;0x0048 RAMERR
void INT_Excep_RAM_RAMERR(void) __attribute__ ((interrupt));
//;0x004C Reserved
//;0x0050 Reserved
//;0x0054 FIFERR
void INT_Excep_FCU_FIFERR(void) __attribute__ ((interrupt));
//;0x0058 Reserved
//;0x005C FRDYI
void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt));
//;0x0060 Reserved
//;0x0064 Reserved
//;0x0068 SWINT2
void INT_Excep_ICU_SWINT2(void) __attribute__ ((interrupt));
//;0x006C SWINT
void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt));
//;0x0070 CMI0
void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt));
//;0x0074 CMI1
void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt));
//;0x0078 CMWI0
void INT_Excep_CMTW0_CMWI0(void) __attribute__ ((interrupt));
//;0x007C CMWI1
void INT_Excep_CMTW1_CMWI1(void) __attribute__ ((interrupt));
//;0x0080 D0FIFO2
void INT_Excep_USBA_D0FIFO2(void) __attribute__ ((interrupt));
//;0x0084 D1FIFO2
void INT_Excep_USBA_D1FIFO2(void) __attribute__ ((interrupt));
//;0x0088 D0FIFO0
void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt));
//;0x008C D1FIFO0
void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt));
//;0x0090 Reserved
//;0x0094 Reserved
//;0x0098 SPRI0
void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt));
//;0x009C SPTI0
void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt));
//;0x00A0 SPRI1
void INT_Excep_RSPI1_SPRI1(void) __attribute__ ((interrupt));
//;0x00A4 SPTI1
void INT_Excep_RSPI1_SPTI1(void) __attribute__ ((interrupt));
//;0x00A8 SPRI
void INT_Excep_QSPI_SPRI(void) __attribute__ ((interrupt));
//;0x00AC SPTI
void INT_Excep_QSPI_SPTI(void) __attribute__ ((interrupt));
//;0x00B0 SBFAI
void INT_Excep_SDHI_SBFAI(void) __attribute__ ((interrupt));
//;0x00B4 MBFAI
void INT_Excep_MMCIF_MBFAI(void) __attribute__ ((interrupt));
//;0x00B8 SSITX0
void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt));
//;0x00BC SSIRX0
void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt));
//;0x00C0 SSIRTI1
void INT_Excep_SSI1_SSIRTI1(void) __attribute__ ((interrupt));
//;0x00C4 Reserved
//;0x00C8 IDEI
void INT_Excep_SRC_IDEI(void) __attribute__ ((interrupt));
//;0x00CC ODFI
void INT_Excep_SRC_ODFI(void) __attribute__ ((interrupt));
//;0x00D0 RXI0
void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt));
//;0x00D4C TXI0
void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt));
//;0x00D8 RXI2
void INT_Excep_RIIC2_RXI2(void) __attribute__ ((interrupt));
//;0x00DC TXI2
void INT_Excep_RIIC2_TXI2(void) __attribute__ ((interrupt));
//;0x00E0 Reserved
//;0x00E4 Reserved
//;0x00E8 RXI0
void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt));
//;0x00EC TXI0
void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt));
//;0x00F0 RXI1
void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt));
//;0x00F4 TXI1
void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt));
//;0x00F8 RXI2
void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt));
//;0x00FC TXI2
void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt));
//;0x0100 IRQ0
void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt));
//;0x0104 IRQ1
void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt));
//;0x0108 IRQ2
void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt));
//;0x010C IRQ3
void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt));
//;0x0110 IRQ4
void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt));
//;0x0114 IRQ5
void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt));
//;0x0118 IRQ6
void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt));
//;0x011C IRQ7
void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt));
//;0x0120 IRQ8
void INT_Excep_ICU_IRQ8(void) __attribute__ ((interrupt));
//;0x0124 IRQ9
void INT_Excep_ICU_IRQ9(void) __attribute__ ((interrupt));
//;0x0128 IRQ10
void INT_Excep_ICU_IRQ10(void) __attribute__ ((interrupt));
//;0x012C IRQ11
void INT_Excep_ICU_IRQ11(void) __attribute__ ((interrupt));
//;0x0130 IRQ12
void INT_Excep_ICU_IRQ12(void) __attribute__ ((interrupt));
//;0x0134 IRQ13
void INT_Excep_ICU_IRQ13(void) __attribute__ ((interrupt));
//;0x0138 IRQ14
void INT_Excep_ICU_IRQ14(void) __attribute__ ((interrupt));
//;0x013C IRQ15
void INT_Excep_ICU_IRQ15(void) __attribute__ ((interrupt));
//;0x0140 RXI3
void INT_Excep_SCI3_RXI3(void) __attribute__ ((interrupt));
//;0x0144 TXI3
void INT_Excep_SCI3_TXI3(void) __attribute__ ((interrupt));
//;0x0148 RXI4
void INT_Excep_SCI4_RXI4(void) __attribute__ ((interrupt));
//;0x014C TXI4
void INT_Excep_SCI4_TXI4(void) __attribute__ ((interrupt));
//;0x0150 RXI5
void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt));
//;0x0154 TXI5
void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt));
//;0x0158 RXI6
void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt));
//;0x015C TXI6
void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt));
//;0x0160 COMPA1
void INT_Excep_LVD1_LVD1(void) __attribute__ ((interrupt));
//;0x0164 COMPA2
void INT_Excep_LVD2_LVD2(void) __attribute__ ((interrupt));
//;0x0168 USBR0
void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt));
//;0x016C Reserved
//;0x0170 ALM
void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt));
//;0x0174 PRD
void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt));
//;0x0178 HSUSBR
void INT_Excep_USBA_USBAR(void) __attribute__ ((interrupt));
//;0x017C IWUNI
void INT_Excep_IWDT_IWUNI(void) __attribute__ ((interrupt));
//;0x0180 WUNI
void INT_Excep_WDT_WUNI(void) __attribute__ ((interrupt));
//;0x0184 PCDFI
void INT_Excep_PDC_PCDFI(void) __attribute__ ((interrupt));
//;0x0188 RXI7
void INT_Excep_SCI7_RXI7(void) __attribute__ ((interrupt));
//;0x018C TXI7
void INT_Excep_SCI7_TXI7(void) __attribute__ ((interrupt));
//;0x0190 RXIF8
void INT_Excep_SCIFA8_RXIF8(void) __attribute__ ((interrupt));
//;0x0194 TXIF8
void INT_Excep_SCIFA8_TXIF8(void) __attribute__ ((interrupt));
//;0x0198 RXIF9
void INT_Excep_SCIFA9_RXIF9(void) __attribute__ ((interrupt));
//;0x019C TXIF9
void INT_Excep_SCIFA9_TXIF9(void) __attribute__ ((interrupt));
//;0x01A0 RXIF10
void INT_Excep_SCIFA10_RXIF10(void) __attribute__ ((interrupt));
//;0x01A4 TXIF10
void INT_Excep_SCIFA10_TXIF10(void) __attribute__ ((interrupt));
//;0x01A8 GROUPBE0
void INT_Excep_ICU_GROUPBE0(void) __attribute__ ((interrupt));
//;0x01AC Reserved
//;0x01B0 Reserved
//;0x01B4 Reserved
//;0x01B8 GROUPBL0
void INT_Excep_ICU_GROUPBL0(void) __attribute__ ((interrupt));
//;0x01BC GROUPBL1
void INT_Excep_ICU_GROUPBL1(void) __attribute__ ((interrupt));
//;0x01C0 GROUPAL0
void INT_Excep_ICU_GROUPAL0(void) __attribute__ ((interrupt));
//;0x01C4 GROUPAL1
void INT_Excep_ICU_GROUPAL1(void) __attribute__ ((interrupt));
//;0x01C8 RXIF11
void INT_Excep_SCIFA11_RXIF11(void) __attribute__ ((interrupt));
//;0x01CC TXIF11
void INT_Excep_SCIFA11_TXIF11(void) __attribute__ ((interrupt));
//;0x01D0 RXIF12
void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt));
//;0x01D4 TXIF12
void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt));
//;0x01D8 Reserved
//;0x01DC Reserved
//;0x01E0 DMAC0I
void INT_Excep_DMAC_DMAC0I(void) __attribute__ ((interrupt));
//;0x01E4 DMAC1I
void INT_Excep_DMAC_DMAC1I(void) __attribute__ ((interrupt));
//;0x01E8 DMAC2I
void INT_Excep_DMAC_DMAC2I(void) __attribute__ ((interrupt));
//;0x01EC DMAC3I
void INT_Excep_DMAC_DMAC3I(void) __attribute__ ((interrupt));
//;0x01F0 DMAC74I
void INT_Excep_DMAC_DMAC74I(void) __attribute__ ((interrupt));
//;0x01F4 OST
void INT_Excep_OST_OST(void) __attribute__ ((interrupt));
//;0x01F8 EXDMAC0I
void INT_Excep_EXDMAC_EXDMAC0I(void) __attribute__ ((interrupt));
//;0x01FC EXDMAC1I
void INT_Excep_EXDMAC_EXDMAC1I(void) __attribute__ ((interrupt));
//;0x0200 INTB128
void INT_Excep_PERIB_INTB128(void) __attribute__ ((interrupt));
//;0x0204 INTB129
void INT_Excep_PERIB_INTB129(void) __attribute__ ((interrupt));
//;0x0208 INTB130
void INT_Excep_PERIB_INTB130(void) __attribute__ ((interrupt));
//;0x020C INTB131
void INT_Excep_PERIB_INTB131(void) __attribute__ ((interrupt));
//;0x0210 INTB132
void INT_Excep_PERIB_INTB132(void) __attribute__ ((interrupt));
//;0x0214 INTB133
void INT_Excep_PERIB_INTB133(void) __attribute__ ((interrupt));
//;0x0218 INTB134
void INT_Excep_PERIB_INTB134(void) __attribute__ ((interrupt));
//;0x021C INTB135
void INT_Excep_PERIB_INTB135(void) __attribute__ ((interrupt));
//;0x0220 INTB136
void INT_Excep_PERIB_INTB136(void) __attribute__ ((interrupt));
//;0x0224 INTB137
void INT_Excep_PERIB_INTB137(void) __attribute__ ((interrupt));
//;0x0228 INTB138
void INT_Excep_PERIB_INTB138(void) __attribute__ ((interrupt));
//;0x022C INTB139
void INT_Excep_PERIB_INTB139(void) __attribute__ ((interrupt));
//;0x0230 INTB140
void INT_Excep_PERIB_INTB140(void) __attribute__ ((interrupt));
//;0x0234 INTB141
void INT_Excep_PERIB_INTB141(void) __attribute__ ((interrupt));
//;0x0238 INTB142
void INT_Excep_PERIB_INTB142(void) __attribute__ ((interrupt));
//;0x023C INTB143
void INT_Excep_PERIB_INTB143(void) __attribute__ ((interrupt));
//;0x0240 INTB144
void INT_Excep_PERIB_INTB144(void) __attribute__ ((interrupt));
//;0x0244 INTB145
void INT_Excep_PERIB_INTB145(void) __attribute__ ((interrupt));
//;0x0248 INTB146
void INT_Excep_PERIB_INTB146(void) __attribute__ ((interrupt));
//;0x024C INTB147
void INT_Excep_PERIB_INTB147(void) __attribute__ ((interrupt));
//;0x0250 INTB148
void INT_Excep_PERIB_INTB148(void) __attribute__ ((interrupt));
//;0x02540 INTB149
void INT_Excep_PERIB_INTB149(void) __attribute__ ((interrupt));
//;0x0258 INTB150
void INT_Excep_PERIB_INTB150(void) __attribute__ ((interrupt));
//;0x025C INTB151
void INT_Excep_PERIB_INTB151(void) __attribute__ ((interrupt));
//;0x0260 INTB152
void INT_Excep_PERIB_INTB152(void) __attribute__ ((interrupt));
//;0x0264 INTB153
void INT_Excep_PERIB_INTB153(void) __attribute__ ((interrupt));
//;0x0268 INTB154
void INT_Excep_PERIB_INTB154(void) __attribute__ ((interrupt));
//;0x026C INTB155
void INT_Excep_PERIB_INTB155(void) __attribute__ ((interrupt));
//;0x0270 INTB156
void INT_Excep_PERIB_INTB156(void) __attribute__ ((interrupt));
//;0x0274 INTB157
void INT_Excep_PERIB_INTB157(void) __attribute__ ((interrupt));
//;0x0278 INTB158
void INT_Excep_PERIB_INTB158(void) __attribute__ ((interrupt));
//;0x027C INTB159
void INT_Excep_PERIB_INTB159(void) __attribute__ ((interrupt));
//;0x0280 INTB160
void INT_Excep_PERIB_INTB160(void) __attribute__ ((interrupt));
//;0x0284 INTB161
void INT_Excep_PERIB_INTB161(void) __attribute__ ((interrupt));
//;0x0288 INTB162
void INT_Excep_PERIB_INTB162(void) __attribute__ ((interrupt));
//;0x028C INTB163
void INT_Excep_PERIB_INTB163(void) __attribute__ ((interrupt));
//;0x0290 INTB164
void INT_Excep_PERIB_INTB164(void) __attribute__ ((interrupt));
//;0x0294 PERIB INTB165
void INT_Excep_PERIB_INTB165(void) __attribute__ ((interrupt));
//;0x0298 PERIB INTB166
void INT_Excep_PERIB_INTB166(void) __attribute__ ((interrupt));
//;0x029C PERIB INTB167
void INT_Excep_PERIB_INTB167(void) __attribute__ ((interrupt));
//;0x02A0 PERIB INTB168
void INT_Excep_PERIB_INTB168(void) __attribute__ ((interrupt));
//;0x02A4 PERIB INTB169
void INT_Excep_PERIB_INTB169(void) __attribute__ ((interrupt));
//;0x02A8 PERIB INTB170
void INT_Excep_PERIB_INTB170(void) __attribute__ ((interrupt));
//;0x02AC PERIB INTB171
void INT_Excep_PERIB_INTB171(void) __attribute__ ((interrupt));
//;0x02B0 PERIB INTB172
void INT_Excep_PERIB_INTB172(void) __attribute__ ((interrupt));
//;0x02B4 PERIB INTB173
void INT_Excep_PERIB_INTB173(void) __attribute__ ((interrupt));
//;0x02B8 PERIB INTB174
void INT_Excep_PERIB_INTB174(void) __attribute__ ((interrupt));
//;0x02BC PERIB INTB175
void INT_Excep_PERIB_INTB175(void) __attribute__ ((interrupt));
//;0x02C0 PERIB INTB176
void INT_Excep_PERIB_INTB176(void) __attribute__ ((interrupt));
//;0x02C4 PERIB INTB177
void INT_Excep_PERIB_INTB177(void) __attribute__ ((interrupt));
//;0x02C8 PERIB INTB178
void INT_Excep_PERIB_INTB178(void) __attribute__ ((interrupt));
//;0x02CC PERIB INTB179
void INT_Excep_PERIB_INTB179(void) __attribute__ ((interrupt));
//;0x02D0 PERIB INTB180
void INT_Excep_PERIB_INTB180(void) __attribute__ ((interrupt));
//;0x02D4 PERIB INTB181
void INT_Excep_PERIB_INTB181(void) __attribute__ ((interrupt));
//;0x02D8 PERIB INTB182
void INT_Excep_PERIB_INTB182(void) __attribute__ ((interrupt));
//;0x02DC PERIB INTB183
void INT_Excep_PERIB_INTB183(void) __attribute__ ((interrupt));
//;0x02E0 PERIB INTB184
void INT_Excep_PERIB_INTB184(void) __attribute__ ((interrupt));
//;0x02E4 PERIB INTB185
void INT_Excep_PERIB_INTB185(void) __attribute__ ((interrupt));
//;0x02E8 PERIB INTB186
void INT_Excep_PERIB_INTB186(void) __attribute__ ((interrupt));
//;0x02EC PERIB INTB187
void INT_Excep_PERIB_INTB187(void) __attribute__ ((interrupt));
//;0x02F0 PERIB INTB188
void INT_Excep_PERIB_INTB188(void) __attribute__ ((interrupt));
//;0x02F4 PERIB INTB189
void INT_Excep_PERIB_INTB189(void) __attribute__ ((interrupt));
//;0x02F8 PERIB INTB190
void INT_Excep_PERIB_INTB190(void) __attribute__ ((interrupt));
//;0x02FC PERIB INTB191
void INT_Excep_PERIB_INTB191(void) __attribute__ ((interrupt));
//;0x0300 PERIB INTB192
void INT_Excep_PERIB_INTB192(void) __attribute__ ((interrupt));
//;0x0304 PERIB INTB193
void INT_Excep_PERIB_INTB193(void) __attribute__ ((interrupt));
//;0x0308 PERIB INTB194
void INT_Excep_PERIB_INTB194(void) __attribute__ ((interrupt));
//;0x030C PERIB INTB195
void INT_Excep_PERIB_INTB195(void) __attribute__ ((interrupt));
//;0x0310 PERIB INTB196
void INT_Excep_PERIB_INTB196(void) __attribute__ ((interrupt));
//;0x0314 PERIB INTB197
void INT_Excep_PERIB_INTB197(void) __attribute__ ((interrupt));
//;0x0318 PERIB INTB198
void INT_Excep_PERIB_INTB198(void) __attribute__ ((interrupt));
//;0x031C PERIB INTB199
void INT_Excep_PERIB_INTB199(void) __attribute__ ((interrupt));
//;0x0320 PERIB INTB200
void INT_Excep_PERIB_INTB200(void) __attribute__ ((interrupt));
//;0x0324 PERIB INTB201
void INT_Excep_PERIB_INTB201(void) __attribute__ ((interrupt));
//;0x0328 PERIB INTB202
void INT_Excep_PERIB_INTB202(void) __attribute__ ((interrupt));
//;0x032C PERIB INTB203
void INT_Excep_PERIB_INTB203(void) __attribute__ ((interrupt));
//;0x0320 PERIB INTB204
void INT_Excep_PERIB_INTB204(void) __attribute__ ((interrupt));
//;0x0334 PERIB INTB205
void INT_Excep_PERIB_INTB205(void) __attribute__ ((interrupt));
//;0x0338 PERIB INTB206
void INT_Excep_PERIB_INTB206(void) __attribute__ ((interrupt));
//;0x033C PERIB INTB207
void INT_Excep_PERIB_INTB207(void) __attribute__ ((interrupt));
//;0x0340 PERIA INTA208
void INT_Excep_PERIA_INTA208(void) __attribute__ ((interrupt));
//;0x0344 PERIA INTA209
void INT_Excep_PERIA_INTA209(void) __attribute__ ((interrupt));
//;0x0348 PERIA INTA210
void INT_Excep_PERIA_INTA210(void) __attribute__ ((interrupt));
//;0x034C PERIA INTA211
void INT_Excep_PERIA_INTA211(void) __attribute__ ((interrupt));
//;0x0350 PERIA INTA212
void INT_Excep_PERIA_INTA212(void) __attribute__ ((interrupt));
//;0x0354 PERIA INTA213
void INT_Excep_PERIA_INTA213(void) __attribute__ ((interrupt));
//;0x0358 PERIA INTA214
void INT_Excep_PERIA_INTA214(void) __attribute__ ((interrupt));
//;0x035C PERIA INTA215
void INT_Excep_PERIA_INTA215(void) __attribute__ ((interrupt));
//;0x0360 PERIA INTA216
void INT_Excep_PERIA_INTA216(void) __attribute__ ((interrupt));
//;0x0364 PERIA INTA217
void INT_Excep_PERIA_INTA217(void) __attribute__ ((interrupt));
//;0x0368 PERIA INTA218
void INT_Excep_PERIA_INTA218(void) __attribute__ ((interrupt));
//;0x036C PERIA INTA219
void INT_Excep_PERIA_INTA219(void) __attribute__ ((interrupt));
//;0x0370 PERIA INTA220
void INT_Excep_PERIA_INTA220(void) __attribute__ ((interrupt));
//;0x0374 PERIA INTA221
void INT_Excep_PERIA_INTA221(void) __attribute__ ((interrupt));
//;0x0378 PERIA INTA222
void INT_Excep_PERIA_INTA222(void) __attribute__ ((interrupt));
//;0x037C PERIA INTA223
void INT_Excep_PERIA_INTA223(void) __attribute__ ((interrupt));
//;0x0380 PERIA INTA224
void INT_Excep_PERIA_INTA224(void) __attribute__ ((interrupt));
//;0x0384 PERIA INTA225
void INT_Excep_PERIA_INTA225(void) __attribute__ ((interrupt));
//;0x0388 PERIA INTA226
void INT_Excep_PERIA_INTA226(void) __attribute__ ((interrupt));
//;0x038C PERIA INTA227
void INT_Excep_PERIA_INTA227(void) __attribute__ ((interrupt));
//;0x0390 PERIA INTA228
void INT_Excep_PERIA_INTA228(void) __attribute__ ((interrupt));
//;0x0394 PERIA INTA229
void INT_Excep_PERIA_INTA229(void) __attribute__ ((interrupt));
//;0x0398 PERIA INTA230
void INT_Excep_PERIA_INTA230(void) __attribute__ ((interrupt));
//;0x039C PERIA INTA231
void INT_Excep_PERIA_INTA231(void) __attribute__ ((interrupt));
//;0x03A0 PERIA INTA232
void INT_Excep_PERIA_INTA232(void) __attribute__ ((interrupt));
//;0x03A4 PERIA INTA233
void INT_Excep_PERIA_INTA233(void) __attribute__ ((interrupt));
//;0x03A8 PERIA INTA234
void INT_Excep_PERIA_INTA234(void) __attribute__ ((interrupt));
//;0x03AC PERIA INTA235
void INT_Excep_PERIA_INTA235(void) __attribute__ ((interrupt));
//;0x03B0 PERIA INTA236
void INT_Excep_PERIA_INTA236(void) __attribute__ ((interrupt));
//;0x04B4 PERIA INTA237
void INT_Excep_PERIA_INTA237(void) __attribute__ ((interrupt));
//;0x03B8 PERIA INTA238
void INT_Excep_PERIA_INTA238(void) __attribute__ ((interrupt));
//;0x03BC PERIA INTA239
void INT_Excep_PERIA_INTA239(void) __attribute__ ((interrupt));
//;0x03C0 PERIA INTA240
void INT_Excep_PERIA_INTA240(void) __attribute__ ((interrupt));
//;0x03C4 PERIA INTA241
void INT_Excep_PERIA_INTA241(void) __attribute__ ((interrupt));
//;0x03C8 PERIA INTA242
void INT_Excep_PERIA_INTA242(void) __attribute__ ((interrupt));
//;0x03CC PERIA INTA243
void INT_Excep_PERIA_INTA243(void) __attribute__ ((interrupt));
//;0x03D0 PERIA INTA244
void INT_Excep_PERIA_INTA244(void) __attribute__ ((interrupt));
//;0x03D4 PERIA INTA245
void INT_Excep_PERIA_INTA245(void) __attribute__ ((interrupt));
//;0x03D8 PERIA INTA246
void INT_Excep_PERIA_INTA246(void) __attribute__ ((interrupt));
//;0x03DC PERIA INTA247
void INT_Excep_PERIA_INTA247(void) __attribute__ ((interrupt));
//;0x03E0 PERIA INTA248
void INT_Excep_PERIA_INTA248(void) __attribute__ ((interrupt));
//;0x03E4 PERIA INTA249
void INT_Excep_PERIA_INTA249(void) __attribute__ ((interrupt));
//;0x03E8 PERIA INTA250
void INT_Excep_PERIA_INTA250(void) __attribute__ ((interrupt));
//;0x03EC PERIA INTA251
void INT_Excep_PERIA_INTA251(void) __attribute__ ((interrupt));
//;0x03F0 PERIA INTA252
void INT_Excep_PERIA_INTA252(void) __attribute__ ((interrupt));
//;0x03F4 PERIA INTA253
void INT_Excep_PERIA_INTA253(void) __attribute__ ((interrupt));
//;0x03F8 PERIA INTA254
void INT_Excep_PERIA_INTA254(void) __attribute__ ((interrupt));
//;0x03FC PERIA INTA255
void INT_Excep_PERIA_INTA255(void) __attribute__ ((interrupt));
//;<<VECTOR DATA START (POWER ON RESET)>>
//;Power On Reset PC
extern void PowerON_Reset(void) __attribute__ ((interrupt));
//;<<VECTOR DATA END (POWER ON RESET)>>
#endif

206
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/reset_program.asm Normal file
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/***************************************************************/
/* */
/* PROJECT NAME : RTOSDemo */
/* FILE : reset_program.asm */
/* DESCRIPTION : Reset Program */
/* CPU SERIES : RX700 */
/* CPU TYPE : RX71M */
/* */
/* This file is generated by e2 studio. */
/* */
/***************************************************************/
/************************************************************************/
/* File Version: V1.01 */
/* Date Generated: 04/03/2015 */
/************************************************************************/
/*reset_program.asm*/
.list
.section .text
.global _PowerON_Reset /*global Start routine */
.extern _HardwareSetup /*external Sub-routine to initialise Hardware*/
.extern _data
.extern _mdata
.extern _ebss
.extern _bss
.extern _edata
.extern _main
.extern _ustack
.extern _istack
.extern _rvectors
.extern _exit
_PowerON_Reset :
/* initialise user stack pointer */
mvtc #_ustack,USP
/* initialise interrupt stack pointer */
mvtc #_istack,ISP
#ifdef __RXv2__
/* setup exception vector */
mvtc #_ExceptVectors, extb /* EXCEPTION VECTOR ADDRESS */
#endif
/* setup intb */
mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */
/* setup FPSW */
mvtc #100h, fpsw
/* load data section from ROM to RAM */
mov #_mdata,r2 /* src ROM address of data section in R2 */
mov #_data,r1 /* dest start RAM address of data section in R1 */
mov #_edata,r3 /* end RAM address of data section in R3 */
sub r1,r3 /* size of data section in R3 (R3=R3-R1) */
#ifdef __RX_ALLOW_STRING_INSNS__
smovf /* block copy R3 bytes from R2 to R1 */
#else
cmp #0, r3
beq 2f
1: mov.b [r2+], r5
mov.b r5, [r1+]
sub #1, r3
bne 1b
2:
#endif
/* bss initialisation : zero out bss */
mov #00h,r2 /* load R2 reg with zero */
mov #_ebss, r3 /* store the end address of bss in R3 */
mov #_bss, r1 /* store the start address of bss in R1 */
sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */
sstr.b
/* call the hardware initialiser */
mov #_HardwareSetup,r7
jsr r7
nop
/* setup PSW */
mvtc #10000h, psw /* Set Ubit & Ibit for PSW */
/* change PSW PM to user-mode */
MVFC PSW,R1
/* DON'T CHANGE TO USER MODE OR #00100000h,R1 */
PUSH.L R1
MVFC PC,R1
ADD #10,R1
PUSH.L R1
RTE
NOP
NOP
#ifdef CPPAPP
mov #__rx_init,r7
jsr r7
#endif
/* start user program */
mov #_main,r7
jsr r7
mov #_exit,r7
jsr r7
#ifdef CPPAPP
.global _rx_run_preinit_array
.type _rx_run_preinit_array,@function
_rx_run_preinit_array:
mov #__preinit_array_start,r1
mov #__preinit_array_end,r2
mov #_rx_run_inilist,r7
jsr r7
.global _rx_run_init_array
.type _rx_run_init_array,@function
_rx_run_init_array:
mov #__init_array_start,r1
mov #__init_array_end,r2
mov #4, r3
mov #_rx_run_inilist,r7
jsr r7
.global _rx_run_fini_array
.type _rx_run_fini_array,@function
_rx_run_fini_array:
mov #__fini_array_start,r2
mov #__fini_array_end,r1
mov #-4, r3
/* fall through */
_rx_run_inilist:
next_inilist:
cmp r1,r2
beq.b done_inilist
mov.l [r1],r4
cmp #-1, r4
beq.b skip_inilist
cmp #0, r4
beq.b skip_inilist
pushm r1-r3
jsr r4
popm r1-r3
skip_inilist:
add r3,r1
mov #next_inilist,r7
jsr r7
done_inilist:
rts
.section .init,"ax"
.balign 4
.global __rx_init
__rx_init:
.section .fini,"ax"
.balign 4
.global __rx_fini
__rx_fini:
mov #_rx_run_fini_array,r7
jsr r7
.section .sdata
.balign 4
.global __gp
.weak __gp
__gp:
.section .data
.global ___dso_handle
.weak ___dso_handle
___dso_handle:
.long 0
.section .init,"ax"
mov #_rx_run_preinit_array,r7
jsr r7
mov #_rx_run_init_array,r7
jsr r7
rts
.global __rx_init_end
__rx_init_end:
.section .fini,"ax"
rts
.global __rx_fini_end
__rx_fini_end:
#endif
/* call to exit*/
_exit:
bra _loop_here
_loop_here:
bra _loop_here
.text
.end

28
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/typedefine.h Normal file
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/***************************************************************/
/* */
/* PROJECT NAME : RTOSDemo */
/* FILE : typedefine.h */
/* DESCRIPTION : Aliases of Integer Type */
/* CPU SERIES : RX700 */
/* CPU TYPE : RX71M */
/* */
/* This file is generated by e2 studio. */
/* */
/***************************************************************/
/************************************************************************/
/* File Version: V1.00 */
/* Date Generated: 08/07/2013 */
/************************************************************************/
typedef signed char _SBYTE;
typedef unsigned char _UBYTE;
typedef signed short _SWORD;
typedef unsigned short _UWORD;
typedef signed int _SINT;
typedef unsigned int _UINT;
typedef signed long _SDWORD;
typedef unsigned long _UDWORD;
typedef signed long long _SQWORD;
typedef unsigned long long _UQWORD;

867
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Renesas_Source/vector_table.c Normal file
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/***************************************************************/
/* */
/* PROJECT NAME : RTOSDemo */
/* FILE : vector_table.c */
/* DESCRIPTION : Vector Table */
/* CPU SERIES : RX700 */
/* CPU TYPE : RX71M */
/* */
/* This file is generated by e2 studio. */
/* */
/***************************************************************/
/************************************************************************/
/* File Version: V1.00 */
/* Date Modified: 18/12/2014 */
/************************************************************************/
#include "interrupt_handlers.h"
typedef void (*fp) (void);
extern void PowerON_Reset (void);
extern void stack (void);
extern void vTickISR( void );
extern void vSoftwareInterruptISR( void );
extern void vIntQTimerISR0( void );
extern void vIntQTimerISR1( void );
#define EXVECT_SECT __attribute__ ((section (".exvectors")))
const void *ExceptVectors[] EXVECT_SECT = {
//;0xffffff80 Reserved
(fp)0,
//;0xffffff84 Reserved
(fp)0,
//;0xffffff88 Reserved
(fp)0,
//;0xffffff8C Reserved
(fp)0,
//;0xffffff90 Reserved
(fp)0,
//;0xffffff94 Reserved
(fp)0,
//;0xffffff98 Reserved
(fp)0,
//;0xffffff9C Reserved
(fp)0,
//;0xffffffA0 Reserved
(fp)0xFFFFFFFF,
//;0xffffffA4 Reserved
(fp)0xFFFFFFFF,
//;0xffffffA8 Reserved
(fp)0xFFFFFFFF,
//;0xffffffAC Reserved
(fp)0xFFFFFFFF,
//;0xffffffB0 Reserved
(fp)0,
//;0xffffffB4 Reserved
(fp)0,
//;0xffffffB8 Reserved
(fp)0,
//;0xffffffBC Reserved
(fp)0,
//;0xffffffC0 Reserved
(fp)0,
//;0xffffffC4 Reserved
(fp)0,
//;0xffffffC8 Reserved
(fp)0,
//;0xffffffCC Reserved
(fp)0,
//;0xffffffd0 Exception(Supervisor Instruction)
INT_Excep_SuperVisorInst,
//;0xffffffd4 Exception(Access Instruction)
INT_Excep_AccessInst,
//;0xffffffd8 Reserved
Dummy,
//;0xffffffdc Exception(Undefined Instruction)
INT_Excep_UndefinedInst,
//;0xffffffe0 Reserved
Dummy,
//;0xffffffe4 Exception(Floating Point)
INT_Excep_FloatingPoint,
//;0xffffffe8 Reserved
Dummy,
//;0xffffffec Reserved
Dummy,
//;0xfffffff0 Reserved
Dummy,
//;0xfffffff4 Reserved
Dummy,
//;0xfffffff8 NMI
INT_NonMaskableInterrupt,
};
#define FVECT_SECT __attribute__ ((section (".fvectors")))
const void *HardwareVectors[] FVECT_SECT = {
//;0xfffffffc RESET
//;<<VECTOR DATA START (POWER ON RESET)>>
//;Power On Reset PC
/*(void*)*/ PowerON_Reset
//;<<VECTOR DATA END (POWER ON RESET)>>
};
#define RVECT_SECT __attribute__ ((section (".rvectors")))
const fp RelocatableVectors[] RVECT_SECT = {
//;0x0000 Reserved
(fp)0,
//;0x0004 Reserved
(fp)0,
//;0x0008 Reserved
(fp)0,
//;0x000C Reserved
(fp)0,
//;0x0010 Reserved
(fp)0,
//;0x0014 Reserved
(fp)0,
//;0x0018 Reserved
(fp)0,
//;0x001C Reserved
(fp)0,
//;0x0020 Reserved
(fp)0,
//;0x0024 Reserved
(fp)0,
//;0x0028 Reserved
(fp)0,
//;0x002C Reserved
(fp)0,
//;0x0030 Reserved
(fp)0,
//;0x0034 Reserved
(fp)0,
//;0x0038 Reserved
(fp)0,
//;0x003C Reserved
(fp)0,
//;0x0040 BUSERR
(fp)INT_Excep_BSC_BUSERR,
//;0x0044 Reserved
(fp)0,
//;0x0048 RAMERR
(fp)INT_Excep_RAM_RAMERR,
//;0x004C Reserved
(fp)0,
//;0x0050 Reserved
(fp)0,
//;0x0054 FIFERR
(fp)INT_Excep_FCU_FIFERR,
//;0x0058 Reserved
(fp)0,
//;0x005C FRDYI
(fp)INT_Excep_FCU_FRDYI,
//;0x0060 Reserved
(fp)0,
//;0x0064 Reserved
(fp)0,
//;0x0068 SWINT2
(fp)INT_Excep_ICU_SWINT2,
//;0x006C SWINT
(fp)vSoftwareInterruptISR,
//;0x0070 CMI0
(fp)vTickISR,
//;0x0074 CMI1
(fp)INT_Excep_CMT1_CMI1,
//;0x0078 CMWI0
(fp)INT_Excep_CMTW0_CMWI0,
//;0x007C CMWI1
(fp)INT_Excep_CMTW1_CMWI1,
//;0x0080 D0FIFO2
(fp)INT_Excep_USBA_D0FIFO2,
//;0x0084 D1FIFO2
(fp)INT_Excep_USBA_D1FIFO2,
//;0x0088 D0FIFO0
(fp)INT_Excep_USB0_D0FIFO0,
//;0x008C D1FIFO0
(fp)INT_Excep_USB0_D1FIFO0,
//;0x0090 Reserved
(fp)0,
//;0x0094 Reserved
(fp)0,
//;0x0098 SPRI0
(fp)INT_Excep_RSPI0_SPRI0,
//;0x009C SPTI0
(fp)INT_Excep_RSPI0_SPTI0,
//;0x00A0 SPRI1
(fp)INT_Excep_RSPI1_SPRI1,
//;0x00A4 SPTI1
(fp)INT_Excep_RSPI1_SPTI1,
//;0x00A8 SPRI
(fp)INT_Excep_QSPI_SPRI,
//;0x00AC SPTI
(fp)INT_Excep_QSPI_SPTI,
//;0x00B0 SBFAI
(fp)INT_Excep_SDHI_SBFAI,
//;0x00B4 MBFAI
(fp)INT_Excep_MMCIF_MBFAI,
//;0x00B8 SSITX0
(fp)INT_Excep_SSI0_SSITXI0,
//;0x00BC SSIRX0
(fp)INT_Excep_SSI0_SSIRXI0,
//;0x00C0 SSIRTI1
(fp)INT_Excep_SSI1_SSIRTI1,
//;0x00C4 Reserved
(fp)0,
//;0x00C8 IDEI
(fp)INT_Excep_SRC_IDEI,
//;0x00CC ODFI
(fp)INT_Excep_SRC_ODFI,
//;0x00D0 RXI0
(fp)INT_Excep_RIIC0_RXI0,
//;0x00D4C TXI0
(fp)INT_Excep_RIIC0_TXI0,
//;0x00D8 RXI2
(fp)INT_Excep_RIIC2_RXI2,
//;0x00DC TXI2
(fp)INT_Excep_RIIC2_TXI2,
//;0x00E0 Reserved
(fp)0,
//;0x00E4 Reserved
(fp)0,
//;0x00E8 RXI0
(fp)INT_Excep_SCI0_RXI0,
//;0x00EC TXI0
(fp)INT_Excep_SCI0_TXI0,
//;0x00F0 RXI1
(fp)INT_Excep_SCI1_RXI1,
//;0x00F4 TXI1
(fp)INT_Excep_SCI1_TXI1,
//;0x00F8 RXI2
(fp)INT_Excep_SCI2_RXI2,
//;0x00FC TXI2
(fp)INT_Excep_SCI2_TXI2,
//;0x0100 IRQ0
(fp)INT_Excep_ICU_IRQ0,
//;0x0104 IRQ1
(fp)INT_Excep_ICU_IRQ1,
//;0x0108 IRQ2
(fp)INT_Excep_ICU_IRQ2,
//;0x010C IRQ3
(fp)INT_Excep_ICU_IRQ3,
//;0x0110 IRQ4
(fp)INT_Excep_ICU_IRQ4,
//;0x0114 IRQ5
(fp)INT_Excep_ICU_IRQ5,
//;0x0118 IRQ6
(fp)INT_Excep_ICU_IRQ6,
//;0x011C IRQ7
(fp)INT_Excep_ICU_IRQ7,
//;0x0120 IRQ8
(fp)INT_Excep_ICU_IRQ8,
//;0x0124 IRQ9
(fp)INT_Excep_ICU_IRQ9,
//;0x0128 IRQ10
(fp)INT_Excep_ICU_IRQ10,
//;0x012C IRQ11
(fp)INT_Excep_ICU_IRQ11,
//;0x0130 IRQ12
(fp)INT_Excep_ICU_IRQ12,
//;0x0134 IRQ13
(fp)INT_Excep_ICU_IRQ13,
//;0x0138 IRQ14
(fp)INT_Excep_ICU_IRQ14,
//;0x013C IRQ15
(fp)INT_Excep_ICU_IRQ15,
//;0x0140 RXI3
(fp)INT_Excep_SCI3_RXI3,
//;0x0144 TXI3
(fp)INT_Excep_SCI3_TXI3,
//;0x0148 RXI4
(fp)INT_Excep_SCI4_RXI4,
//;0x014C TXI4
(fp)INT_Excep_SCI4_TXI4,
//;0x0150 RXI5
(fp)INT_Excep_SCI5_RXI5,
//;0x0154 TXI5
(fp)INT_Excep_SCI5_TXI5,
//;0x0158 RXI6
(fp)INT_Excep_SCI6_RXI6,
//;0x015C TXI6
(fp)INT_Excep_SCI6_TXI6,
//;0x0160 COMPA1
(fp)INT_Excep_LVD1_LVD1,
//;0x0164 COMPA2
(fp)INT_Excep_LVD2_LVD2,
//;0x0168 USBR0
(fp)INT_Excep_USB0_USBR0,
//;0x016C Reserved
(fp)0,
//;0x0170 ALM
(fp)INT_Excep_RTC_ALM,
//;0x0174 PRD
(fp)INT_Excep_RTC_PRD,
//;0x0178 HSUSBR
(fp)INT_Excep_USBA_USBAR,
//;0x017C IWUNI
(fp)INT_Excep_IWDT_IWUNI,
//;0x0180 WUNI
(fp)INT_Excep_WDT_WUNI,
//;0x0184 PCDFI
(fp)INT_Excep_PDC_PCDFI,
//;0x0188 RXI7
(fp)INT_Excep_SCI7_RXI7,
//;0x018C TXI7
(fp)INT_Excep_SCI7_TXI7,
//;0x0190 RXIF8
(fp)INT_Excep_SCIFA8_RXIF8,
//;0x0194 TXIF8
(fp)INT_Excep_SCIFA8_TXIF8,
//;0x0198 RXIF9
(fp)INT_Excep_SCIFA9_RXIF9,
//;0x019C TXIF9
(fp)INT_Excep_SCIFA9_TXIF9,
//;0x01A0 RXIF10
(fp)INT_Excep_SCIFA10_RXIF10,
//;0x01A4 TXIF10
(fp)INT_Excep_SCIFA10_TXIF10,
//;0x01A8 GROUPBE0
(fp)INT_Excep_ICU_GROUPBE0,
//;0x01AC Reserved
(fp)0,
//;0x01B0 Reserved
(fp)0,
//;0x01B4 Reserved
(fp)0,
//;0x01B8 GROUPBL0
(fp)INT_Excep_ICU_GROUPBL0,
//;0x01BC GROUPBL1
(fp)INT_Excep_ICU_GROUPBL1,
//;0x01C0 GROUPAL0
(fp)INT_Excep_ICU_GROUPAL0,
//;0x01C4 GROUPAL1
(fp)INT_Excep_ICU_GROUPAL1,
//;0x01C8 RXIF11
(fp)INT_Excep_SCIFA11_RXIF11,
//;0x01CC TXIF11
(fp)INT_Excep_SCIFA11_TXIF11,
//;0x01D0 RXIF12
(fp)INT_Excep_SCI12_RXI12,
//;0x01D4 TXIF12
(fp)INT_Excep_SCI12_TXI12,
//;0x01D8 Reserved
(fp)0,
//;0x01DC Reserved
(fp)0,
//;0x01E0 DMAC0I
(fp)INT_Excep_DMAC_DMAC0I,
//;0x01E4 DMAC1I
(fp)INT_Excep_DMAC_DMAC1I,
//;0x01E8 DMAC2I
(fp)INT_Excep_DMAC_DMAC2I,
//;0x01EC DMAC3I
(fp)INT_Excep_DMAC_DMAC3I,
//;0x01F0 DMAC74I
(fp)INT_Excep_DMAC_DMAC74I,
//;0x01F4 OST
(fp)INT_Excep_OST_OST,
//;0x01F8 EXDMAC0I
(fp)INT_Excep_EXDMAC_EXDMAC0I,
//;0x01FC EXDMAC1I
(fp)INT_Excep_EXDMAC_EXDMAC1I,
//;0x0200 INTB128
(fp)vIntQTimerISR0,
//;0x0204 INTB129
(fp)vIntQTimerISR1,
//;0x0208 INTB130
(fp)INT_Excep_PERIB_INTB130,
//;0x020C INTB131
(fp)INT_Excep_PERIB_INTB131,
//;0x0210 INTB132
(fp)INT_Excep_PERIB_INTB132,
//;0x0214 INTB133
(fp)INT_Excep_PERIB_INTB133,
//;0x0218 INTB134
(fp)INT_Excep_PERIB_INTB134,
//;0x021C INTB135
(fp)INT_Excep_PERIB_INTB135,
//;0x0220 INTB136
(fp)INT_Excep_PERIB_INTB136,
//;0x0224 INTB137
(fp)INT_Excep_PERIB_INTB137,
//;0x0228 INTB138
(fp)INT_Excep_PERIB_INTB138,
//;0x022C INTB139
(fp)INT_Excep_PERIB_INTB139,
//;0x0230 INTB140
(fp)INT_Excep_PERIB_INTB140,
//;0x0234 INTB141
(fp)INT_Excep_PERIB_INTB141,
//;0x0238 INTB142
(fp)INT_Excep_PERIB_INTB142,
//;0x023C INTB143
(fp)INT_Excep_PERIB_INTB143,
//;0x0240 INTB144
(fp)INT_Excep_PERIB_INTB144,
//;0x0244 INTB145
(fp)INT_Excep_PERIB_INTB145,
//;0x0248 INTB146
(fp)INT_Excep_PERIB_INTB146,
//;0x024C INTB147
(fp)INT_Excep_PERIB_INTB147,
//;0x0250 INTB148
(fp)INT_Excep_PERIB_INTB148,
//;0x02540 INTB149
(fp)INT_Excep_PERIB_INTB149,
//;0x0258 INTB150
(fp)INT_Excep_PERIB_INTB150,
//;0x025C INTB151
(fp)INT_Excep_PERIB_INTB151,
//;0x0260 INTB152
(fp)INT_Excep_PERIB_INTB152,
//;0x0264 INTB153
(fp)INT_Excep_PERIB_INTB153,
//;0x0268 INTB154
(fp)INT_Excep_PERIB_INTB154,
//;0x026C INTB155
(fp)INT_Excep_PERIB_INTB155,
//;0x0270 INTB156
(fp)INT_Excep_PERIB_INTB156,
//;0x0274 INTB157
(fp)INT_Excep_PERIB_INTB157,
//;0x0278 INTB158
(fp)INT_Excep_PERIB_INTB158,
//;0x027C INTB159
(fp)INT_Excep_PERIB_INTB159,
//;0x0280 INTB160
(fp)INT_Excep_PERIB_INTB160,
//;0x0284 INTB161
(fp)INT_Excep_PERIB_INTB161,
//;0x0288 INTB162
(fp)INT_Excep_PERIB_INTB162,
//;0x028C INTB163
(fp)INT_Excep_PERIB_INTB163,
//;0x0290 INTB164
(fp)INT_Excep_PERIB_INTB164,
//;0x0294 PERIB INTB165
(fp)INT_Excep_PERIB_INTB165,
//;0x0298 PERIB INTB166
(fp)INT_Excep_PERIB_INTB166,
//;0x029C PERIB INTB167
(fp)INT_Excep_PERIB_INTB167,
//;0x02A0 PERIB INTB168
(fp)INT_Excep_PERIB_INTB168,
//;0x02A4 PERIB INTB169
(fp)INT_Excep_PERIB_INTB169,
//;0x02A8 PERIB INTB170
(fp)INT_Excep_PERIB_INTB170,
//;0x02AC PERIB INTB171
(fp)INT_Excep_PERIB_INTB171,
//;0x02B0 PERIB INTB172
(fp)INT_Excep_PERIB_INTB172,
//;0x02B4 PERIB INTB173
(fp)INT_Excep_PERIB_INTB173,
//;0x02B8 PERIB INTB174
(fp)INT_Excep_PERIB_INTB174,
//;0x02BC PERIB INTB175
(fp)INT_Excep_PERIB_INTB175,
//;0x02C0 PERIB INTB176
(fp)INT_Excep_PERIB_INTB176,
//;0x02C4 PERIB INTB177
(fp)INT_Excep_PERIB_INTB177,
//;0x02C8 PERIB INTB178
(fp)INT_Excep_PERIB_INTB178,
//;0x02CC PERIB INTB179
(fp)INT_Excep_PERIB_INTB179,
//;0x02D0 PERIB INTB180
(fp)INT_Excep_PERIB_INTB180,
//;0x02D4 PERIB INTB181
(fp)INT_Excep_PERIB_INTB181,
//;0x02D8 PERIB INTB182
(fp)INT_Excep_PERIB_INTB182,
//;0x02DC PERIB INTB183
(fp)INT_Excep_PERIB_INTB183,
//;0x02E0 PERIB INTB184
(fp)INT_Excep_PERIB_INTB184,
//;0x02E4 PERIB INTB185
(fp)INT_Excep_PERIB_INTB185,
//;0x02E8 PERIB INTB186
(fp)INT_Excep_PERIB_INTB186,
//;0x02EC PERIB INTB187
(fp)INT_Excep_PERIB_INTB187,
//;0x02F0 PERIB INTB188
(fp)INT_Excep_PERIB_INTB188,
//;0x02F4 PERIB INTB189
(fp)INT_Excep_PERIB_INTB189,
//;0x02F8 PERIB INTB190
(fp)INT_Excep_PERIB_INTB190,
//;0x02FC PERIB INTB191
(fp)INT_Excep_PERIB_INTB191,
//;0x0300 PERIB INTB192
(fp)INT_Excep_PERIB_INTB192,
//;0x0304 PERIB INTB193
(fp)INT_Excep_PERIB_INTB193,
//;0x0308 PERIB INTB194
(fp)INT_Excep_PERIB_INTB194,
//;0x030C PERIB INTB195
(fp)INT_Excep_PERIB_INTB195,
//;0x0310 PERIB INTB196
(fp)INT_Excep_PERIB_INTB196,
//;0x0314 PERIB INTB197
(fp)INT_Excep_PERIB_INTB197,
//;0x0318 PERIB INTB198
(fp)INT_Excep_PERIB_INTB198,
//;0x031C PERIB INTB199
(fp)INT_Excep_PERIB_INTB199,
//;0x0320 PERIB INTB200
(fp)INT_Excep_PERIB_INTB200,
//;0x0324 PERIB INTB201
(fp)INT_Excep_PERIB_INTB201,
//;0x0328 PERIB INTB202
(fp)INT_Excep_PERIB_INTB202,
//;0x032C PERIB INTB203
(fp)INT_Excep_PERIB_INTB203,
//;0x0320 PERIB INTB204
(fp)INT_Excep_PERIB_INTB204,
//;0x0334 PERIB INTB205
(fp)INT_Excep_PERIB_INTB205,
//;0x0338 PERIB INTB206
(fp)INT_Excep_PERIB_INTB206,
//;0x033C PERIB INTB207
(fp)INT_Excep_PERIB_INTB207,
//;0x0340 PERIA INTA208
(fp)INT_Excep_PERIA_INTA208,
//;0x0344 PERIA INTA209
(fp)INT_Excep_PERIA_INTA209,
//;0x0348 PERIA INTA210
(fp)INT_Excep_PERIA_INTA210,
//;0x034C PERIA INTA211
(fp)INT_Excep_PERIA_INTA211,
//;0x0350 PERIA INTA212
(fp)INT_Excep_PERIA_INTA212,
//;0x0354 PERIA INTA213
(fp)INT_Excep_PERIA_INTA213,
//;0x0358 PERIA INTA214
(fp)INT_Excep_PERIA_INTA214,
//;0x035C PERIA INTA215
(fp)INT_Excep_PERIA_INTA215,
//;0x0360 PERIA INTA216
(fp)INT_Excep_PERIA_INTA216,
//;0x0364 PERIA INTA217
(fp)INT_Excep_PERIA_INTA217,
//;0x0368 PERIA INTA218
(fp)INT_Excep_PERIA_INTA218,
//;0x036C PERIA INTA219
(fp)INT_Excep_PERIA_INTA219,
//;0x0370 PERIA INTA220
(fp)INT_Excep_PERIA_INTA220,
//;0x0374 PERIA INTA221
(fp)INT_Excep_PERIA_INTA221,
//;0x0378 PERIA INTA222
(fp)INT_Excep_PERIA_INTA222,
//;0x037C PERIA INTA223
(fp)INT_Excep_PERIA_INTA223,
//;0x0380 PERIA INTA224
(fp)INT_Excep_PERIA_INTA224,
//;0x0384 PERIA INTA225
(fp)INT_Excep_PERIA_INTA225,
//;0x0388 PERIA INTA226
(fp)INT_Excep_PERIA_INTA226,
//;0x038C PERIA INTA227
(fp)INT_Excep_PERIA_INTA227,
//;0x0390 PERIA INTA228
(fp)INT_Excep_PERIA_INTA228,
//;0x0394 PERIA INTA229
(fp)INT_Excep_PERIA_INTA229,
//;0x0398 PERIA INTA230
(fp)INT_Excep_PERIA_INTA230,
//;0x039C PERIA INTA231
(fp)INT_Excep_PERIA_INTA231,
//;0x03A0 PERIA INTA232
(fp)INT_Excep_PERIA_INTA232,
//;0x03A4 PERIA INTA233
(fp)INT_Excep_PERIA_INTA233,
//;0x03A8 PERIA INTA234
(fp)INT_Excep_PERIA_INTA234,
//;0x03AC PERIA INTA235
(fp)INT_Excep_PERIA_INTA235,
//;0x03B0 PERIA INTA236
(fp)INT_Excep_PERIA_INTA236,
//;0x04B4 PERIA INTA237
(fp)INT_Excep_PERIA_INTA237,
//;0x03B8 PERIA INTA238
(fp)INT_Excep_PERIA_INTA238,
//;0x03BC PERIA INTA239
(fp)INT_Excep_PERIA_INTA239,
//;0x03C0 PERIA INTA240
(fp)INT_Excep_PERIA_INTA240,
//;0x03C4 PERIA INTA241
(fp)INT_Excep_PERIA_INTA241,
//;0x03C8 PERIA INTA242
(fp)INT_Excep_PERIA_INTA242,
//;0x03CC PERIA INTA243
(fp)INT_Excep_PERIA_INTA243,
//;0x03D0 PERIA INTA244
(fp)INT_Excep_PERIA_INTA244,
//;0x03D4 PERIA INTA245
(fp)INT_Excep_PERIA_INTA245,
//;0x03D8 PERIA INTA246
(fp)INT_Excep_PERIA_INTA246,
//;0x03DC PERIA INTA247
(fp)INT_Excep_PERIA_INTA247,
//;0x03E0 PERIA INTA248
(fp)INT_Excep_PERIA_INTA248,
//;0x03E4 PERIA INTA249
(fp)INT_Excep_PERIA_INTA249,
//;0x03E8 PERIA INTA250
(fp)INT_Excep_PERIA_INTA250,
//;0x03EC PERIA INTA251
(fp)INT_Excep_PERIA_INTA251,
//;0x03F0 PERIA INTA252
(fp)INT_Excep_PERIA_INTA252,
//;0x03F4 PERIA INTA253
(fp)INT_Excep_PERIA_INTA253,
//;0x03F8 PERIA INTA254
(fp)INT_Excep_PERIA_INTA254,
//;0x03FC PERIA INTA255
(fp)INT_Excep_PERIA_INTA255,
};
#define OFS_SPCC __attribute__ ((section (".ofs1"))) /* 0x00120040 */
#define OFS_TMEF __attribute__ ((section (".ofs2"))) /* 0x00120048 */
#define OFS_OSIC __attribute__ ((section (".ofs3"))) /* 0x00120050 */
#define OFS_REG __attribute__ ((section (".ofs4"))) /* 0x00120060 */
const unsigned long __SPCCreg OFS_SPCC = 0xffffffff;
const unsigned long __TMEFreg OFS_TMEF = 0xffffffff;
// OSIC register (ID codes)
const unsigned long __OSISreg[4] OFS_OSIC = {
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff,
};
// TMINF register
const unsigned long __TMINFreg OFS_REG = 0xffffffff;
// MDE register (Single Chip Mode)
#ifdef __RX_BIG_ENDIAN__
const unsigned long __MDEreg OFS_REG = 0xfffffff8; // big
#else
const unsigned long __MDEreg OFS_REG = 0xffffffff; // little
#endif
// OFS0 register
const unsigned long __OFS0reg OFS_REG = 0xffffffff;
// OFS1 register
const unsigned long __OFS1reg OFS_REG = 0xffffffff;

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_cgc.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for CGC module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_cgc.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: R_CGC_Create
* Description : This function initializes the clock generator.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_CGC_Create(void)
{
volatile uint32_t memorywaitcycle;
/* Set main clock control registers */
SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER24M;
SYSTEM.MOSCWTCR.BYTE = _5C_CGC_MOSCWTCR_VALUE;
/* Set main clock operation */
SYSTEM.MOSCCR.BIT.MOSTP = 0U;
/* Wait for main clock oscillator wait counter overflow */
while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);
/* Set system clock */
SYSTEM.SCKCR.LONG = _00000002_CGC_PCLKD_DIV_4 | _00000020_CGC_PCLKC_DIV_4 | _00000200_CGC_PCLKB_DIV_4 |
_00001000_CGC_PCLKA_DIV_2 | _00020000_CGC_BCLK_DIV_4 | _00000000_CGC_ICLK_DIV_1 |
_20000000_CGC_FCLK_DIV_4;
/* Set PLL circuit */
SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0000_CGC_PLL_SOURCE_MAIN | _1300_CGC_PLL_FREQ_MUL_10_0;
SYSTEM.PLLCR2.BIT.PLLEN = 0U;
/* Wait for PLL wait counter overflow */
while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);
/* Stop sub-clock */
RTC.RCR3.BIT.RTCEN = 0U;
/* Wait for the register modification to complete */
while (0U != RTC.RCR3.BIT.RTCEN);
/* Stop sub-clock */
SYSTEM.SOSCCR.BIT.SOSTP = 1U;
/* Wait for the register modification to complete */
while (1U != SYSTEM.SOSCCR.BIT.SOSTP);
/* Wait for sub-clock oscillation stopping */
while (0U != SYSTEM.OSCOVFSR.BIT.SOOVF);
/* Set UCLK */
SYSTEM.SCKCR2.WORD = _0040_CGC_UCLK_DIV_5 | _0001_SCKCR2_BIT0;
/* Set BCLK */
SYSTEM.SCKCR.BIT.PSTOP1 = 1U;
/* Set SDCLK */
SYSTEM.SCKCR.BIT.PSTOP0 = 1U;
/* Set memory wait cycle setting register */
SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U;
memorywaitcycle = SYSTEM.MEMWAIT.LONG;
memorywaitcycle++;
/* Set clock source */
SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL;
/* Set LOCO */
SYSTEM.LOCOCR.BIT.LCSTP = 0U;
}
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

218
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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_cgc.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for CGC module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef CGC_H
#define CGC_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
System Clock Control Register (SCKCR)
*/
/* Peripheral Module Clock D (PCLKD) */
#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */
#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */
#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */
#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */
#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */
#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */
#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */
/* Peripheral Module Clock C (PCLKC) */
#define _00000000_CGC_PCLKC_DIV_1 (0x00000000UL) /* x1 */
#define _00000010_CGC_PCLKC_DIV_2 (0x00000010UL) /* x1/2 */
#define _00000020_CGC_PCLKC_DIV_4 (0x00000020UL) /* x1/4 */
#define _00000030_CGC_PCLKC_DIV_8 (0x00000030UL) /* x1/8 */
#define _00000040_CGC_PCLKC_DIV_16 (0x00000040UL) /* x1/16 */
#define _00000050_CGC_PCLKC_DIV_32 (0x00000050UL) /* x1/32 */
#define _00000060_CGC_PCLKC_DIV_64 (0x00000060UL) /* x1/64 */
/* Peripheral Module Clock B (PCLKB) */
#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */
#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */
#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */
#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */
#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */
#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */
#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */
/* Peripheral Module Clock A (PCLKA) */
#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */
#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */
#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */
#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */
#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */
#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */
#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */
/* External Bus Clock (BCLK) */
#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */
#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */
#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */
#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */
#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */
#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */
#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */
/* System Clock (ICLK) */
#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */
#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */
#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */
#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */
#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */
#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */
#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */
/* System Clock (FCLK) */
#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */
#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */
#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */
#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */
#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */
#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */
#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */
/*
System Clock Control Register 2 (SCKCR2)
*/
#define _0010_CGC_UCLK_DIV_1 (0x0010U) /* x1/2 */
#define _0020_CGC_UCLK_DIV_3 (0x0020U) /* x1/3 */
#define _0030_CGC_UCLK_DIV_4 (0x0030U) /* x1/4 */
#define _0040_CGC_UCLK_DIV_5 (0x0040U) /* x1/5 */
#define _0001_SCKCR2_BIT0 (0x0001U) /* RESERVE BIT0 */
/*
System Clock Control Register 3 (SCKCR3)
*/
#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */
#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */
#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */
#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */
#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */
/*
PLL Control Register (PLLCR)
*/
/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */
#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */
#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */
/* PLL Clock Source Select (PLLSRCSEL) */
#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */
#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */
/* Frequency Multiplication Factor Select (STC[5:0]) */
#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */
#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */
#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */
#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */
#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */
#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */
#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */
#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */
#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */
#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */
#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */
#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */
#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */
#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */
#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */
#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */
#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */
#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */
#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */
#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */
#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */
#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */
#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */
#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */
#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */
#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */
#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */
#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */
#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */
#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */
#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */
#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */
#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */
#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */
#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */
#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */
#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */
#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */
#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */
#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */
#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */
/*
Oscillation Stop Detection Control Register (OSTDCR)
*/
/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */
#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */
/* Oscillation Stop Detection Function Enable (OSTDE) */
#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */
#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */
/*
High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)
*/
/* HOCO Frequency Setting (HCFRQ[1:0]) */
#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */
#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */
#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */
/*
Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
*/
/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */
#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */
#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */
#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */
#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */
/* Main Clock Oscillator Switch (MOSEL) */
#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */
#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */
/*
RTC Control Register 4 (RCR4)
*/
/* Count source select */
#define _00_RTC_SOURCE_SELECT_SUB (0x00U) /* Select sub-clock oscillator */
#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01U) /* Select main clock oscillator */
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
#define _5C_CGC_MOSCWTCR_VALUE (0x5CU) /* Main Clock Oscillator Wait Time */
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_CGC_Create(void);
/* Start user code for function. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_cgc_user.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for CGC module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_cgc.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_hardware_setup.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements system initializing function.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_cgc.h"
#include "r_cg_icu.h"
#include "r_cg_port.h"
#include "r_cg_sci.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: R_Systeminit
* Description : This function initializes every macro.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_Systeminit(void)
{
/* Enable writing to registers related to operating modes, LPC, CGC and software reset */
SYSTEM.PRCR.WORD = 0xA50BU;
/* Enable writing to MPC pin function control registers */
MPC.PWPR.BIT.B0WI = 0U;
MPC.PWPR.BIT.PFSWE = 1U;
/* Initialize non-existent pins */
PORT5.PDR.BYTE = 0x70U;
/* Set peripheral settings */
R_CGC_Create();
R_ICU_Create();
R_PORT_Create();
R_SCI7_Create();
/* Disable writing to MPC pin function control registers */
MPC.PWPR.BIT.PFSWE = 0U;
MPC.PWPR.BIT.B0WI = 1U;
/* Enable protection */
SYSTEM.PRCR.WORD = 0xA500U;
}
/***********************************************************************************************************************
* Function Name: HardwareSetup
* Description : This function initializes hardware setting.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void HardwareSetup(void)
{
R_Systeminit();
}
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_icu.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for ICU module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_icu.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: R_ICU_Create
* Description : This function initializes ICU module.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_ICU_Create(void)
{
/* Disable IRQ interrupts */
ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE |
_00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE;
ICU.IER[0x09].BYTE = _00_ICU_IRQ8_DISABLE | _00_ICU_IRQ9_DISABLE | _00_ICU_IRQ10_DISABLE | _00_ICU_IRQ11_DISABLE |
_00_ICU_IRQ12_DISABLE | _00_ICU_IRQ13_DISABLE | _00_ICU_IRQ14_DISABLE | _00_ICU_IRQ15_DISABLE;
/* Disable group interrupts */
IEN(ICU,GROUPBL0) = 0U;
/* Set IRQ settings */
ICU.IRQCR[2].BYTE = _04_ICU_IRQ_EDGE_FALLING;
ICU.IRQCR[5].BYTE = _04_ICU_IRQ_EDGE_FALLING;
/* Set IRQ2 priority level */
IPR(ICU,IRQ2) = _0F_ICU_PRIORITY_LEVEL15;
/* Set IRQ5 priority level */
IPR(ICU,IRQ5) = _0F_ICU_PRIORITY_LEVEL15;
/* Set Group BL0 priority level */
IPR(ICU,GROUPBL0) = _0F_ICU_PRIORITY_LEVEL15;
/* Enable group BL0 interrupt */
IEN(ICU,GROUPBL0) = 1U;
/* Set IRQ2 pin */
MPC.P12PFS.BYTE = 0x40U;
PORT1.PDR.BYTE &= 0xFBU;
PORT1.PMR.BYTE &= 0xFBU;
/* Set IRQ5 pin */
MPC.P15PFS.BYTE = 0x40U;
PORT1.PDR.BYTE &= 0xDFU;
PORT1.PMR.BYTE &= 0xDFU;
}
/***********************************************************************************************************************
* Function Name: R_ICU_IRQ2_Start
* Description : This function enables IRQ2 interrupt.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_ICU_IRQ2_Start(void)
{
/* Enable IRQ2 interrupt */
IEN(ICU,IRQ2) = 1U;
}
/***********************************************************************************************************************
* Function Name: R_ICU_IRQ2_Stop
* Description : This function disables IRQ2 interrupt.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_ICU_IRQ2_Stop(void)
{
/* Disable IRQ2 interrupt */
IEN(ICU,IRQ2) = 0U;
}
/***********************************************************************************************************************
* Function Name: R_ICU_IRQ5_Start
* Description : This function enables IRQ5 interrupt.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_ICU_IRQ5_Start(void)
{
/* Enable IRQ5 interrupt */
IEN(ICU,IRQ5) = 1U;
}
/***********************************************************************************************************************
* Function Name: R_ICU_IRQ5_Stop
* Description : This function disables IRQ5 interrupt.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_ICU_IRQ5_Stop(void)
{
/* Disable IRQ5 interrupt */
IEN(ICU,IRQ5) = 0U;
}
/* Start user code for adding. Do not edit comment generated here */
/*******************************************************************************
* Function Name: R_ICU_IRQIsFallingEdge
* Description : This function returns 1 if the specified ICU_IRQ is set to
* falling edge triggered, otherwise 0.
* Arguments : uint8_t irq_no
* Return Value : 1 if falling edge triggered, 0 if not
*******************************************************************************/
uint8_t R_ICU_IRQIsFallingEdge (const uint8_t irq_no)
{
uint8_t falling_edge_trig = 0x0;
if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING)
{
falling_edge_trig = 1;
}
return falling_edge_trig;
}
/*******************************************************************************
* End of function R_ICU_IRQIsFallingEdge
*******************************************************************************/
/*******************************************************************************
* Function Name: R_ICU_IRQSetFallingEdge
* Description : This function sets/clears the falling edge trigger for the
* specified ICU_IRQ.
* Arguments : uint8_t irq_no
* uint8_t set_f_edge, 1 if setting falling edge triggered, 0 if
* clearing
* Return Value : None
*******************************************************************************/
void R_ICU_IRQSetFallingEdge (const uint8_t irq_no, const uint8_t set_f_edge)
{
if (1 == set_f_edge)
{
ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING;
}
else
{
ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING;
}
}
/******************************************************************************
* End of function R_ICU_IRQSetFallingEdge
*******************************************************************************/
/*******************************************************************************
* Function Name: R_ICU_IRQSetRisingEdge
* Description : This function sets/clear the rising edge trigger for the
* specified ICU_IRQ.
* Arguments : uint8_t irq_no
* uint8_t set_r_edge, 1 if setting rising edge triggered, 0 if
* clearing
* Return Value : None
*******************************************************************************/
void R_ICU_IRQSetRisingEdge (const uint8_t irq_no, const uint8_t set_r_edge)
{
if (1 == set_r_edge)
{
ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING;
}
else
{
ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING;
}
}
/******************************************************************************
* End of function R_ICU_IRQSetRisingEdge
*******************************************************************************/
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_icu.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for ICU module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef ICU_H
#define ICU_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
Interrupt Request Enable Register 08 (IER08)
*/
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_ICU_IRQ0_DISABLE (0x00U) /* IRQ0 interrupt request is disabled */
#define _01_ICU_IRQ0_ENABLE (0x01U) /* IRQ0 interrupt request is enabled */
#define _00_ICU_IRQ1_DISABLE (0x00U) /* IRQ1 interrupt request is disabled */
#define _02_ICU_IRQ1_ENABLE (0x02U) /* IRQ1 interrupt request is enabled */
#define _00_ICU_IRQ2_DISABLE (0x00U) /* IRQ2 interrupt request is disabled */
#define _04_ICU_IRQ2_ENABLE (0x04U) /* IRQ2 interrupt request is enabled */
#define _00_ICU_IRQ3_DISABLE (0x00U) /* IRQ3 interrupt request is disabled */
#define _08_ICU_IRQ3_ENABLE (0x08U) /* IRQ3 interrupt request is enabled */
#define _00_ICU_IRQ4_DISABLE (0x00U) /* IRQ4 interrupt request is disabled */
#define _10_ICU_IRQ4_ENABLE (0x10U) /* IRQ4 interrupt request is enabled */
#define _00_ICU_IRQ5_DISABLE (0x00U) /* IRQ5 interrupt request is disabled */
#define _20_ICU_IRQ5_ENABLE (0x20U) /* IRQ5 interrupt request is enabled */
#define _00_ICU_IRQ6_DISABLE (0x00U) /* IRQ6 interrupt request is disabled */
#define _40_ICU_IRQ6_ENABLE (0x40U) /* IRQ6 interrupt request is enabled */
#define _00_ICU_IRQ7_DISABLE (0x00U) /* IRQ7 interrupt request is disabled */
#define _80_ICU_IRQ7_ENABLE (0x80U) /* IRQ7 interrupt request is enabled */
/*
Interrupt Request Enable Register 09 (IER09)
*/
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_ICU_IRQ8_DISABLE (0x00U) /* IRQ8 interrupt request is disabled */
#define _01_ICU_IRQ8_ENABLE (0x01U) /* IRQ8 interrupt request is enabled */
#define _00_ICU_IRQ9_DISABLE (0x00U) /* IRQ9 interrupt request is disabled */
#define _02_ICU_IRQ9_ENABLE (0x02U) /* IRQ9 interrupt request is enabled */
#define _00_ICU_IRQ10_DISABLE (0x00U) /* IRQ10 interrupt request is disabled */
#define _04_ICU_IRQ10_ENABLE (0x04U) /* IRQ10 interrupt request is enabled */
#define _00_ICU_IRQ11_DISABLE (0x00U) /* IRQ11 interrupt request is disabled */
#define _08_ICU_IRQ11_ENABLE (0x08U) /* IRQ11 interrupt request is enabled */
#define _00_ICU_IRQ12_DISABLE (0x00U) /* IRQ12 interrupt request is disabled */
#define _10_ICU_IRQ12_ENABLE (0x10U) /* IRQ12 interrupt request is enabled */
#define _00_ICU_IRQ13_DISABLE (0x00U) /* IRQ13 interrupt request is disabled */
#define _20_ICU_IRQ13_ENABLE (0x20U) /* IRQ13 interrupt request is enabled */
#define _00_ICU_IRQ14_DISABLE (0x00U) /* IRQ14 interrupt request is disabled */
#define _40_ICU_IRQ14_ENABLE (0x40U) /* IRQ14 interrupt request is enabled */
#define _00_ICU_IRQ15_DISABLE (0x00U) /* IRQ15 interrupt request is disabled */
#define _80_ICU_IRQ15_ENABLE (0x80U) /* IRQ15 interrupt request is enabled */
/*
Interrupt Source Priority Register n (IPRn)
*/
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */
#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */
#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */
#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */
#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */
#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */
#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */
/*
Fast Interrupt Set Register (FIR)
*/
/* Fast Interrupt Enable (FIEN) */
#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000U) /* Fast interrupt is disabled */
#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000U) /* Fast interrupt is enabled */
/*
IRQ Control Register i (IRQCRi) (i = 0 to 7)
*/
/* IRQ Detection Sense Select (IRQMD[1:0]) */
#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */
#define _04_ICU_IRQ_EDGE_FALLING (0x04U) /* Falling edge */
#define _08_ICU_IRQ_EDGE_RISING (0x08U) /* Rising edge */
#define _0C_ICU_IRQ_EDGE_BOTH (0x0CU) /* Rising and falling edge */
/*
IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)
*/
/* Digital Filter Enable (FLTEN0n) */
#define _00_ICU_IRQn_FILTER_DISABLE (0x00U) /* IRQn digital filter is disabled */
#define _01_ICU_IRQ0_FILTER_ENABLE (0x01U) /* IRQ0 digital filter is enabled */
#define _02_ICU_IRQ1_FILTER_ENABLE (0x02U) /* IRQ1 digital filter is enabled */
#define _04_ICU_IRQ2_FILTER_ENABLE (0x04U) /* IRQ2 digital filter is enabled */
#define _08_ICU_IRQ3_FILTER_ENABLE (0x08U) /* IRQ3 digital filter is enabled */
#define _10_ICU_IRQ4_FILTER_ENABLE (0x10U) /* IRQ4 digital filter is enabled */
#define _20_ICU_IRQ5_FILTER_ENABLE (0x20U) /* IRQ5 digital filter is enabled */
#define _40_ICU_IRQ6_FILTER_ENABLE (0x40U) /* IRQ6 digital filter is enabled */
#define _80_ICU_IRQ7_FILTER_ENABLE (0x80U) /* IRQ7 digital filter is enabled */
/*
IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1)
*/
/* Digital Filter Enable (FLTEN8~15) */
#define _01_ICU_IRQ8_FILTER_ENABLE (0x01U) /* IRQ8 digital filter is enabled */
#define _02_ICU_IRQ9_FILTER_ENABLE (0x02U) /* IRQ9 digital filter is enabled */
#define _04_ICU_IRQ10_FILTER_ENABLE (0x04U) /* IRQ10 digital filter is enabled */
#define _08_ICU_IRQ11_FILTER_ENABLE (0x08U) /* IRQ11 digital filter is enabled */
#define _10_ICU_IRQ12_FILTER_ENABLE (0x10U) /* IRQ12 digital filter is enabled */
#define _20_ICU_IRQ13_FILTER_ENABLE (0x20U) /* IRQ13 digital filter is enabled */
#define _40_ICU_IRQ14_FILTER_ENABLE (0x40U) /* IRQ14 digital filter is enabled */
#define _80_ICU_IRQ15_FILTER_ENABLE (0x80U) /* IRQ15 digital filter is enabled */
/*
IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)
*/
/* IRQn Digital Filter Sampling Clock (FCLKSELn) */
#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000U) /* IRQ0 sample clock is run at every PCLK cycle */
#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001U) /* IRQ0 sample clock is run at every PCLK/8 cycle */
#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002U) /* IRQ0 sample clock is run at every PCLK/32 cycle */
#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003U) /* IRQ0 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000U) /* IRQ1 sample clock is run at every PCLK cycle */
#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004U) /* IRQ1 sample clock is run at every PCLK/8 cycle */
#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008U) /* IRQ1 sample clock is run at every PCLK/32 cycle */
#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000CU) /* IRQ1 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000U) /* IRQ2 sample clock is run at every PCLK cycle */
#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010U) /* IRQ2 sample clock is run at every PCLK/8 cycle */
#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020U) /* IRQ2 sample clock is run at every PCLK/32 cycle */
#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030U) /* IRQ2 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000U) /* IRQ3 sample clock is run at every PCLK cycle */
#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040U) /* IRQ3 sample clock is run at every PCLK/8 cycle */
#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080U) /* IRQ3 sample clock is run at every PCLK/32 cycle */
#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00C0U) /* IRQ3 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000U) /* IRQ4 sample clock is run at every PCLK cycle */
#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100U) /* IRQ4 sample clock is run at every PCLK/8 cycle */
#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200U) /* IRQ4 sample clock is run at every PCLK/32 cycle */
#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300U) /* IRQ4 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000U) /* IRQ5 sample clock is run at every PCLK cycle */
#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400U) /* IRQ5 sample clock is run at every PCLK/8 cycle */
#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800U) /* IRQ5 sample clock is run at every PCLK/32 cycle */
#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0C00U) /* IRQ5 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000U) /* IRQ6 sample clock is run at every PCLK cycle */
#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000U) /* IRQ6 sample clock is run at every PCLK/8 cycle */
#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000U) /* IRQ6 sample clock is run at every PCLK/32 cycle */
#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000U) /* IRQ6 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000U) /* IRQ7 sample clock is run at every PCLK cycle */
#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000U) /* IRQ7 sample clock is run at every PCLK/8 cycle */
#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000U) /* IRQ7 sample clock is run at every PCLK/32 cycle */
#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xC000U) /* IRQ7 sample clock is run at every PCLK/64 cycle */
/*
IRQ Pin Digital Filter Setting Register 0 (IRQFLTC1)
*/
/* IRQn Digital Filter Sampling Clock (FCLKSEL8~15) */
#define _0000_ICU_IRQ8_FILTER_PCLK (0x0000U) /* IRQ8 sample clock is run at every PCLK cycle */
#define _0001_ICU_IRQ8_FILTER_PCLK_8 (0x0001U) /* IRQ8 sample clock is run at every PCLK/8 cycle */
#define _0002_ICU_IRQ8_FILTER_PCLK_32 (0x0002U) /* IRQ8 sample clock is run at every PCLK/32 cycle */
#define _0003_ICU_IRQ8_FILTER_PCLK_64 (0x0003U) /* IRQ8 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ9_FILTER_PCLK (0x0000U) /* IRQ9 sample clock is run at every PCLK cycle */
#define _0004_ICU_IRQ9_FILTER_PCLK_8 (0x0004U) /* IRQ9 sample clock is run at every PCLK/8 cycle */
#define _0008_ICU_IRQ9_FILTER_PCLK_32 (0x0008U) /* IRQ9 sample clock is run at every PCLK/32 cycle */
#define _000C_ICU_IRQ9_FILTER_PCLK_64 (0x000CU) /* IRQ9 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ10_FILTER_PCLK (0x0000U) /* IRQ10 sample clock is run at every PCLK cycle */
#define _0010_ICU_IRQ10_FILTER_PCLK_8 (0x0010U) /* IRQ10 sample clock is run at every PCLK/8 cycle */
#define _0020_ICU_IRQ10_FILTER_PCLK_32 (0x0020U) /* IRQ10 sample clock is run at every PCLK/32 cycle */
#define _0030_ICU_IRQ10_FILTER_PCLK_64 (0x0030U) /* IRQ10 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ11_FILTER_PCLK (0x0000U) /* IRQ11 sample clock is run at every PCLK cycle */
#define _0040_ICU_IRQ11_FILTER_PCLK_8 (0x0040U) /* IRQ11 sample clock is run at every PCLK/8 cycle */
#define _0080_ICU_IRQ11_FILTER_PCLK_32 (0x0080U) /* IRQ11 sample clock is run at every PCLK/32 cycle */
#define _00C0_ICU_IRQ11_FILTER_PCLK_64 (0x00C0U) /* IRQ11 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ12_FILTER_PCLK (0x0000U) /* IRQ12 sample clock is run at every PCLK cycle */
#define _0100_ICU_IRQ12_FILTER_PCLK_8 (0x0100U) /* IRQ12 sample clock is run at every PCLK/8 cycle */
#define _0200_ICU_IRQ12_FILTER_PCLK_32 (0x0200U) /* IRQ12 sample clock is run at every PCLK/32 cycle */
#define _0300_ICU_IRQ12_FILTER_PCLK_64 (0x0300U) /* IRQ12 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ13_FILTER_PCLK (0x0000U) /* IRQ13 sample clock is run at every PCLK cycle */
#define _0400_ICU_IRQ13_FILTER_PCLK_8 (0x0400U) /* IRQ13 sample clock is run at every PCLK/8 cycle */
#define _0800_ICU_IRQ13_FILTER_PCLK_32 (0x0800U) /* IRQ13 sample clock is run at every PCLK/32 cycle */
#define _0C00_ICU_IRQ13_FILTER_PCLK_64 (0x0C00U) /* IRQ13 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ14_FILTER_PCLK (0x0000U) /* IRQ14 sample clock is run at every PCLK cycle */
#define _1000_ICU_IRQ14_FILTER_PCLK_8 (0x1000U) /* IRQ14 sample clock is run at every PCLK/8 cycle */
#define _2000_ICU_IRQ14_FILTER_PCLK_32 (0x2000U) /* IRQ14 sample clock is run at every PCLK/32 cycle */
#define _3000_ICU_IRQ14_FILTER_PCLK_64 (0x3000U) /* IRQ14 sample clock is run at every PCLK/64 cycle */
#define _0000_ICU_IRQ15_FILTER_PCLK (0x0000U) /* IRQ15 sample clock is run at every PCLK cycle */
#define _4000_ICU_IRQ15_FILTER_PCLK_8 (0x4000U) /* IRQ15 sample clock is run at every PCLK/8 cycle */
#define _8000_ICU_IRQ15_FILTER_PCLK_32 (0x8000U) /* IRQ15 sample clock is run at every PCLK/32 cycle */
#define _C000_ICU_IRQ15_FILTER_PCLK_64 (0xC000U) /* IRQ15 sample clock is run at every PCLK/64 cycle */
/*
NMI Pin Interrupt Control Register (NMICR)
*/
/* NMI Digital Filter Sampling Clock (NMIMD) */
#define _00_ICU_NMI_EDGE_FALLING (0x00U) /* Falling edge */
#define _08_ICU_NMI_EDGE_RISING (0x08U) /* Rising edge */
/*
NMI Pin Digital Filter Setting Register (NMIFLTC)
*/
/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */
#define _00_ICU_NMI_FILTER_PCLK (0x00U) /* NMI sample clock is run at every PCLK cycle */
#define _01_ICU_NMI_FILTER_PCLK_8 (0x01U) /* NMI sample clock is run at every PCLK/8 cycle */
#define _02_ICU_NMI_FILTER_PCLK_32 (0x02U) /* NMI sample clock is run at every PCLK/32 cycle */
#define _03_ICU_NMI_FILTER_PCLK_64 (0x03U) /* NMI sample clock is run at every PCLK/64 cycle */
/*
EXDMAC Activation Peripheral Interrupt Select Register (SELEXDR)
*/
/* EXDMAC0 Activation Peripheral Interrupt Select (SELEXD0) */
#define _00_ICU_EXDMAC0_SLIBR144 (0x00U) /* Interrupt B selected in SLIBR144 activates EXDMAC0 */
#define _01_ICU_EXDMAC0_SLIAR208 (0x01U) /* Interrupt B selected in SLIAR208 activates EXDMAC0 */
/* EXDMAC1 Activation Peripheral Interrupt Select (SELEXD1) */
#define _00_ICU_EXDMAC1_SLIBR145 (0x00U) /* Interrupt B selected in SLIBR145 activates EXDMAC1 */
#define _02_ICU_EXDMAC1_SLIAR209 (0x02U) /* Interrupt B selected in SLIAR209 activates EXDMAC1 */
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_ICU_Create(void);
void R_ICU_IRQ2_Start(void);
void R_ICU_IRQ2_Stop(void);
void R_ICU_IRQ5_Start(void);
void R_ICU_IRQ5_Stop(void);
/* Start user code for function. Do not edit comment generated here */
/* Function prototypes for detecting and setting the edge trigger of ICU_IRQ */
uint8_t R_ICU_IRQIsFallingEdge(const uint8_t irq_no);
void R_ICU_IRQSetFallingEdge(const uint8_t irq_no, const uint8_t set_f_edge);
void R_ICU_IRQSetRisingEdge(const uint8_t irq_no, const uint8_t set_r_edge);
/* End user code. Do not edit comment generated here */
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_icu_user.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for ICU module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_icu.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: r_icu_irq2_interrupt
* Description : This function is IRQ2 interrupt service routine.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
#if FAST_INTERRUPT_VECTOR == VECT_ICU_IRQ2
#pragma interrupt r_icu_irq2_interrupt(vect=VECT(ICU,IRQ2),fint)
#else
#pragma interrupt r_icu_irq2_interrupt(vect=VECT(ICU,IRQ2))
#endif
static void r_icu_irq2_interrupt(void)
{
/* Start user code. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
}
/***********************************************************************************************************************
* Function Name: r_icu_irq5_interrupt
* Description : This function is IRQ5 interrupt service routine.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
#if FAST_INTERRUPT_VECTOR == VECT_ICU_IRQ5
#pragma interrupt r_icu_irq5_interrupt(vect=VECT(ICU,IRQ5),fint)
#else
#pragma interrupt r_icu_irq5_interrupt(vect=VECT(ICU,IRQ5))
#endif
static void r_icu_irq5_interrupt(void)
{
/* Start user code. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
}
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_macrodriver.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements general head file.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef MODULEID_H
#define MODULEID_H
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "../iodefine.h"
//_RB_#include <machine.h>
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
#ifndef __TYPEDEF__
/* Status list definition */
#define MD_STATUSBASE (0x00U)
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
/* Error list definition */
#define MD_ERRORBASE (0x80U)
#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */
#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
#endif
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
#ifndef __TYPEDEF__
#ifndef _STD_USING_INT_TYPES
#define _SYS_INT_TYPES_H
#ifndef _STD_USING_BIT_TYPES
#ifndef __int8_t_defined
#define __int8_t_defined
typedef signed char int8_t;
typedef signed short int16_t;
#endif
#endif
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef signed long int32_t;
typedef unsigned long uint32_t;
typedef signed char int_least8_t;
typedef signed short int_least16_t;
typedef signed long int_least32_t;
typedef unsigned char uint_least8_t;
typedef unsigned short uint_least16_t;
typedef unsigned long uint_least32_t;
#endif
typedef unsigned short MD_STATUS;
#define __TYPEDEF__
#endif
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void HardwareSetup(void);
void R_Systeminit(void);
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_port.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for Port module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_port.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: R_PORT_Create
* Description : This function initializes the Port I/O.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_PORT_Create(void)
{
PORT0.PODR.BYTE = _08_Pm3_OUTPUT_1 | _20_Pm5_OUTPUT_1;
PORT2.PODR.BYTE = _02_Pm1_OUTPUT_1 | _40_Pm6_OUTPUT_1 | _80_Pm7_OUTPUT_1;
PORT4.PODR.BYTE = _20_Pm5_OUTPUT_1 | _40_Pm6_OUTPUT_1;
PORT0.DSCR.BYTE |= _08_Pm3_HIDRV_ON | _20_Pm5_HIDRV_ON;
PORT2.DSCR.BYTE |= _02_Pm1_HIDRV_ON | _40_Pm6_HIDRV_ON | _80_Pm7_HIDRV_ON;
PORT0.PDR.BYTE = _08_Pm3_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT;
PORT2.PDR.BYTE = _02_Pm1_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT;
PORT4.PDR.BYTE = _20_Pm5_MODE_OUTPUT | _40_Pm6_MODE_OUTPUT | _80_Pm7_MODE_OUTPUT;
}
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_port.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for Port module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef PORT_H
#define PORT_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
Port Direction Register (PDR)
*/
/* Pmn Direction Control (B7 - B0) */
#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */
#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */
#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */
#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */
#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */
#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */
#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */
#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */
#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */
#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */
#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */
#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */
#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */
#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */
#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */
#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */
#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */
#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */
#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */
#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */
#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */
#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */
#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */
#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */
/*
Port Output Data Register (PODR)
*/
/* Pmn Output Data Store (B7 - B0) */
#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */
#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */
#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */
#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */
#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */
#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */
#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */
#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */
#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */
#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */
#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */
#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */
#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */
#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */
#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */
#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */
/*
Open Drain Control Register 0 (ODR0)
*/
/* Pmn Output Type Select (Pm0 to Pm3) */
#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* NMOS open-drain output */
#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* NMOS open-drain output */
#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* PMOS open-drain output, for PE1 only*/
#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* NMOS open-drain output */
#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* NMOS open-drain output */
/*
Open Drain Control Register 1 (ODR1)
*/
/* Pmn Output Type Select (Pm4 to Pm7) */
#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* NMOS open-drain output */
#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* NMOS open-drain output */
#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* NMOS open-drain output */
#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */
#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* NMOS open-drain output */
/*
Pull-Up Control Register (PCR)
*/
/* Pmn Input Pull-Up Resistor Control (B7 - B0) */
#define _00_Pm0_PULLUP_OFF (0x00U) /* Pm0 pull-up resistor not connected */
#define _01_Pm0_PULLUP_ON (0x01U) /* Pm0 pull-up resistor connected */
#define _00_Pm1_PULLUP_OFF (0x00U) /* Pm1 pull-up resistor not connected */
#define _02_Pm1_PULLUP_ON (0x02U) /* Pm1 pull-up resistor connected */
#define _00_Pm2_PULLUP_OFF (0x00U) /* Pm2 Pull-up resistor not connected */
#define _04_Pm2_PULLUP_ON (0x04U) /* Pm2 pull-up resistor connected */
#define _00_Pm3_PULLUP_OFF (0x00U) /* Pm3 pull-up resistor not connected */
#define _08_Pm3_PULLUP_ON (0x08U) /* Pm3 pull-up resistor connected */
#define _00_Pm4_PULLUP_OFF (0x00U) /* Pm4 pull-up resistor not connected */
#define _10_Pm4_PULLUP_ON (0x10U) /* Pm4 pull-up resistor connected */
#define _00_Pm5_PULLUP_OFF (0x00U) /* Pm5 pull-up resistor not connected */
#define _20_Pm5_PULLUP_ON (0x20U) /* Pm5 pull-up resistor connected */
#define _00_Pm6_PULLUP_OFF (0x00U) /* Pm6 pull-up resistor not connected */
#define _40_Pm6_PULLUP_ON (0x40U) /* Pm6 pull-up resistor connected */
#define _00_Pm7_PULLUP_OFF (0x00U) /* Pm7 pull-up resistor not connected */
#define _80_Pm7_PULLUP_ON (0x80U) /* Pm7 pull-up resistor connected */
/*
Drive Capacity Control Register (DSCR)
*/
/* Pmn Drive Capacity Control (B7 - B0) */
#define _00_Pm0_HIDRV_OFF (0x00U) /* Pm0 Normal drive output */
#define _01_Pm0_HIDRV_ON (0x01U) /* Pm0 High-drive output */
#define _00_Pm1_HIDRV_OFF (0x00U) /* Pm1 Normal drive output */
#define _02_Pm1_HIDRV_ON (0x02U) /* Pm1 High-drive output */
#define _00_Pm2_HIDRV_OFF (0x00U) /* Pm2 Normal drive output */
#define _04_Pm2_HIDRV_ON (0x04U) /* Pm2 High-drive output */
#define _00_Pm3_HIDRV_OFF (0x00U) /* Pm3 Normal drive output */
#define _08_Pm3_HIDRV_ON (0x08U) /* Pm3 High-drive output */
#define _00_Pm4_HIDRV_OFF (0x00U) /* Pm4 Normal drive output */
#define _10_Pm4_HIDRV_ON (0x10U) /* Pm4 High-drive output */
#define _00_Pm5_HIDRV_OFF (0x00U) /* Pm5 Normal drive output */
#define _20_Pm5_HIDRV_ON (0x20U) /* Pm5 High-drive output */
#define _00_Pm6_HIDRV_OFF (0x00U) /* Pm6 Normal drive output */
#define _40_Pm6_HIDRV_ON (0x40U) /* Pm6 High-drive output */
#define _00_Pm7_HIDRV_OFF (0x00U) /* Pm7 Normal drive output */
#define _80_Pm7_HIDRV_ON (0x80U) /* Pm7 High-drive output */
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
#define _70_PDR5_DEFAULT (0x70U) /* PDR5 default value */
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_PORT_Create(void);
/* Start user code for function. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_port_user.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for Port module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_port.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_sbrk.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : Program of sbrk.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include <stddef.h>
#include <stdio.h>
#include "r_cg_sbrk.h"
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
int8_t *sbrk(size_t size);
extern int8_t *_s1ptr;
union HEAP_TYPE
{
int16_t dummy ; /* Dummy for 4-byte boundary */
int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */
};
static union HEAP_TYPE heap_area ;
/* End address allocated by sbrk */
static int8_t *brk = (int8_t *) &heap_area;
/**************************************************************************/
/* sbrk:Memory area allocation */
/* Return value:Start address of allocated area (Pass) */
/* -1 (Failure) */
/**************************************************************************/
int8_t *sbrk(size_t size) /* Assigned area size */
{
int8_t *p;
if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */
{
p = (int8_t *)-1;
}
else
{
p = brk; /* Area assignment */
brk += size; /* End address update */
}
return p;
}
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

48
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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_sbrk.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : Header file of sbrk file.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef _SBRK_H
#define _SBRK_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_sci.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for SCI module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_sci.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
uint8_t * gp_sci7_tx_address; /* SCI7 transmit buffer address */
uint16_t g_sci7_tx_count; /* SCI7 transmit data number */
uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */
uint16_t g_sci7_rx_count; /* SCI7 receive data number */
uint16_t g_sci7_rx_length; /* SCI7 receive data length */
/* Start user code for global. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: R_SCI7_Create
* Description : This function initializes SCI7.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_SCI7_Create(void)
{
/* Cancel SCI7 module stop state */
MSTP(SCI7) = 0U;
/* Set interrupt priority */
IPR(SCI7, RXI7) = _0F_SCI_PRIORITY_LEVEL15;
IPR(SCI7, TXI7) = _0F_SCI_PRIORITY_LEVEL15;
/* Clear the control register */
SCI7.SCR.BYTE = 0x00U;
/* Set clock enable */
SCI7.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;
/* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit, and set SPMR */
SCI7.SIMR1.BIT.IICM = 0U;
SCI7.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;
/* Set control registers */
SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE |
_00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;
SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST |
_10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT;
SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK |
_00_SCI_BAUDRATE_SINGLE | _00_SCI_BIT_MODULATION_DISABLE;
/* Set bitrate */
SCI7.BRR = 0xC2U;
/* Set RXD7 pin */
MPC.P92PFS.BYTE = 0x0AU;
PORT9.PMR.BYTE |= 0x04U;
/* Set TXD7 pin */
MPC.P90PFS.BYTE = 0x0AU;
PORT9.PODR.BYTE |= 0x01U;
PORT9.PDR.BYTE |= 0x01U;
PORT9.PMR.BYTE |= 0x01U;
}
/***********************************************************************************************************************
* Function Name: R_SCI7_Start
* Description : This function starts SCI7.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_SCI7_Start(void)
{
/* Clear interrupt flag */
IR(SCI7, TXI7) = 0U;
IR(SCI7, RXI7) = 0U;
/* Enable SCI interrupt */
IEN(SCI7, TXI7) = 1U;
ICU.GENBL0.BIT.EN14 = 1U;
IEN(SCI7, RXI7) = 1U;
ICU.GENBL0.BIT.EN15 = 1U;
}
/***********************************************************************************************************************
* Function Name: R_SCI7_Stop
* Description : This function stops SCI7.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_SCI7_Stop(void)
{
/* Set TXD7 pin */
PORT9.PMR.BYTE &= 0xFEU;
SCI7.SCR.BIT.TE = 0U; /* Disable serial transmit */
SCI7.SCR.BIT.RE = 0U; /* Disable serial receive */
/* Disable SCI interrupt */
SCI7.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */
SCI7.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */
IR(SCI7, TXI7) = 0U;
IEN(SCI7, TXI7) = 0U;
ICU.GENBL0.BIT.EN14 = 0U;
IR(SCI7, RXI7) = 0U;
IEN(SCI7, RXI7) = 0U;
ICU.GENBL0.BIT.EN15 = 0U;
}
/***********************************************************************************************************************
* Function Name: R_SCI7_Serial_Receive
* Description : This function receives SCI7 data.
* Arguments : rx_buf -
* receive buffer pointer (Not used when receive data handled by DTC or DMAC)
* rx_num -
* buffer size (Not used when receive data handled by DTC or DMAC)
* Return Value : status -
* MD_OK or MD_ARGERROR
***********************************************************************************************************************/
MD_STATUS R_SCI7_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num)
{
MD_STATUS status = MD_OK;
if (1U > rx_num)
{
status = MD_ARGERROR;
}
else
{
g_sci7_rx_count = 0U;
g_sci7_rx_length = rx_num;
gp_sci7_rx_address = rx_buf;
SCI7.SCR.BIT.RIE = 1U;
SCI7.SCR.BIT.RE = 1U;
}
return (status);
}
/***********************************************************************************************************************
* Function Name: R_SCI7_Serial_Send
* Description : This function transmits SCI7 data.
* Arguments : tx_buf -
* transfer buffer pointer (Not used when transmit data handled by DTC)
* tx_num -
* buffer size (Not used when transmit data handled by DTC or DMAC)
* Return Value : status -
* MD_OK or MD_ARGERROR
***********************************************************************************************************************/
MD_STATUS R_SCI7_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num)
{
MD_STATUS status = MD_OK;
if (1U > tx_num)
{
status = MD_ARGERROR;
}
else
{
gp_sci7_tx_address = tx_buf;
g_sci7_tx_count = tx_num;
/* Set TXD7 pin */
PORT9.PMR.BYTE |= 0x01U;
SCI7.SCR.BIT.TIE = 1U;
SCI7.SCR.BIT.TE = 1U;
}
return (status);
}
/* Start user code for adding. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_sci.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for SCI module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef SCI_H
#define SCI_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
Serial mode register (SMR)
*/
/* Clock select (CKS) */
#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */
#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */
#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */
#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */
/* Multi-processor Mode (MP) */
#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */
#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */
/* Stop bit length (STOP) */
#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */
#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */
/* Parity mode (PM) */
#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */
#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */
/* Parity enable (PE) */
#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */
#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */
/* Character length (CHR) */
#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */
#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */
/* Communications mode (CM) */
#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */
#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */
/* Base clock pulse (BCP) */
#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */
#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */
#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */
#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */
/* Block transfer mode (BLK) */
#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */
#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */
/* GSM mode (GSM) */
#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */
#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */
/*
Serial control register (SCR)
*/
/* Clock enable (CKE) */
#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */
#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */
#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */
#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */
/* Transmit end interrupt enable (TEIE) */
#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */
#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */
/* Multi-processor interrupt enable (MPIE) */
#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */
#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */
/* Receive enable (RE) */
#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */
#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */
/* Transmit enable (TE) */
#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */
#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */
/* Receive interrupt enable (RIE) */
#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */
#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */
/* Transmit interrupt enable (TIE) */
#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */
#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */
/* Clock enable (CKE) */
#define _00_SCI_SCK_OUTPUT_DISABLE (0x00U) /* SCK output is disabled */
#define _01_SCI_SCK_OUTPUT_ENABLE (0x01U) /* SCK output is enabled */
#define _00_SCI_SCK_OUTPUT_FIX_LOW (0x00U) /* GSM mode SCK fixed to low */
#define _02_SCI_SCK_OUTPUT_FIX_HIGH (0x02U) /* GSM mode SCK fixed to high */
/*
Serial status register (SSR)
*/
/* Multi-Processor bit transfer */
#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */
#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */
/* Multi-Processor */
#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */
#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */
/* Transmit end flag (TEND) */
#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */
#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */
/* Parity error flag (PER) */
#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */
/* Framing error flag (FER) */
#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */
/* Error signal status flag (ERS) */
#define _10_SCI_LOW_ERROR_DETECTED (0x10U) /* A low error signal responded */
/* Overrun error flag (ORER) */
#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */
/* Receive Data Full Flag (RDRF) */
#define _40_SCI_RECEIVE_DATAFULL (0x40U) /* Data has been received normally, and transferred from
RSR to RDR */
/* Transmit Data Empty Flag (TDRE) */
#define _80_SCI_TRANSMIT_DATAEMPTY (0x80U) /* Data is transferred from TDR to TSR */
/*
Smart card mode register (SCMR)
*/
/* Smart card interface mode select (SMIF) */
#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */
#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */
/* Transmitted / received data invert (SINV) */
#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */
#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */
/* Transmitted / received data transfer direction (SDIR) */
#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */
#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */
/* Character length 1 */
#define _00_SCI_DATA_LENGTH_9 (0x00U) /* Transmit/receive in 9-bit data length */
#define _10_SCI_DATA_LENGTH_8_OR_7 (0x10U) /* Transmit/receive in 8-bit or 7-bit data length */
/* Base clock pulse 2 (BCP2) */
#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */
#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */
#define _62_SCI_SCMR_DEFAULT (0x62U) /* Write default value of SCMR */
/*
Serial extended mode register (SEMR)
*/
/* Asynchronous Mode Clock Source Select (ACS0) */
#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */
#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */
/* Bit Modulation Enable (BRME) */
#define _00_SCI_BIT_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */
#define _04_SCI_BIT_MODULATION_ENABLE (0x04U) /* Bit rate modulation function is enabled */
/* Asynchronous mode base clock select (ABCS) */
#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */
#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */
/* Digital noise filter function enable (NFEN) */
#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */
#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */
/* Baud Rate Generator Double-Speed Mode Select (BGDM) */
#define _00_SCI_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */
#define _40_SCI_BAUDRATE_DOUBLE (0x40U) /* Baud rate generator doubles output frequency */
/* Asynchronous start bit edge detections select (RXDESEL) */
#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */
#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */
/*
Noise filter setting register (SNFR)
*/
/* Noise filter clock select (NFCS) */
#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */
#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */
#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */
#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */
#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */
/*
I2C mode register 1 (SIMR1)
*/
/* Simple IIC mode select (IICM) */
#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */
#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */
/*
I2C mode register 2 (SIMR2)
*/
/* IIC interrupt mode select (IICINTM) */
#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */
#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */
/* Clock synchronization (IICCSC) */
#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */
#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */
/* ACK transmission data (IICACKT) */
#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */
#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */
/*
I2C mode register 3 (SIMR3)
*/
/* Start condition generation (IICSTAREQ) */
#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */
#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */
/* Restart condition generation (IICRSTAREQ) */
#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */
#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */
/* Stop condition generation (IICSTPREQ) */
#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */
#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */
/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */
#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */
#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */
/* SSDA output select (IICSDAS) */
#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */
#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */
#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */
#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */
/* SSCL output select (IICSCLS) */
#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */
#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */
#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */
#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */
/*
I2C status register (SISR)
*/
/* ACK reception data flag (IICACKR) */
#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */
#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */
/*
SPI mode register (SPMR)
*/
/* SS pin function enable (SSE) */
#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */
#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */
/* CTS enable (CTSE) */
#define _00_SCI_RTS (0x00U) /* RTS function is enabled */
#define _02_SCI_CTS (0x02U) /* CTS function is disabled */
/* Master slave select (MSS) */
#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */
#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */
/* Mode fault flag (MFF) */
#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */
#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */
/* Clock polarity select (CKPOL) */
#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */
#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */
/* Clock phase select (CKPH) */
#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */
#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */
/*
Interrupt Source Priority Register n (IPRn)
*/
/* Interrupt Priority Level Select (IPR[3:0]) */
#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */
#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */
#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */
#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */
#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */
#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */
#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */
/*
Transfer status control value
*/
/* Simple IIC Transmit Receive Flag */
#define _80_SCI_IIC_TRANSMISSION (0x80U)
#define _00_SCI_IIC_RECEPTION (0x00U)
/* Simple IIC Start Stop Flag */
#define _80_SCI_IIC_START_CYCLE (0x80U)
#define _00_SCI_IIC_STOP_CYCLE (0x00U)
/* Multiprocessor Asynchronous Communication Flag */
#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U)
#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U)
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_SCI7_Create(void);
void R_SCI7_Start(void);
void R_SCI7_Stop(void);
MD_STATUS R_SCI7_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);
MD_STATUS R_SCI7_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);
static void r_sci7_callback_transmitend(void);
static void r_sci7_callback_receiveend(void);
static void r_sci7_callback_receiveerror(void);
/* Start user code for function. Do not edit comment generated here */
/* Exported functions used to transmit a number of bytes and wait for completion */
MD_STATUS R_SCI6_SPIMasterTransmit(uint8_t * const tx_buf, const uint16_t tx_num);
MD_STATUS R_SCI7_AsyncTransmit(uint8_t * const tx_buf, const uint16_t tx_num);
/* Character is used to receive key presses from PC terminal */
extern uint8_t g_rx_char;
/* Flag used to control transmission to PC terminal */
extern volatile uint8_t g_tx_flag;
/* End user code. Do not edit comment generated here */
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_sci_user.c
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file implements device driver for SCI module.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/* Start user code for pragma. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_sci.h"
/* Start user code for include. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
extern uint8_t * gp_sci7_tx_address; /* SCI7 send buffer address */
extern uint16_t g_sci7_tx_count; /* SCI7 send data number */
extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */
extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */
extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */
/* Start user code for global. Do not edit comment generated here */
/* Flag used locally to detect transmission complete */
/* Global used to receive a character from the PC terminal */
uint8_t g_rx_char;
/* Flag used to control transmission to PC terminal */
volatile uint8_t g_tx_flag = FALSE;
/* Flag used locally to detect transmission complete */
static volatile uint8_t sci6_txdone;
static volatile uint8_t sci7_txdone;
/* End user code. Do not edit comment generated here */
/***********************************************************************************************************************
* Function Name: r_sci7_transmit_interrupt
* Description : None
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
#if FAST_INTERRUPT_VECTOR == VECT_SCI7_TXI7
#pragma interrupt r_sci7_transmit_interrupt(vect=VECT(SCI7,TXI7),fint)
#else
#pragma interrupt r_sci7_transmit_interrupt(vect=VECT(SCI7,TXI7))
#endif
static void r_sci7_transmit_interrupt(void)
{
if (0U < g_sci7_tx_count)
{
SCI7.TDR = *gp_sci7_tx_address;
gp_sci7_tx_address++;
g_sci7_tx_count--;
}
else
{
SCI7.SCR.BIT.TIE = 0U;
SCI7.SCR.BIT.TEIE = 1U;
}
}
/***********************************************************************************************************************
* Function Name: r_sci7_transmitend_interrupt
* Description : This function is TEI7 interrupt service routine.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void r_sci7_transmitend_interrupt(void)
{
/* Set TXD7 pin */
PORT9.PMR.BYTE &= 0xFEU;
SCI7.SCR.BIT.TIE = 0U;
SCI7.SCR.BIT.TE = 0U;
SCI7.SCR.BIT.TEIE = 0U;
r_sci7_callback_transmitend();
}
/***********************************************************************************************************************
* Function Name: r_sci7_receive_interrupt
* Description : None
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
#if FAST_INTERRUPT_VECTOR == VECT_SCI7_RXI7
#pragma interrupt r_sci7_receive_interrupt(vect=VECT(SCI7,RXI7),fint)
#else
#pragma interrupt r_sci7_receive_interrupt(vect=VECT(SCI7,RXI7))
#endif
static void r_sci7_receive_interrupt(void)
{
if (g_sci7_rx_length > g_sci7_rx_count)
{
*gp_sci7_rx_address = SCI7.RDR;
gp_sci7_rx_address++;
g_sci7_rx_count++;
if (g_sci7_rx_length <= g_sci7_rx_count)
{
r_sci7_callback_receiveend();
}
}
}
/***********************************************************************************************************************
* Function Name: r_sci7_receiveerror_interrupt
* Description : This function is ERI7 interrupt service routine.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void r_sci7_receiveerror_interrupt(void)
{
uint8_t err_type;
r_sci7_callback_receiveerror();
/* Clear overrun, framing and parity error flags */
err_type = SCI7.SSR.BYTE;
err_type &= 0xC7U;
err_type |= 0xC0U;
SCI7.SSR.BYTE = err_type;
}
/***********************************************************************************************************************
* Function Name: r_sci7_callback_transmitend
* Description : This function is a callback function when SCI7 finishes transmission.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
static void r_sci7_callback_transmitend(void)
{
/* Start user code. Do not edit comment generated here */
sci7_txdone = TRUE;
/* End user code. Do not edit comment generated here */
}
/***********************************************************************************************************************
* Function Name: r_sci7_callback_receiveend
* Description : This function is a callback function when SCI7 finishes reception.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
static void r_sci7_callback_receiveend(void)
{
/* Start user code. Do not edit comment generated here */
/* Check the contents of g_rx_char */
if (('c' == g_rx_char) || ('C' == g_rx_char))
{
//_RB_ g_adc_trigger = TRUE;
}
/* Set up SCI7 receive buffer and callback function again */
R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1);
/* End user code. Do not edit comment generated here */
}
/***********************************************************************************************************************
* Function Name: r_sci7_callback_receiveerror
* Description : This function is a callback function when SCI7 reception encounters error.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
static void r_sci7_callback_receiveerror(void)
{
/* Start user code. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
}
/* Start user code for adding. Do not edit comment generated here */
/*******************************************************************************
* Function Name: R_SCI7_AsyncTransmit
* Description : This function sends SCI7 data and waits for the transmit end flag.
* Arguments : tx_buf -
* transfer buffer pointer
* tx_num -
* buffer size
* Return Value : status -
* MD_OK or MD_ARGERROR
*******************************************************************************/
MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)
{
MD_STATUS status = MD_OK;
/* clear the flag before initiating a new transmission */
sci7_txdone = FALSE;
/* Send the data using the API */
status = R_SCI7_Serial_Send(tx_buf, tx_num);
/* Wait for the transmit end flag */
while (FALSE == sci7_txdone)
{
/* Wait */
}
return (status);
}
/*******************************************************************************
* End of function R_SCI7_AsyncTransmit
*******************************************************************************/
/* End user code. Do not edit comment generated here */

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_stacksct.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : Setting of Stack area.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef _STACKSCT_H
#define _STACKSCT_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
#pragma stacksize su = 0x100
#pragma stacksize si = 0x300
#endif

49
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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_userdefine.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file includes user definition.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef _USER_DEF_H
#define _USER_DEF_H
/***********************************************************************************************************************
User definitions
***********************************************************************************************************************/
#define FAST_INTERRUPT_VECTOR 0
/* Start user code for function. Do not edit comment generated here */
#define TRUE (1)
#define FALSE (0)
extern volatile uint8_t g_adc_trigger;
/* used to stop warnings being generated in r_cg_intprg.c */
extern void r_sci6_transmitend_interrupt(void);
extern void r_sci7_transmitend_interrupt(void);
extern void r_sci7_receiveerror_interrupt(void);
extern void r_s12ad0_compare_interrupt(void);
/* End user code. Do not edit comment generated here */
#endif

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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : r_cg_vect.h
* Version : Code Generator for RX71M V1.00.02.02 [28 May 2015]
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* Description : This file contains definition of vector.
* Creation Date: 20/09/2015
***********************************************************************************************************************/
#ifndef _VECT_H
#define _VECT_H
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
/* Undefined */
#pragma interrupt (r_undefined_exception)
void r_undefined_exception(void);
/* Reserved */
#pragma interrupt (r_reserved_exception)
void r_reserved_exception(void);
/* NMI */
#pragma interrupt (r_nmi_exception)
void r_nmi_exception(void);
/* BRK */
#pragma interrupt (r_brk_exception(vect=0))
void r_brk_exception(void);
/* ICU GROUPBE0 */
#pragma interrupt (r_icu_group_be0_interrupt(vect=106))
void r_icu_group_be0_interrupt(void);
/* ICU GROUPBL0 */
#pragma interrupt (r_icu_group_bl0_interrupt(vect=110))
void r_icu_group_bl0_interrupt(void);
/* ICU GROUPBL1 */
#pragma interrupt (r_icu_group_bl1_interrupt(vect=111))
void r_icu_group_bl1_interrupt(void);
/* ICU GROUPAL0 */
#pragma interrupt (r_icu_group_al0_interrupt(vect=112))
void r_icu_group_al0_interrupt(void);
/* ICU GROUPAL1 */
#pragma interrupt (r_icu_group_al1_interrupt(vect=113))
void r_icu_group_al1_interrupt(void);
/*;<<VECTOR DATA START (POWER ON RESET)>> */
/*;Power On Reset PC */
extern void PowerON_Reset_PC(void);
/*;<<VECTOR DATA END (POWER ON RESET)>> */
#endif

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253
FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c Normal file
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup, standard FreeRTOS hook functions, and the ISR hander called
* by the RTOS after interrupt entry (including nesting) has been taken care of.
*
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
*
*/
/* Standard includes. */
#include "string.h"
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Renesas code generator includes. */
#include "r_cg_macrodriver.h"
#include "r_cg_sci.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* Configure the hardware as necessary to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
extern void main_blinky( void );
#else
extern void main_full( void );
#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
within this file. */
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
void vApplicationTickHook( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* Configure the hardware ready to run the demo. */
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
of this file. */
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Set up SCI7 receive buffer and callback function. */
R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1);
/* Enable SCI7 operations. */
R_SCI7_Start();
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
/* Force an assert. */
configASSERT( ( volatile void * ) NULL );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
/* Force an assert. */
configASSERT( ( volatile void * ) NULL );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeHeapSpace;
/* This is just a trivial example of an idle hook. It is called on each
cycle of the idle task. It must *NOT* attempt to block. In this case the
idle task just queries the amount of FreeRTOS heap that remains. See the
memory management section on the http://www.FreeRTOS.org web site for memory
management options. If there is a lot of heap memory free then the
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
RAM. */
xFreeHeapSpace = xPortGetFreeHeapSize();
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
( void ) xFreeHeapSpace;
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
{
extern void vFullDemoTickHook( void );
vFullDemoTickHook();
}
#endif
}
/*-----------------------------------------------------------*/
/* The RX port uses this callback function to configure its tick interrupt.
This allows the application to choose the tick interrupt source. */
void vApplicationSetupTimerInterrupt( void )
{
const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;
/* Disable register write protection. */
SYSTEM.PRCR.WORD = ulEnableRegisterWrite;
/* Enable compare match timer 0. */
MSTP( CMT0 ) = 0;
/* Interrupt on compare match. */
CMT0.CMCR.BIT.CMIE = 1;
/* Set the compare match value. */
CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );
/* Divide the PCLK by 8. */
CMT0.CMCR.BIT.CKS = 0;
/* Enable the interrupt... */
_IEN( _CMT0_CMI0 ) = 1;
/* ...and set its priority to the application defined kernel priority. */
_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the timer. */
CMT.CMSTR0.BIT.STR0 = 1;
/* Reneable register protection. */
SYSTEM.PRCR.WORD = ulDisableRegisterWrite;
}

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FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/rskrx71mdef.h Normal file
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/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
* this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : rskrx71mdef.h
* Device(s) : R5F571MLCxFC
* Tool-Chain : CCRX
* H/W Platform : RSK+RX71M
* Description : Defines macros relating to the RSK+RX71M user LEDs and switches
***********************************************************************************************************************/
/**********************************************************************************************************************
* History : DD.MM.YYYY Version Description
* : 23.01.2015 1.00 First Release
***********************************************************************************************************************/
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
#ifndef RSKRX71M_H
#define RSKRX71M_H
/* General Values */
#define LED_ON (0)
#define LED_OFF (1)
#define SET_BIT_HIGH (1)
#define SET_BIT_LOW (0)
#define SET_BYTE_HIGH (0xFF)
#define SET_BYTE_LOW (0x00)
/* Switches */
#define SW1 (PORT1.PIDR.BIT.B5)
#define SW2 (PORT1.PIDR.BIT.B2)
#define SW3 (PORT0.PIDR.BIT.B7)
/* LED port settings */
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED2 (PORT2.PODR.BIT.B6)
#define LED3 (PORT2.PODR.BIT.B7)
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Exported global variables
***********************************************************************************************************************/
/***********************************************************************************************************************
Exported global functions (to be accessed by other files)
***********************************************************************************************************************/
#endif