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Update M33F simulator Keil example (#990)

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* Update M33F simulator Keil example

The example is updated to use latest CMSIS 5.9.0 and Device startup
2.1.0.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Increase timeout and correct config file path in the secure project

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove auto-generated files

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
This commit is contained in:
Devaraj Ranganna 2023-04-18 07:53:31 +01:00 • committed by GitHub
parent 5eaf2f3bce
commit 27cbc7f6a2
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GPG key ID: 4AEE18F83AFDEB23
15 changed files with 264 additions and 3336 deletions
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8
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/.gitignore vendored Normal file
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@ -0,0 +1,8 @@
# Keil autogenerated files.
RTE/
*.uvgui*
EventRecorderStub.scvd
# Build artifacts.
Objects/
Listings/

77
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.sct
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@ -1,3 +1,9 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
; NOTE: ARMv8-M MPU requires that each region must start on a 32 byte aligned
; address and the size of a region must be a multiple of 32 bytes.
;
@ -19,7 +25,58 @@
; | Unprivileged Data |
; ---------------------
LR_APP 0x00200000 ; load region
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00200000
#define __ROM_SIZE 0x00200000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20200000
#define __RAM_SIZE 0x00020000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
LR_APP __ROM_BASE __ROM_SIZE ; load region
{
ER_IROM_NS_PRIVILEGED +0 ALIGN 32
{
@ -50,7 +107,7 @@ LR_APP 0x00200000 ; load region
{
}
ER_IRAM_NS_PRIVILEGED 0x20200000 ALIGN 32
ER_IRAM_NS_PRIVILEGED __RAM_BASE ALIGN 32
{
*(privileged_data)
}
@ -67,4 +124,20 @@ LR_APP 0x00200000 ; load region
ER_IRAM_NS_UNPRIVILEGED_ALIGN +0 ALIGN 32 EMPTY 0x0
{
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE ; Reserve empty region for heap
{
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE ; Reserve empty region for stack
{
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE ; Reserve empty region for stack seal immediately after stack
{
}
#endif
}

45
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvoptx
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@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>16</nTsel>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -120,7 +120,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(6010=70,43,547,639,0)(6018=1091,145,1280,478,0)(6019=1091,137,1280,457,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=1022,0,1280,731,0)(6015=2837,586,3095,1208,1)(6003=2678,41,3260,577,1)(6000=-1,-1,-1,-1,0)</Name>
<Name>(6010=70,43,547,639,0)(6018=1091,145,1280,478,0)(6019=1091,137,1280,457,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=1022,0,1280,731,0)(6015=1278,242,1536,864,1)(6003=1966,270,2548,806,1)(6000=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -135,7 +135,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF".\FVP\MPS2_Cortex-M\ARMCM33_DSP_FP_TZ_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O528390 -C0 -MC".\VHT\VHT_MPS2_Cortex-M33.exe" -MF"..\VHT_MPS2_Cortex-M33-config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -143,40 +143,7 @@
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>105</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>2116472</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>&lt;2&gt;.\main_ns.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\FreeRTOSDemo_ns\main_ns.c\105</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>67</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>2044</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>&lt;1&gt;.\main_s.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\FreeRTOSDemo_s\main_s.c\67</Expression>
</Bp>
</Breakpoint>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
@ -472,7 +439,7 @@
<Group>
<GroupName>User</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

55
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/FreeRTOSDemo_ns.uvprojx
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@ -10,13 +10,13 @@
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
<pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM33_DSP_FP_TZ</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.6.0</PackID>
<PackID>ARM.CMSIS.5.9.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -185,6 +185,8 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>16</StupSel>
@ -312,7 +314,7 @@
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>2</Optim>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
@ -351,7 +353,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -512,14 +514,14 @@
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
@ -538,26 +540,38 @@
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
<targetInfos/>
</file>
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<file attr="config" category="linkerScript" condition="Startup ARMCC6 Unsecure" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6.sct" version="1.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.S" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.S</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.3.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
@ -625,4 +639,13 @@
</files>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>FreeRTOSDemo_ns</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

1260
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
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267
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
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@ -1,267 +0,0 @@
;/**************************************************************************//**
; * @file startup_ARMCM33.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM33 Device Series
; * @version V5.00
; * @date 21. October 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD SecureFault_Handler ; Secure Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SecureFault_Handler\
PROC
EXPORT SecureFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

99
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
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@ -1,99 +0,0 @@
/**************************************************************************//**
* @file system_ARMCM33.c
* @brief CMSIS Device System Source File for
* ARMCM33 Device Series
* @version V5.00
* @date 02. November 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM33)
#include "ARMCM33.h"
#elif defined (ARMCM33_TZ)
#include "ARMCM33_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM33.h"
#endif
#elif defined (ARMCM33_DSP_FP)
#include "ARMCM33_DSP_FP.h"
#elif defined (ARMCM33_DSP_FP_TZ)
#include "ARMCM33_DSP_FP_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM33.h"
#endif
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
(3U << 11U*2U) ); /* set CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

7
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/ReadMe.txt
View file

@ -1,3 +1,10 @@
Prerequisites:
- Keil MDK release 5.38a or 5.37
Notes:
The demo has been updated to work with latest MDK release 5.38a. From Keil MDK version 5.37, Arm Virtual Hardware (AVH)
models Version 11.17.40 are replacing the FVP models.
Instructions to Build and Run:
- The Keil multi-project workspace FreeRTOSDemo.uvmpw contains projects for both the secure project, and non secure project.
- Set the FreeRTOSDemo_s project as Active - Right click on "Project: FreeRTOSDemo_s" and select "Set as Active Project".

72
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.sct
View file

@ -1,8 +1,60 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
; command above MUST be in first line (no comment above!)
LR_IROM_S 0x00000000 0x00200000 ; load region size_region
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00200000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00020000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
LR_IROM_S __ROM_BASE __ROM_SIZE ; load region size_region
{
ER_IROM_S +0 ; load address = execution address
{
@ -13,8 +65,18 @@ LR_IROM_S 0x00000000 0x00200000 ; load region size_region
.ANY (+XO)
}
RW_IRAM_S 0x20000000 0x00020000 ; RW data
RW_IRAM_S __RAM_BASE __RAM_SIZE ; RW data
{
.ANY (+RW +ZI)
}
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE ; Reserve empty region for stack
{
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE ; Reserve empty region for stack seal immediately after stack
{
}
#endif
}

8
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvoptx
View file

@ -10,7 +10,7 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
@ -73,7 +73,7 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>16</nTsel>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -135,7 +135,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF".\FVP\MPS2_Cortex-M\ARMCM33_DSP_FP_TZ_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O528390 -C0 -MC".\VHT\VHT_MPS2_Cortex-M33.exe" -MF"..\VHT_MPS2_Cortex-M33-config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>

52
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/FreeRTOSDemo_s.uvprojx
View file

@ -10,13 +10,13 @@
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6130001::V6.13.1::.\ARMCLANG</pCCUsed>
<pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM33_DSP_FP_TZ</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.6.0</PackID>
<PackID>ARM.CMSIS.5.9.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -185,6 +185,8 @@
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
@ -312,7 +314,7 @@
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>2</Optim>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
@ -351,7 +353,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
@ -472,40 +474,54 @@
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<file attr="config" category="linkerScript" condition="Startup ARMCC6 Secure" name="Device\ARM\ARMCM33\Source\ARM\ARMCM33_ac6_s.sct" version="1.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6_s.sct</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<file attr="config" category="header" condition="TZ Secure" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC6" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.S" version="1.0.0">
<instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.S</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.3.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\startup_ARMCM33.c" version="2.1.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM33 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="1"/>
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="FVP Simulation Model"/>
</targetInfos>

1260
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h
View file

File diff suppressed because it is too large Load diff

267
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s
View file

@ -1,267 +0,0 @@
;/**************************************************************************//**
; * @file startup_ARMCM33.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM33 Device Series
; * @version V5.00
; * @date 21. October 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD SecureFault_Handler ; Secure Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SecureFault_Handler\
PROC
EXPORT SecureFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

99
FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/Secure/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c
View file

@ -1,99 +0,0 @@
/**************************************************************************//**
* @file system_ARMCM33.c
* @brief CMSIS Device System Source File for
* ARMCM33 Device Series
* @version V5.00
* @date 02. November 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM33)
#include "ARMCM33.h"
#elif defined (ARMCM33_TZ)
#include "ARMCM33_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM33.h"
#endif
#elif defined (ARMCM33_DSP_FP)
#include "ARMCM33_DSP_FP.h"
#elif defined (ARMCM33_DSP_FP_TZ)
#include "ARMCM33_DSP_FP_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM33.h"
#endif
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
(3U << 11U*2U) ); /* set CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

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FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/VHT_MPS2_Cortex-M33-config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------