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Jonathan Cubides 2025-03-27 09:24:57 +01:00
parent 5b1a05f64c
commit 26e5060307
2 changed files with 52 additions and 40 deletions
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2
portable/GCC/RISC-V/portASM.S
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@ -191,8 +191,8 @@ definitions. */
* x6 * x6
* x5 * x5
* portTASK_RETURN_ADDRESS * portTASK_RETURN_ADDRESS
* [VPU registers (when enabled/available) go here]
* [FPU registers (when enabled/available) go here] * [FPU registers (when enabled/available) go here]
* [VPU registers (when enabled/available) go here]
* [chip specific registers go here] * [chip specific registers go here]
* mstatus * mstatus
* pxCode * pxCode

90
portable/GCC/RISC-V/portContext.h
View file

@ -111,6 +111,7 @@
#define MSTATUS_VS_CLEAN 0x400 #define MSTATUS_VS_CLEAN 0x400
#define MSTATUS_VS_DIRTY 0x600 #define MSTATUS_VS_DIRTY 0x600
#define MSTATUS_VS_OFFSET 9 #define MSTATUS_VS_OFFSET 9
#ifndef __riscv_vector #ifndef __riscv_vector
#error configENABLE_VPU must not be set to 1 if the hardware does not have VPU #error configENABLE_VPU must not be set to 1 if the hardware does not have VPU
#endif #endif
@ -204,23 +205,26 @@ addi sp, sp, ( portFPU_CONTEXT_SIZE )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
.macro portcontexSAVE_VPU_CONTEXT .macro portcontexSAVE_VPU_CONTEXT
/* Store the vector registers on groups of 8. Use the length in bytes (vlenb) /* Un-reserve the space reserved for mstatus and epc. */
to know how much space they need and reserve it in the stack. */ add sp, sp, ( 2 * portWORD_SIZE )
csrr t0, vlenb
slli t0, t0, 3 /* vlenb * 8 */ csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */
neg t0, t0 slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
/* Store the vector registers. */ neg t0, t0
/* Store the vector registers in group of 8. */
add sp, sp, t0 add sp, sp, t0
vs8r.v v0, (sp) vs8r.v v0, (sp) /* Store v0-v7. */
add sp, sp, t0 add sp, sp, t0
vs8r.v v8, (sp) vs8r.v v8, (sp) /* Store v8-v15. */
add sp, sp, t0 add sp, sp, t0
vs8r.v v16, (sp) vs8r.v v16, (sp) /* Store v16-v23. */
add sp, sp, t0 add sp, sp, t0
vs8r.v v24, (sp) vs8r.v v24, (sp) /* Store v24-v31. */
/* Store the VPU registers. */
addi sp, sp, -( 4 * portWORD_SIZE ) /* Store the VPU CSRs. */
csrr t0, vstart addi sp, sp, -( 4 * portWORD_SIZE )
csrr t0, vstart
store_x t0, 0 * portWORD_SIZE( sp ) store_x t0, 0 * portWORD_SIZE( sp )
csrr t0, vcsr csrr t0, vcsr
store_x t0, 1 * portWORD_SIZE( sp ) store_x t0, 1 * portWORD_SIZE( sp )
@ -228,33 +232,41 @@ csrr t0, vl
store_x t0, 2 * portWORD_SIZE( sp ) store_x t0, 2 * portWORD_SIZE( sp )
csrr t0, vtype csrr t0, vtype
store_x t0, 3 * portWORD_SIZE( sp ) store_x t0, 3 * portWORD_SIZE( sp )
/* Re-reserve the space for mstatus and epc. */
add sp, sp, -( 2 * portWORD_SIZE )
.endm .endm
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
.macro portcontextRESTORE_VPU_CONTEXT .macro portcontextRESTORE_VPU_CONTEXT
/* Restore the VPU registers. */ /* Un-reserve the space reserved for mstatus and epc. */
load_x t0, 0 * portWORD_SIZE( sp ) add sp, sp, ( 2 * portWORD_SIZE )
/* Restore the VPU CSRs. */
load_x t0, 0 * portWORD_SIZE( sp )
csrw vstart, t0 csrw vstart, t0
load_x t0, 1 * portWORD_SIZE( sp ) load_x t0, 1 * portWORD_SIZE( sp )
csrw vcsr, t0 csrw vcsr, t0
load_x t0, 2 * portWORD_SIZE( sp ) load_x t0, 2 * portWORD_SIZE( sp )
load_x t1, 3 * portWORD_SIZE( sp ) load_x t1, 3 * portWORD_SIZE( sp )
/* vlen and vtype can only be updated by using vset*vl* instructions. */ vsetvl x0, t0, t1 /* vlen and vtype can only be updated by using vset*vl* instructions. */
vsetvl x0, t0, t1 addi sp, sp, ( 4 * portWORD_SIZE )
addi sp, sp, ( 4 * portWORD_SIZE )
/* Load the vector registers on groups of 8. Use the length in bytes (vlenb) csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */
to know how much space they use. */ slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
csrr t0, vlenb
slli t0, t0, 3 /* vlenb * 8 */
/* Restore the vector registers. */ /* Restore the vector registers. */
vl8r.v v24, (sp) vl8r.v v24, (sp)
add sp, sp, t0 add sp, sp, t0
vl8r.v v16, (sp) vl8r.v v16, (sp)
add sp, sp, t0 add sp, sp, t0
vl8r.v v8, (sp) vl8r.v v8, (sp)
add sp, sp, t0 add sp, sp, t0
vl8r.v v0, (sp) vl8r.v v0, (sp)
add sp, sp, t0 add sp, sp, t0
/* Re-reserve the space for mstatus and epc. */
add sp, sp, -( 2 * portWORD_SIZE )
.endm .endm
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -310,10 +322,10 @@ store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the criti
srl t1, t0, MSTATUS_VS_OFFSET srl t1, t0, MSTATUS_VS_OFFSET
andi t1, t1, 3 andi t1, t1, 3
addi t2, x0, 3 addi t2, x0, 3
bne t1, t2, 1f /* If VPU status is not dirty, do not save FPU registers. */ bne t1, t2, 2f /* If VPU status is not dirty, do not save FPU registers. */
portcontexSAVE_VPU_CONTEXT portcontexSAVE_VPU_CONTEXT
1: 2:
#endif #endif
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
@ -326,14 +338,14 @@ store_x t0, 1 * portWORD_SIZE( sp )
srl t1, t0, MSTATUS_FS_OFFSET srl t1, t0, MSTATUS_FS_OFFSET
andi t1, t1, 3 andi t1, t1, 3
addi t2, x0, 3 addi t2, x0, 3
bne t1, t2, 2f bne t1, t2, 3f
li t1, ~MSTATUS_FS_MASK li t1, ~MSTATUS_FS_MASK
and t0, t0, t1 and t0, t0, t1
li t1, MSTATUS_FS_CLEAN li t1, MSTATUS_FS_CLEAN
or t0, t0, t1 or t0, t0, t1
csrw mstatus, t0 csrw mstatus, t0
2: 3:
#endif #endif
#if( configENABLE_VPU == 1 ) #if( configENABLE_VPU == 1 )
@ -341,14 +353,14 @@ store_x t0, 1 * portWORD_SIZE( sp )
srl t1, t0, MSTATUS_VS_OFFSET srl t1, t0, MSTATUS_VS_OFFSET
andi t1, t1, 3 andi t1, t1, 3
addi t2, x0, 3 addi t2, x0, 3
bne t1, t2, 2f bne t1, t2, 4f
li t1, ~MSTATUS_VS_MASK li t1, ~MSTATUS_VS_MASK
and t0, t0, t1 and t0, t0, t1
li t1, MSTATUS_VS_CLEAN li t1, MSTATUS_VS_CLEAN
or t0, t0, t1 or t0, t0, t1
csrw mstatus, t0 csrw mstatus, t0
2: 4:
#endif #endif
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
@ -396,10 +408,10 @@ portasmRESTORE_ADDITIONAL_REGISTERS
srl t1, t0, MSTATUS_VS_OFFSET srl t1, t0, MSTATUS_VS_OFFSET
andi t1, t1, 3 andi t1, t1, 3
addi t2, x0, 3 addi t2, x0, 3
bne t1, t2, 3f /* If VPU status is not dirty, do not restore VPU registers. */ bne t1, t2, 5f /* If VPU status is not dirty, do not restore VPU registers. */
portcontextRESTORE_VPU_CONTEXT portcontextRESTORE_VPU_CONTEXT
3: 5:
#endif /* ifdef portasmSTORE_VPU_CONTEXT */ #endif /* ifdef portasmSTORE_VPU_CONTEXT */
#if( configENABLE_FPU == 1 ) #if( configENABLE_FPU == 1 )
@ -407,10 +419,10 @@ portasmRESTORE_ADDITIONAL_REGISTERS
srl t1, t0, MSTATUS_FS_OFFSET srl t1, t0, MSTATUS_FS_OFFSET
andi t1, t1, 3 andi t1, t1, 3
addi t2, x0, 3 addi t2, x0, 3
bne t1, t2, 3f /* If FPU status is not dirty, do not restore FPU registers. */ bne t1, t2, 6f /* If FPU status is not dirty, do not restore FPU registers. */
portcontextRESTORE_FPU_CONTEXT portcontextRESTORE_FPU_CONTEXT
3: 6:
#endif /* ifdef portasmSTORE_FPU_CONTEXT */ #endif /* ifdef portasmSTORE_FPU_CONTEXT */
load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */