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armv8-r: Add Arm Cortex-R82 non-MPU port
The goal of this commit is to add the GCC/ARMClang non-MPU port variant for ARM Cortex-R82 processor which is ARMv8-R AArch64 based. The work done is inspired by the GCC ARM_AARCH64 FreeRTOS port. This port has the following features: * Uses single security state (non TrustZone). * Supports SMP (Symmetric multi-processing). * Doesn't support Hypervisor (EL2). * Doesn't support neither PMSA (MPU) nor VMSA (MMU). Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
This commit is contained in:
Ahmed Ismail
parent
7225fbcbb9
commit
255b9b642b
7 changed files with 1622 additions and 0 deletions
521
portable/GCC/ARM_CR82/portASM.S
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portable/GCC/ARM_CR82/portASM.S
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2025 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* This file is tailored for ARM Cortex-R82 with SMP enabled.
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* It includes macros and functions for saving/restoring task context,
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* handling interrupts, and supporting multi-core operations.
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*/
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#include "FreeRTOSConfig.h"
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.text
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/* Variables and functions. */
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.extern ullMaxAPIPriorityMask
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#if ( configNUMBER_OF_CORES == 1 )
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.extern pxCurrentTCB
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.extern ullCriticalNesting
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.extern ullPortInterruptNesting
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#else /* #if ( configNUMBER_OF_CORES == 1 ) */
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.extern pxCurrentTCBs
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.extern ullCriticalNestings
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.extern ullPortInterruptNestings
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#endif
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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.extern ullPortTaskHasFPUContext
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.extern ullPortYieldRequired
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.extern _freertos_vector_table
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.global vPortRestoreTaskContext
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.macro saveallgpregisters
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/* Save all general-purpose registers on stack. */
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STP X0, X1, [ SP, # - 0x10 ] !
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STP X2, X3, [ SP, # - 0x10 ] !
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STP X4, X5, [ SP, # - 0x10 ] !
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STP X6, X7, [ SP, # - 0x10 ] !
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STP X8, X9, [ SP, # - 0x10 ] !
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STP X10, X11, [ SP, # - 0x10 ] !
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STP X12, X13, [ SP, # - 0x10 ] !
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STP X14, X15, [ SP, # - 0x10 ] !
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STP X16, X17, [ SP, # - 0x10 ] !
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STP X18, X19, [ SP, # - 0x10 ] !
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STP X20, X21, [ SP, # - 0x10 ] !
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STP X22, X23, [ SP, # - 0x10 ] !
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STP X24, X25, [ SP, # - 0x10 ] !
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STP X26, X27, [ SP, # - 0x10 ] !
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STP X28, X29, [ SP, # - 0x10 ] !
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STR X30, [ SP, # - 0x10 ] !
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.endm
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.macro restoreallgpregisters
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/* Restore all general-purpose registers from stack. */
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LDR X30, [ SP ], # 0x10
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LDP X28, X29, [ SP ], # 0x10
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LDP X26, X27, [ SP ], # 0x10
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LDP X24, X25, [ SP ], # 0x10
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LDP X22, X23, [ SP ], # 0x10
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LDP X20, X21, [ SP ], # 0x10
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LDP X18, X19, [ SP ], # 0x10
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LDP X16, X17, [ SP ], # 0x10
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LDP X14, X15, [ SP ], # 0x10
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LDP X12, X13, [ SP ], # 0x10
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LDP X10, X11, [ SP ], # 0x10
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LDP X8, X9, [ SP ], # 0x10
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LDP X6, X7, [ SP ], # 0x10
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LDP X4, X5, [ SP ], # 0x10
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LDP X2, X3, [ SP ], # 0x10
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LDP X0, X1, [ SP ], # 0x10
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.endm
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.macro savefuncontextgpregs
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/* Save function context general-purpose registers. */
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STP X0, X1, [ SP, # - 0x10 ] !
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STP X2, X3, [ SP, # - 0x10 ] !
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STP X4, X5, [ SP, # - 0x10 ] !
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STP X6, X7, [ SP, # - 0x10 ] !
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STP X8, X9, [ SP, # - 0x10 ] !
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STP X10, X11, [ SP, # - 0x10 ] !
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STP X12, X13, [ SP, # - 0x10 ] !
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STP X14, X15, [ SP, # - 0x10 ] !
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STP X16, X17, [ SP, # - 0x10 ] !
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STP X18, X29, [ SP, # - 0x10 ] !
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STR X30, [ SP, # - 0x10 ] !
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.endm
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.macro restorefuncontextgpregs
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/* Restore function context general-purpose registers. */
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LDR X30, [ SP ], # 0x10
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LDP X18, X29, [ SP ], # 0x10
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LDP X16, X17, [ SP ], # 0x10
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LDP X14, X15, [ SP ], # 0x10
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LDP X12, X13, [ SP ], # 0x10
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LDP X10, X11, [ SP ], # 0x10
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LDP X8, X9, [ SP ], # 0x10
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LDP X6, X7, [ SP ], # 0x10
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LDP X4, X5, [ SP ], # 0x10
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LDP X2, X3, [ SP ], # 0x10
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LDP X0, X1, [ SP ], # 0x10
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.endm
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.macro savefloatregisters
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/* Save floating-point registers and configuration/status registers. */
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STP Q0, Q1, [ SP, # - 0x20 ] !
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STP Q2, Q3, [ SP, # - 0x20 ] !
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STP Q4, Q5, [ SP, # - 0x20 ] !
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STP Q6, Q7, [ SP, # - 0x20 ] !
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STP Q8, Q9, [ SP, # - 0x20 ] !
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STP Q10, Q11, [ SP, # - 0x20 ] !
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STP Q12, Q13, [ SP, # - 0x20 ] !
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STP Q14, Q15, [ SP, # - 0x20 ] !
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STP Q16, Q17, [ SP, # - 0x20 ] !
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STP Q18, Q19, [ SP, # - 0x20 ] !
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STP Q20, Q21, [ SP, # - 0x20 ] !
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STP Q22, Q23, [ SP, # - 0x20 ] !
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STP Q24, Q25, [ SP, # - 0x20 ] !
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STP Q26, Q27, [ SP, # - 0x20 ] !
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STP Q28, Q29, [ SP, # - 0x20 ] !
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STP Q30, Q31, [ SP, # - 0x20 ] !
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MRS X9, FPSR
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MRS X10, FPCR
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STP W9, W10, [ SP, # - 0x10 ] !
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.endm
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.macro restorefloatregisters
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/* Restore floating-point registers and configuration/status registers. */
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LDP W9, W10, [ SP ], # 0x10
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MSR FPSR, X9
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MSR FPCR, X10
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LDP Q30, Q31, [ SP ], # 0x20
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LDP Q28, Q29, [ SP ], # 0x20
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LDP Q26, Q27, [ SP ], # 0x20
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LDP Q24, Q25, [ SP ], # 0x20
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LDP Q22, Q23, [ SP ], # 0x20
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LDP Q20, Q21, [ SP ], # 0x20
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LDP Q18, Q19, [ SP ], # 0x20
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LDP Q16, Q17, [ SP ], # 0x20
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LDP Q14, Q15, [ SP ], # 0x20
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LDP Q12, Q13, [ SP ], # 0x20
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LDP Q10, Q11, [ SP ], # 0x20
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LDP Q8, Q9, [ SP ], # 0x20
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LDP Q6, Q7, [ SP ], # 0x20
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LDP Q4, Q5, [ SP ], # 0x20
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LDP Q2, Q3, [ SP ], # 0x20
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LDP Q0, Q1, [ SP ], # 0x20
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.endm
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.macro portSAVE_CONTEXT
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/* Switch to use the EL0 stack pointer. */
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MSR SPSEL, # 0
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/* Save the entire context. */
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saveallgpregisters
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/* Save the SPSR and ELR values. */
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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STP X2, X3, [ SP, # - 0x10 ] !
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/* Save the critical section nesting depth. */
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LDR X0, ullCriticalNestingsConst
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#if configNUMBER_OF_CORES > 1
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/* Calculate per-core index using MPIDR_EL1 for SMP support. */
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MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X1, X1, # 0xff /* Extract Aff0 (core ID) */
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LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes) */
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ADD X0, X0, X1 /* Add offset to base address */
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#endif
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LDR X3, [ X0 ]
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/* Save the FPU context indicator. */
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LDR X0, ullPortTaskHasFPUContextConst
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#if configNUMBER_OF_CORES > 1
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ADD X0, X0, X1 /* Add to the base of the FPU array */
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#endif
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LDR X2, [ X0 ]
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/* Save the FPU context, if any (32 128-bit registers). */
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CMP X2, # 0
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B.EQ 1f /* FPU context not present, skip saving FPU registers */
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savefloatregisters
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1 :
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/* Store the critical nesting count and FPU context indicator. */
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STP X2, X3, [ SP, # - 0x10 ] !
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LDR X0, pxCurrentTCBsConst
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#if ( configNUMBER_OF_CORES > 1 )
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MRS X1, MPIDR_EL1 /* Read Multiprocessor Affinity Register */
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AND X1, X1, # 0xff /* Extract core ID */
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LSL X1, X1, # 3 /* Multiply core ID by pointer size */
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ADD X0, X0, X1 /* Offset for current core's TCB pointer */
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#endif
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LDR X1, [ X0 ]
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MOV X0, SP /* Save current stack pointer */
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STR X0, [ X1 ]
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/* Switch to use the ELx stack pointer. */
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MSR SPSEL, # 1
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.endm
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.macro portRESTORE_CONTEXT
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/* Switch to use the EL0 stack pointer. */
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MSR SPSEL, # 0
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/* Set the SP to point to the stack of the task being restored. */
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LDR X0, pxCurrentTCBsConst
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#if configNUMBER_OF_CORES > 1
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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#endif
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LDR X1, [ X0 ]
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LDR X0, [ X1 ]
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MOV SP, X0
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LDP X2, X3, [ SP ], # 0x10 /* Retrieve critical nesting and FPU indicator */
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LDR X0, ullCriticalNestingsConst
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/* Calculate offset for current core's ullCriticalNesting */
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#if configNUMBER_OF_CORES > 1
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/* Existing code to get core ID and scale to pointer size is reused. */
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MRS X1, MPIDR_EL1 /* Read Multiprocessor Affinity Register */
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AND X1, X1, # 0xff /* Extract Aff0, which contains the core ID */
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LSL X1, X1, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system) */
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ADD X0, X0, X1 /* Add offset for the current core's ullCriticalNesting */
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#endif
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MOV X1, # 255 /* Default mask */
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CMP X3, # 0
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B.EQ 1f
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LDR X6, ullMaxAPIPriorityMaskConst
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LDR X1, [ X6 ] /* Use computed mask value */
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1 :
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MSR ICC_PMR_EL1, X1 /* Set interrupt mask */
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DSB SY
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ISB SY
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STR X3, [ X0 ] /* Restore critical nesting */
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/* Restore the FPU context indicator. */
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LDR X0, ullPortTaskHasFPUContextConst
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#if configNUMBER_OF_CORES > 1
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/* Existing code to get core ID and scale to pointer size is reused. */
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MRS X1, MPIDR_EL1 /* Read Multiprocessor Affinity Register */
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AND X1, X1, # 0xff /* Extract Aff0, which contains the core ID */
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LSL X1, X1, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system) */
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/* Restore the FPU context indicator. */
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ADD X0, X0, X1 /* Add to the base of the FPU array */
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#endif
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STR X2, [ X0 ]
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/* Restore the FPU context, if any. */
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CMP X2, # 0
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B.EQ 1f
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restorefloatregisters
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1 :
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LDP X2, X3, [ SP ], # 0x10 /* Restore SPSR and ELR */
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MSR SPSR_EL1, X3
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MSR ELR_EL1, X2
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restoreallgpregisters
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/* Switch to use the ELx stack pointer. */
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MSR SPSEL, # 1
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ERET
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.endm
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/******************************************************************************
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* FreeRTOS_SWI_Handler handler is used to perform a context switch.
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*****************************************************************************/
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.align 8
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.type FreeRTOS_SWI_Handler, % function
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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MRS X0, ESR_EL1
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LSR X1, X0, # 26
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CMP X1, # 0x15 /* 0x15 = SVC instruction. */
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B.NE FreeRTOS_Abort
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#if configNUMBER_OF_CORES > 1
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MRS x0, mpidr_el1
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AND x0, x0, 255
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#endif
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BL vTaskSwitchContext
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portRESTORE_CONTEXT
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FreeRTOS_Abort:
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/* Full ESR is in X0, exception class code is in X1. */
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B .
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/******************************************************************************
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* vPortRestoreTaskContext is used to start the scheduler.
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*****************************************************************************/
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.align 8
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.type vPortRestoreTaskContext, % function
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vPortRestoreTaskContext:
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.set freertos_vector_base, _freertos_vector_table
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/* Install the FreeRTOS interrupt handlers. */
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LDR X1, = freertos_vector_base
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MSR VBAR_EL1, X1
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DSB SY
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ISB SY
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/* Start the first task. */
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portRESTORE_CONTEXT
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/******************************************************************************
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* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
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*
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* This handler is supposed to be used only for IRQs and never for FIQs. Per ARM
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* GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since
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* this handler is only for IRQs, We can safely assume Group 1 while accessing
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* Interrupt Acknowledge and End Of Interrupt registers and therefore, use
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* ICC_IAR1_EL1 and ICC_EOIR1_EL1.
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*
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* [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals
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*****************************************************************************/
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.align 8
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.type FreeRTOS_IRQ_Handler, % function
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FreeRTOS_IRQ_Handler:
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/* Save volatile registers. */
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savefuncontextgpregs
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savefloatregisters
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/* Save the SPSR and ELR. */
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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STP X2, X3, [ SP, # - 0x10 ] !
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/* Increment the interrupt nesting counter. */
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LDR X5, ullPortInterruptNestingsConst /* Load base address of the ullPortYieldRequired array */
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#if configNUMBER_OF_CORES > 1
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/* Existing code to get core ID and scale to pointer size is reused. */
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MRS X2, MPIDR_EL1 /* Read Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0, which contains the core ID */
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LSL X2, X2, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system) */
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/* Calculate offset for the current core's ullPortYieldRequired and load its address. */
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ADD X5, X5, X2 /* Add offset for the current core's ullPortYieldRequired */
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#endif
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LDR X1, [ X5 ] /* Old nesting count in X1. */
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ADD X6, X1, # 1
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STR X6, [ X5 ] /* Address of nesting count variable in X5. */
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/* Maintain the interrupt nesting information across the function call. */
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STP X1, X5, [ SP, # - 0x10 ] !
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/* Read interrupt ID from the interrupt acknowledge register and store it
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* in X0 for future parameter and interrupt clearing use. */
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MRS X0, ICC_IAR1_EL1
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/* Maintain the interrupt ID value across the function call. */
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STP X0, X1, [ SP, # - 0x10 ] !
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/* Call the C handler. */
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BL vApplicationIRQHandler
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/* Disable interrupts. */
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MSR DAIFSET, # 2
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DSB SY
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ISB SY
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/* Restore the interrupt ID value. */
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LDP X0, X1, [ SP ], # 0x10
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/* End IRQ processing by writing interrupt ID value to the EOI register. */
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MSR ICC_EOIR1_EL1, X0
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||||
|
||||
/* Restore the critical nesting count. */
|
||||
LDP X1, X5, [ SP ], # 0x10
|
||||
STR X1, [ X5 ]
|
||||
|
||||
/* Has interrupt nesting unwound? */
|
||||
CMP X1, # 0
|
||||
B.NE Exit_IRQ_No_Context_Switch
|
||||
|
||||
/* Is a context switch required? */
|
||||
LDR X0, ullPortYieldRequiredConst
|
||||
#if configNUMBER_OF_CORES > 1
|
||||
/* Existing code to get core ID and scale to pointer size is reused. */
|
||||
MRS X2, MPIDR_EL1 /* Read Multiprocessor Affinity Register */
|
||||
AND X2, X2, # 0xff /* Extract Aff0, which contains the core ID */
|
||||
LSL X2, X2, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system) */
|
||||
|
||||
/* Calculate offset for the current core's ullPortYieldRequired and load its address. */
|
||||
ADD X0, X0, X2 /* Add offset for the current core's ullPortYieldRequired */
|
||||
#endif
|
||||
LDR X1, [ X0 ]
|
||||
CMP X1, # 0
|
||||
B.EQ Exit_IRQ_No_Context_Switch
|
||||
|
||||
/* Reset ullPortYieldRequired to 0. */
|
||||
MOV X2, # 0
|
||||
STR X2, [ X0 ]
|
||||
|
||||
/* Restore volatile registers. */
|
||||
LDP X4, X5, [ SP ], # 0x10 /* SPSR and ELR. */
|
||||
|
||||
MSR SPSR_EL1, X5
|
||||
MSR ELR_EL1, X4
|
||||
DSB SY
|
||||
ISB SY
|
||||
|
||||
restorefloatregisters
|
||||
restorefuncontextgpregs
|
||||
|
||||
/* Save the context of the current task and select a new task to run. */
|
||||
portSAVE_CONTEXT
|
||||
#if configNUMBER_OF_CORES > 1
|
||||
MRS x0, mpidr_el1
|
||||
AND x0, x0, 255
|
||||
#endif
|
||||
BL vTaskSwitchContext
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
Exit_IRQ_No_Context_Switch:
|
||||
/* Restore volatile registers. */
|
||||
LDP X4, X5, [ SP ], # 0x10 /* SPSR and ELR. */
|
||||
|
||||
MSR SPSR_EL1, X5
|
||||
MSR ELR_EL1, X4
|
||||
DSB SY
|
||||
ISB SY
|
||||
|
||||
restorefloatregisters
|
||||
restorefuncontextgpregs
|
||||
|
||||
ERET
|
||||
|
||||
/******************************************************************************
|
||||
* If the application provides an implementation of vApplicationIRQHandler(),
|
||||
* then it will get called directly without saving the FPU registers on
|
||||
* interrupt entry, and this weak implementation of
|
||||
* vApplicationIRQHandler() will not get called.
|
||||
*
|
||||
* If the application provides its own implementation of
|
||||
* vApplicationFPUSafeIRQHandler() then this implementation of
|
||||
* vApplicationIRQHandler() will be called, save the FPU registers, and then
|
||||
* call vApplicationFPUSafeIRQHandler().
|
||||
*
|
||||
* Therefore, if the application writer wants FPU registers to be saved on
|
||||
* interrupt entry their IRQ handler must be called
|
||||
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
|
||||
* FPU registers to be saved on interrupt entry their IRQ handler must be
|
||||
* called vApplicationIRQHandler().
|
||||
*****************************************************************************/
|
||||
|
||||
.align 8
|
||||
.weak vApplicationIRQHandler
|
||||
.type vApplicationIRQHandler, % function
|
||||
vApplicationIRQHandler:
|
||||
/* Save LR and FP on the stack */
|
||||
STP X29, X30, [ SP, # - 0x10 ] !
|
||||
|
||||
/* Save FPU registers (32 128-bits + 2 64-bits configuration and status registers) */
|
||||
savefloatregisters
|
||||
|
||||
/* Call the C handler. */
|
||||
BL vApplicationFPUSafeIRQHandler
|
||||
|
||||
/* Restore FPU registers */
|
||||
restorefloatregisters
|
||||
|
||||
/* Restore FP and LR */
|
||||
LDP X29, X30, [ SP ], # 0x10
|
||||
RET
|
||||
|
||||
.align 8
|
||||
#if ( configNUMBER_OF_CORES == 1 )
|
||||
pxCurrentTCBsConst:.dword pxCurrentTCB
|
||||
ullCriticalNestingsConst:.dword ullCriticalNesting
|
||||
ullPortInterruptNestingsConst:.dword ullPortInterruptNesting
|
||||
ullPortYieldRequiredConst:.dword ullPortYieldRequired
|
||||
ullPortTaskHasFPUContextConst:.dword ullPortTaskHasFPUContext
|
||||
#else
|
||||
pxCurrentTCBsConst:.dword pxCurrentTCBs
|
||||
ullCriticalNestingsConst:.dword ullCriticalNestings
|
||||
ullPortInterruptNestingsConst:.dword ullPortInterruptNestings
|
||||
ullPortYieldRequiredConst:.dword ullPortYieldRequired
|
||||
ullPortTaskHasFPUContextConst:.dword ullPortTaskHasFPUContext
|
||||
#endif /* if ( configNUMBER_OF_CORES == 1 ) */
|
||||
ullMaxAPIPriorityMaskConst:.dword ullMaxAPIPriorityMask
|
||||
vApplicationIRQHandlerConst:.word vApplicationIRQHandler
|
||||
.end
|
||||
Loading…
Add table
Add a link
Reference in a new issue