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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
xTaskGetTaskHandle() changed to xTaskGetHandle().
Tidy up CEC1302 demo. Ensure bit 0 of the task address is clear when setting up stack of initial Cortex-M3/4/7 stacks (for strict compliance, although not practically necessary). vTaskGetTaskInfo() changed to vTaskGetInfo() - with a macro added for backward compatibility.
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30 changed files with 179 additions and 112 deletions
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@ -131,6 +131,10 @@ occurred while the SysTick counter is stopped during tickless idle
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calculations. */
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#define portMISSED_COUNTS_FACTOR ( 45UL )
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/* For strict compliance with the Cortex-M spec the task start address should
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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@ -216,7 +220,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
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pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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@ -480,6 +484,8 @@ void xPortSysTickHandler( void )
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/* Enter a critical section but don't use the taskENTER_CRITICAL()
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method as that will mask interrupts that should exit sleep mode. */
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__asm volatile( "cpsid i" );
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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/* If a context switch is pending or a task is waiting for the scheduler
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to be unsuspended then abandon the low power entry. */
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@ -134,6 +134,10 @@ r0p1 port. */
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/* The systick is a 24-bit counter. */
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#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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/* For strict compliance with the Cortex-M spec the task start address should
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* A fiddle factor to estimate the number of SysTick counts that would have
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occurred while the SysTick counter is stopped during tickless idle
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calculations. */
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@ -233,7 +237,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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@ -537,6 +541,8 @@ void xPortSysTickHandler( void )
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/* Enter a critical section but don't use the taskENTER_CRITICAL()
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method as that will mask interrupts that should exit sleep mode. */
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__asm volatile( "cpsid i" );
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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/* If a context switch is pending or a task is waiting for the scheduler
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to be unsuspended then abandon the low power entry. */
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@ -133,6 +133,10 @@ occurred while the SysTick counter is stopped during tickless idle
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calculations. */
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#define portMISSED_COUNTS_FACTOR ( 45UL )
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/* For strict compliance with the Cortex-M spec the task start address should
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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@ -227,7 +231,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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@ -527,6 +531,8 @@ void xPortSysTickHandler( void )
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/* Enter a critical section but don't use the taskENTER_CRITICAL()
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method as that will mask interrupts that should exit sleep mode. */
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__asm volatile( "cpsid i" );
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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/* If a context switch is pending or a task is waiting for the scheduler
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to be unsuspended then abandon the low power entry. */
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@ -555,7 +555,7 @@ uint32_t ulReturn;
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this is not the case (if some bits represent a sub-priority).
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The priority grouping is configured by the GIC's binary point register
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(ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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(ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
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possible value (which may be above 0). */
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configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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}
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