diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.cproject b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.cproject new file mode 100644 index 000000000..7aefb8212 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.cproject @@ -0,0 +1,135 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.project b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.project new file mode 100644 index 000000000..7a0005113 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.project @@ -0,0 +1,104 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Common_Demo_Source + 2 + virtual:/virtual + + + FreeRTOS_Source + 2 + virtual:/virtual + + + Common_Demo_Source/blocktim.c + 1 + FREERTOS_BASE/Demo/Common/Minimal/blocktim.c + + + Common_Demo_Source/countsem.c + 1 + FREERTOS_BASE/Demo/Common/Minimal/countsem.c + + + Common_Demo_Source/dynamic.c + 1 + FREERTOS_BASE/Demo/Common/Minimal/dynamic.c + + + Common_Demo_Source/include + 2 + FREERTOS_BASE/Demo/Common/include + + + Common_Demo_Source/recmutex.c + 1 + FREERTOS_BASE/Demo/Common/Minimal/recmutex.c + + + FreeRTOS_Source/ARM_CM0 + 2 + FREERTOS_BASE/Source/portable/GCC/ARM_CM0 + + + FreeRTOS_Source/heap_4.c + 1 + FREERTOS_BASE/Source/portable/MemMang/heap_4.c + + + FreeRTOS_Source/include + 2 + FREERTOS_BASE/Source/include + + + FreeRTOS_Source/list.c + 1 + FREERTOS_BASE/Source/list.c + + + FreeRTOS_Source/queue.c + 1 + FREERTOS_BASE/Source/queue.c + + + FreeRTOS_Source/tasks.c + 1 + FREERTOS_BASE/Source/tasks.c + + + FreeRTOS_Source/timers.c + 1 + FREERTOS_BASE/Source/timers.c + + + + + FREERTOS_BASE + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/com.atollic.truestudio.debug.hardware_device.prefs new file mode 100644 index 000000000..669e09ab0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/com.atollic.truestudio.debug.hardware_device.prefs @@ -0,0 +1,11 @@ +BOARD=XMC1200_Boot_Kit +CODE_LOCATION=FLASH +ENDIAN=Little-endian +MCU=XMC1200-T038F0200 +MCU_VENDOR=Infineon +MODEL=Pro +PROBE=SEGGER J-LINK +PROJECT_FORMAT_VERSION=2 +TARGET=ARM\u00AE +VERSION=4.1.0 +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 000000000..96ff207bb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/delimiter=; +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/operation=remove +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/append=true +environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/delimiter=; +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/operation=remove +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/append=true +environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/RegTest.c new file mode 100644 index 000000000..472cba864 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/RegTest.c @@ -0,0 +1,232 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +void vRegTest1Task( void ) __attribute__((naked)); +void vRegTest2Task( void ) __attribute__((naked)); + +void vRegTest1Task( void ) +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " movs r0, #108 \n" + " mov r8, r0 \n" + " movs r0, #109 \n" + " mov r9, r0 \n" + " movs r0, #110 \n" + " mov r10, r0 \n" + " movs r0, #111 \n" + " mov r11, r0 \n" + " movs r0, #112 \n" + " mov r12, r0 \n" + " movs r0, #100 \n" + " \n" + "reg1_loop: \n" + " \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " movs r0, #108 \n" + " cmp r8, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #109 \n" + " cmp r9, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #110 \n" + " cmp r10, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #111 \n" + " cmp r11, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #112 \n" + " cmp r12, r0 \n" + " bne reg1_error_loop \n" + " \n" + " /* Everything passed, increment the loop counter. */ \n" + " push { r1 } \n" + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " add r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r1 } \n" + " \n" + " /* Start again. */ \n" + " movs r0, #100 \n" + " b reg1_loop \n" + " \n" + "reg1_error_loop: \n" + " /* If this line is hit then there was an error in a core register value. \n" + " The loop ensures the loop counter stops incrementing. */ \n" + " b reg1_error_loop \n" + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest2Task( void ) +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " movs r0, #8 \n" + " movs r8, r0 \n" + " movs r0, #9 \n" + " mov r9, r0 \n" + " movs r0, #10 \n" + " mov r10, r0 \n" + " movs r0, #11 \n" + " mov r11, r0 \n" + " movs r0, #12 \n" + " mov r12, r0 \n" + " movs r0, #10 \n" + " \n" + "reg2_loop: \n" + " \n" + " cmp r0, #10 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " movs r0, #8 \n" + " cmp r8, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #9 \n" + " cmp r9, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #10 \n" + " cmp r10, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #11 \n" + " cmp r11, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #12 \n" + " cmp r12, r0 \n" + " bne reg2_error_loop \n" + " \n" + " /* Everything passed, increment the loop counter. */ \n" + " push { r1 } \n" + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " add r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r1 } \n" + " \n" + " /* Start again. */ \n" + " movs r0, #10 \n" + " b reg2_loop \n" + " \n" + "reg2_error_loop: \n" + " /* If this line is hit then there was an error in a core register value. \n" + " The loop ensures the loop counter stops incrementing. */ \n" + " b reg2_error_loop \n" + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/startup_XMC1200.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/startup_XMC1200.s new file mode 100644 index 000000000..914907047 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/startup_XMC1200.s @@ -0,0 +1,608 @@ +/** +***************************************************************************** +** +** File : startup_XMC1200.s +** +** Abstract : This assembler file contains interrupt vector and +** startup code for ARM. +** +** Functions : Reset_Handler +** Default_Handler +** XMCVeneer code +** +** Target : Infineon $(DEVICE) Device +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. This file may only be built (assembled or compiled and linked) +** using the Atollic TrueSTUDIO(R) product. The use of this file together +** with other tools than Atollic TrueSTUDIO(R) is not permitted. +** +***************************************************************************** +*/ + +#ifdef DAVE_CE +#include +#else +#define CLKVAL1_SSW 0x80000000 +#define CLKVAL2_SSW 0x80000000 +#endif + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global Reset_Handler +.global InterruptVector +.global Default_Handler + +/* Linker script definitions */ +/* start address for the initialization values of the .data section */ +.word _sidata +/* start address for the .data section */ +.word _sdata +/* end address for the .data section */ +.word _edata +/* start address for the .bss section */ +.word _sbss +/* end address for the .bss section */ +.word _ebss + +.word VeneerLoadAddr +.word VeneerStart +.word VeneerSize + + +/** +**=========================================================================== +** Program - Reset_Handler +** Abstract: This code gets called after reset. +**=========================================================================== +*/ + .section .text.Reset_Handler,"ax", %progbits + .type Reset_Handler, %function +Reset_Handler: + /* Set stack pointer */ + ldr r0, =_estack + mov sp, r0 + + /* Branch to SystemInit function */ + bl SystemInit + + /* Copy data initialization values */ + ldr r1,=_sidata + ldr r2,=_sdata + ldr r3,=_edata + b cmpdata +CopyLoop: + ldr r0, [r1] + str r0, [r2] + adds r1, r1, #4 + adds r2, r2, #4 +cmpdata: + cmp r2, r3 + blt CopyLoop + + /* Clear BSS section */ + movs r0, #0 + ldr r2,=_sbss + ldr r3,=_ebss + b cmpbss +ClearLoop: + str r0, [r2] + adds r2, r2, #4 +cmpbss: + cmp r2, r3 + blt ClearLoop + + /* VENEER COPY */ + /* R0 = Start address, R1 = Destination address, R2 = Size */ + ldr r0, =VeneerLoadAddr + ldr r1, =VeneerStart + ldr r2, =VeneerSize + +STARTVENEERCOPY: + /* R2 contains byte count. Change it to word count. It is ensured in the + linker script that the length is always word aligned. + */ + lsrs r2,r2,#2 /* Divide by 4 to obtain word count */ + beq SKIPVENEERCOPY + + /* The proverbial loop from the schooldays */ +VENEERCOPYLOOP: + ldr r3,[R0] + str r3,[R1] + subs r2,#1 + beq SKIPVENEERCOPY + adds r0,#4 + adds r1,#4 + b VENEERCOPYLOOP + +SKIPVENEERCOPY: + /* Update System Clock */ + ldr r0,=SystemCoreClockUpdate + blx r0 + + /* Call static constructors */ + bl __libc_init_array + + /* Branch to main */ + bl main + + /* If main returns, branch to Default_Handler. */ + b Default_Handler + + .size Reset_Handler, .-Reset_Handler + +/** +**=========================================================================== +** Program - Default_Handler +** Abstract: This code gets called when the processor receives an +** unexpected interrupt. +**=========================================================================== +*/ + .section .text.Default_Handler,"ax", %progbits +Default_Handler: + b Default_Handler + + .size Default_Handler, .-Default_Handler + +/** +**=========================================================================== +** Interrupt vector table +**=========================================================================== +*/ + .section .isr_vector,"a", %progbits + .globl InterruptVector + .type InterruptVector, %object + +InterruptVector: + .word _estack /* 0 - Stack pointer */ + .word Reset_Handler /* 1 - Reset */ + .word NMI_Handler /* 2 - NMI */ + .word HardFault_Handler /* 3 - Hard fault */ + .word CLKVAL1_SSW /* Clock configuration value */ + .word CLKVAL2_SSW /* Clock gating configuration */ + + .size InterruptVector, . - InterruptVector + +/** +**=========================================================================== +** Weak interrupt handlers redirected to Default_Handler. These can be +** overridden in user code. +**=========================================================================== +*/ + .weak NMI_Handler + .thumb_set NMI_Handler, Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler, Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler, Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler, Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler, Default_Handler + +/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +/* IRQ Handlers */ + .weak SCU_0_IRQHandler + .type SCU_0_IRQHandler, %function +SCU_0_IRQHandler: + B . + .size SCU_0_IRQHandler, . - SCU_0_IRQHandler +/* ======================================================================== */ + .weak SCU_1_IRQHandler + .type SCU_1_IRQHandler, %function +SCU_1_IRQHandler: + B . + .size SCU_1_IRQHandler, . - SCU_1_IRQHandler +/* ======================================================================== */ + .weak SCU_2_IRQHandler + .type SCU_2_IRQHandler, %function +SCU_2_IRQHandler: + B . + .size SCU_2_IRQHandler, . - SCU_2_IRQHandler +/* ======================================================================== */ + .weak ERU0_0_IRQHandler + .type ERU0_0_IRQHandler, %function +ERU0_0_IRQHandler: + B . + .size ERU0_0_IRQHandler, . - ERU0_0_IRQHandler +/* ======================================================================== */ + .weak ERU0_1_IRQHandler + .type ERU0_1_IRQHandler, %function +ERU0_1_IRQHandler: + B . + .size ERU0_1_IRQHandler, . - ERU0_1_IRQHandler +/* ======================================================================== */ + .weak ERU0_2_IRQHandler + .type ERU0_2_IRQHandler, %function +ERU0_2_IRQHandler: + B . + .size ERU0_2_IRQHandler, . - ERU0_2_IRQHandler +/* ======================================================================== */ + .weak ERU0_3_IRQHandler + .type ERU0_3_IRQHandler, %function +ERU0_3_IRQHandler: + B . + .size ERU0_3_IRQHandler, . - ERU0_3_IRQHandler +/* ======================================================================== */ + .weak MATH0_0_IRQHandler + .type MATH0_0_IRQHandler, %function +MATH0_0_IRQHandler: + B . + .size MATH0_0_IRQHandler, . - MATH0_0_IRQHandler +/* ======================================================================== */ + .weak VADC0_C0_0_IRQHandler + .type VADC0_C0_0_IRQHandler , %function +VADC0_C0_0_IRQHandler: + B . + .size VADC0_C0_0_IRQHandler , . - VADC0_C0_0_IRQHandler +/* ======================================================================== */ + .weak VADC0_C0_1_IRQHandler + .type VADC0_C0_1_IRQHandler , %function +VADC0_C0_1_IRQHandler: + B . + .size VADC0_C0_1_IRQHandler , . - VADC0_C0_1_IRQHandler +/* ======================================================================== */ + .weak VADC0_G0_0_IRQHandler + .type VADC0_G0_0_IRQHandler, %function +VADC0_G0_0_IRQHandler: + B . + .size VADC0_G0_0_IRQHandler, . - VADC0_G0_0_IRQHandler +/* ======================================================================== */ + .weak VADC0_G0_1_IRQHandler + .type VADC0_G0_1_IRQHandler, %function +VADC0_G0_1_IRQHandler: + B . + .size VADC0_G0_1_IRQHandler, . - VADC0_G0_1_IRQHandler +/* ======================================================================== */ + .weak VADC0_G1_0_IRQHandler + .type VADC0_G1_0_IRQHandler, %function +VADC0_G1_0_IRQHandler: + B . + .size VADC0_G1_0_IRQHandler, . - VADC0_G1_0_IRQHandler +/* ======================================================================== */ + .weak VADC0_G1_1_IRQHandler + .type VADC0_G1_1_IRQHandler, %function +VADC0_G1_1_IRQHandler: + B . + .size VADC0_G1_1_IRQHandler, . - VADC0_G1_1_IRQHandler +/* ======================================================================== */ + .weak CCU40_0_IRQHandler + .type CCU40_0_IRQHandler, %function +CCU40_0_IRQHandler: + B . + .size CCU40_0_IRQHandler, . - CCU40_0_IRQHandler +/* ======================================================================== */ + .weak CCU40_1_IRQHandler + .type CCU40_1_IRQHandler, %function + +CCU40_1_IRQHandler: + B . + .size CCU40_1_IRQHandler, . - CCU40_1_IRQHandler +/* ======================================================================== */ + .weak CCU40_2_IRQHandler + .type CCU40_2_IRQHandler, %function +CCU40_2_IRQHandler: + B . + .size CCU40_2_IRQHandler, . - CCU40_2_IRQHandler +/* ======================================================================== */ + .weak CCU40_3_IRQHandler + .type CCU40_3_IRQHandler, %function +CCU40_3_IRQHandler: + B . + .size CCU40_3_IRQHandler, . - CCU40_3_IRQHandler +/* ======================================================================== */ + .weak CCU80_0_IRQHandler + .type CCU80_0_IRQHandler, %function +CCU80_0_IRQHandler: + B . + .size CCU80_0_IRQHandler, . - CCU80_0_IRQHandler +/* ======================================================================== */ + .weak CCU80_1_IRQHandler + .type CCU80_1_IRQHandler, %function +CCU80_1_IRQHandler: + B . + .size CCU80_1_IRQHandler, . - CCU80_1_IRQHandler +/* ======================================================================== */ + .weak POSIF0_0_IRQHandler + .type POSIF0_0_IRQHandler, %function + +POSIF0_0_IRQHandler: + B . + .size POSIF0_0_IRQHandler, . - POSIF0_0_IRQHandler +/* ======================================================================== */ + .weak POSIF0_1_IRQHandler + .type POSIF0_1_IRQHandler, %function +POSIF0_1_IRQHandler: + B . + .size POSIF0_1_IRQHandler, . - POSIF0_1_IRQHandler +/* ======================================================================== */ + .weak USIC0_0_IRQHandler + .type USIC0_0_IRQHandler, %function +USIC0_0_IRQHandler: + B . + .size USIC0_0_IRQHandler, . - USIC0_0_IRQHandler +/* ======================================================================== */ + .weak USIC0_1_IRQHandler + .type USIC0_1_IRQHandler, %function +USIC0_1_IRQHandler: + B . + .size USIC0_1_IRQHandler, . - USIC0_1_IRQHandler +/* ======================================================================== */ + .weak USIC0_2_IRQHandler + .type USIC0_2_IRQHandler, %function +USIC0_2_IRQHandler: + B . + .size USIC0_2_IRQHandler, . - USIC0_2_IRQHandler +/* ======================================================================== */ + .weak USIC0_3_IRQHandler + .type USIC0_3_IRQHandler, %function +USIC0_3_IRQHandler: + B . + .size USIC0_3_IRQHandler, . - USIC0_3_IRQHandler +/* ======================================================================== */ + .weak USIC0_4_IRQHandler + .type USIC0_4_IRQHandler, %function +USIC0_4_IRQHandler: + B . + .size USIC0_4_IRQHandler, . - USIC0_4_IRQHandler +/* ======================================================================== */ + .weak USIC0_5_IRQHandler + .type USIC0_5_IRQHandler, %function +USIC0_5_IRQHandler: + B . + .size USIC0_5_IRQHandler, . - USIC0_5_IRQHandler +/* ======================================================================== */ + .weak LEDTS0_0_IRQHandler + .type LEDTS0_0_IRQHandler, %function +LEDTS0_0_IRQHandler: + B . + .size LEDTS0_0_IRQHandler, . - LEDTS0_0_IRQHandler +/* ======================================================================== */ + .weak LEDTS1_0_IRQHandler + .type LEDTS1_0_IRQHandler, %function +LEDTS1_0_IRQHandler: + B . + .size LEDTS1_0_IRQHandler, . - LEDTS1_0_IRQHandler +/* ======================================================================== */ + .weak BCCU0_0_IRQHandler + .type BCCU0_0_IRQHandler, %function +BCCU0_0_IRQHandler: + B . + .size BCCU0_0_IRQHandler, . - BCCU0_0_IRQHandler +/* ======================================================================== */ +/* ======================================================================== */ + +/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */ + .section ".XmcVeneerCode","ax",%progbits +.globl HardFault_Veneer +HardFault_Veneer: + LDR R0, =HardFault_Handler + MOV PC,R0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + +/* ======================================================================== */ +.globl SVC_Veneer +SVC_Veneer: + LDR R0, =SVC_Handler + MOV PC,R0 + .long 0 + .long 0 +/* ======================================================================== */ +.globl PendSV_Veneer +PendSV_Veneer: + LDR R0, =PendSV_Handler + MOV PC,R0 +/* ======================================================================== */ +.globl SysTick_Veneer +SysTick_Veneer: + LDR R0, =SysTick_Handler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_0_Veneer +SCU_0_Veneer: + LDR R0, =SCU_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_1_Veneer +SCU_1_Veneer: + LDR R0, =SCU_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_2_Veneer +SCU_2_Veneer: + LDR R0, =SCU_2_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_3_Veneer +SCU_3_Veneer: + LDR R0, =ERU0_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_4_Veneer +SCU_4_Veneer: + LDR R0, =ERU0_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_5_Veneer +SCU_5_Veneer: + LDR R0, =ERU0_2_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_6_Veneer +SCU_6_Veneer: + LDR R0, =ERU0_3_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl SCU_7_Veneer +SCU_7_Veneer: + LDR R0, =MATH0_0_IRQHandler + MOV PC,R0 + .long 0 +/* ======================================================================== */ +.globl VADC0_C0_0_Veneer +VADC0_C0_0_Veneer: + LDR R0, =VADC0_C0_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl VADC0_C0_1_Veneer +VADC0_C0_1_Veneer: + LDR R0, =VADC0_C0_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl VADC0_G0_0_Veneer +VADC0_G0_0_Veneer: + LDR R0, =VADC0_G0_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl VADC0_G0_1_Veneer +VADC0_G0_1_Veneer: + LDR R0, =VADC0_G0_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl VADC0_G1_0_Veneer +VADC0_G1_0_Veneer: + LDR R0, =VADC0_G1_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl VADC0_G1_1_Veneer +VADC0_G1_1_Veneer: + LDR R0, =VADC0_G1_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl CCU40_0_Veneer +CCU40_0_Veneer: + LDR R0, =CCU40_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl CCU40_1_Veneer +CCU40_1_Veneer: + LDR R0, =CCU40_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl CCU40_2_Veneer +CCU40_2_Veneer: + LDR R0, =CCU40_2_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl CCU40_3_Veneer +CCU40_3_Veneer: + LDR R0, =CCU40_3_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl CCU80_0_Veneer +CCU80_0_Veneer: + LDR R0, =CCU80_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl CCU80_1_Veneer +CCU80_1_Veneer: + LDR R0, =CCU80_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl POSIF0_0_Veneer +POSIF0_0_Veneer: + LDR R0, =POSIF0_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl POSIF0_1_Veneer +POSIF0_1_Veneer: + LDR R0, =POSIF0_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl USIC0_0_Veneer +USIC0_0_Veneer: + LDR R0, =USIC0_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl USIC0_1_Veneer +USIC0_1_Veneer: + LDR R0, =USIC0_1_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl USIC0_2_Veneer +USIC0_2_Veneer: + LDR R0, =USIC0_2_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl USIC0_3_Veneer +USIC0_3_Veneer: + LDR R0, =USIC0_3_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl USIC0_4_Veneer +USIC0_4_Veneer: + LDR R0, =USIC0_4_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl USIC0_5_Veneer +USIC0_5_Veneer: + LDR R0, =USIC0_5_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl LEDTS0_0_Veneer +LEDTS0_0_Veneer: + LDR R0, =LEDTS0_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ +.globl LEDTS1_0_Veneer +LEDTS1_0_Veneer: + LDR R0, =LEDTS1_0_IRQHandler + MOV PC,R0 +/* ======================================================================== */ + .globl BCCU0_0_Veneer +BCCU0_0_Veneer: + LDR R0, =BCCU0_0_IRQHandler + MOV PC,R0 + +/* ======================================================================== */ + +/* ===== Decision function queried by CMSIS startup for Clock tree setup === */ +/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock + tree setup. + + This decision routine defined here will always return TRUE. + + When overridden by a definition defined in DAVE code engine, this routine + returns FALSE indicating that the code engine has performed the clock setup +*/ + .section ".XmcStartup" + .weak AllowClkInitByStartup + .type AllowClkInitByStartup, %function +AllowClkInitByStartup: + MOVS R0,#1 + BX LR + .size AllowClkInitByStartup, . - AllowClkInitByStartup + +/* ====== Definition of the default weak SystemInit_DAVE3 function ========= +If DAVE3 requires an extended SystemInit it will create its own version of +SystemInit_DAVE3 which overrides this weak definition. Example includes +setting up of external memory interfaces. +*/ + .weak SystemInit_DAVE3 + .type SystemInit_DAVE3, %function +SystemInit_DAVE3: + NOP + BX LR + .size SystemInit_DAVE3, . - SystemInit_DAVE3 + + .end diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/xmc1000_flash.ld b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/xmc1000_flash.ld new file mode 100644 index 000000000..4c3bb4c35 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Atollic_Specific/xmc1000_flash.ld @@ -0,0 +1,190 @@ +/* +***************************************************************************** +** +** File : xmc1000_flash.ld +** +** Abstract : Linker script for XMC1200-T038F0200 Device with +** 200KByte FLASH, 16KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Target : Infineon XMC1000 Microcontrollers +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. This file may only be built (assembled or compiled and linked) +** using the Atollic TrueSTUDIO(R) product. The use of this file together +** with other tools than Atollic TrueSTUDIO(R) is not permitted. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20004000; /* end of 16K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x80; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x10001000, LENGTH = 200K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.XmcStartup); + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + . = ALIGN(4); + eROData = . ; + + /* Initialize XMC Veneer interrupt code */ + VeneerLoadAddr = ABSOLUTE(eROData); + .VENEER_Code ABSOLUTE(0x2000000C) : + { + VeneerStart = .; + KEEP(*(.XmcVeneerCode)) /* Keep the VeneerCode */ + *(.XmcVeneerCode); + . = ALIGN(4); + VeneerEnd = .; + + } >RAM AT> FLASH + + VeneerSize = ABSOLUTE(VeneerEnd) - ABSOLUTE(VeneerStart); + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/core_cm0.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cm0.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/core_cm0.h rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cm0.h diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmFunc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/core_cmFunc.h rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmFunc.h diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmInstr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/core_cmInstr.h rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/CMSIS/core_cmInstr.h diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RegTest_IAR.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/RegTest_IAR.s similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RegTest_IAR.s rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/RegTest_IAR.s diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/startup_XMC1200.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/startup_XMC1200.s similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_IAR/startup_XMC1200.s rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/IAR_Specific/startup_XMC1200.s diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/JLinkSettings.ini new file mode 100644 index 000000000..de1b137f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/JLinkSettings.ini @@ -0,0 +1,34 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RegTest_Keil.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/RegTest_Keil.s similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RegTest_Keil.s rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/RegTest_Keil.s diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/startup_XMC1300.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/startup_XMC1300.s similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/startup_XMC1300.s rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/startup_XMC1300.s diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1100.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1100.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1100.c rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1100.c diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1200.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1200.c rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1200.c diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1300.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1300.c rename to FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Keil_Specific/system_XMC1300.c diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp index 98ac9510e..29cfce81e 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.ewp @@ -297,12 +297,11 @@