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Update the GCC RL78 demo to include four separate build configurations, each of which targets different hardware.

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This commit is contained in:
Richard Barry 2013-03-19 12:24:05 +00:00
parent 3a1a500950
commit 236683d74d
24 changed files with 4493 additions and 725 deletions
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199
FreeRTOS/Demo/RL78_E2Studio_GCC/src/vector_table.c
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@ -6,16 +6,21 @@
/* CPU SERIES : RL78 - G14 */
/* CPU TYPE : R5F104PJ */
/* */
/* This file is generated by e2studio. */
/* This file is generated by e2studio. */
/* */
/***********************************************************************/
#include "interrupt_handlers.h"
#include "FreeRTOS.h"
extern void PowerON_Reset( void );
extern void vPortTickISR( void );
extern void vPortYield( void );
void Dummy_Handler( void ) __attribute__((interrupt));
void Dummy_Handler( void )
{
}
const unsigned char Option_Bytes[] __attribute__ ((section (".option_bytes"))) = {
0x6e, 0xff, 0xe8, 0x85
};
@ -32,102 +37,110 @@ const void *HardwareVectors[] VEC = {
#define VECT_SECT __attribute__ ((section (".vects")))
const void *Vectors[] VECT_SECT = {
//INT_SRO/INT_WDTI (0x4)
INT_WDTI,
//INT_LVI (0x6)
INT_LVI,
//INT_P0 (0x8)
INT_P0,
//INT_P1 (0xA)
INT_P1,
//INT_P2 (0xC)
INT_P2,
//INT_P3 (0xE)
INT_P3,
//INT_P4 (0x10)
INT_P4,
//INT_P5 (0x12)
INT_P5,
//INT_CSI20/INT_IIC20/INT_ST2 (0x14)
INT_ST2,
//INT_CSI21/INT_IIC21/INT_SR2 (0x16)
INT_SR2,
//INT_SRE2/INT_TM11H (0x18)
INT_TM11H,
//(0x4)
Dummy_Handler,
//(0x6)
Dummy_Handler,
//(0x8)
Dummy_Handler,
//(0xA)
Dummy_Handler,
//(0xC)
Dummy_Handler,
//(0xE)
Dummy_Handler,
//(0x10)
Dummy_Handler,
//(0x12)
Dummy_Handler,
//(0x14)
Dummy_Handler,
//(0x16)
Dummy_Handler,
//(0x18)
Dummy_Handler,
// Padding
(void*)0xFFFF,
// Padding
(void*)0xFFFF,
//INT_CSI00/INT_IIC00/INT_ST0 (0x1E)
INT_ST0,
//INT_CSI01/INT_IIC01/INT_SR0 (0x20)
INT_SR0,
//INT_SRE0/INT_TM01H (0x22)
INT_TM01H,
//INT_CSI10/INT_IIC10/INT_ST1 (0x24)
INT_ST1,
//INT_CSI11/INT_IIC11/INT_SR1 (0x26)
INT_SR1,
//INT_SRE1/INT_TM03H (0x28)
INT_TM03H,
//INT_IICA0 (0x2A)
INT_IICA0,
//INT_TM00 (0x2C)
INT_TM00,
//INT_TM01 (0x2E)
INT_TM01,
//INT_TM02 (0x30)
INT_TM02,
//INT_TM03 (0x32)
INT_TM03,
//INT_AD (0x34)
INT_AD,
//INT_RTC (0x36)
INT_RTC,
//INT_IT (0x38)
vPortTickISR,
//INT_KR (0x3A)
INT_KR,
//INT_CSI30/INT_IIC30/INT_ST3 (0x3C)
INT_ST3,
//INT_CSI31/INT_IIC31/INT_SR3 (0x3E)
INT_SR3,
//INT_TRJ0 (0x40)
INT_TRJ0,
//INT_TM10 (0x42)
INT_TM10,
//INT_TM11 (0x44)
INT_TM11,
//INT_TM12 (0x46)
INT_TM12,
//INT_TM13 (0x48)
INT_TM13,
//INT_P6 (0x4A)
INT_P6,
//INT_P7 (0x4C)
INT_P7,
//INT_P8 (0x4E)
INT_P8,
//INT_P9 (0x50)
INT_P9,
//INT_CMP0/INT_P10 (0x52)
INT_P10,
//INT_CMP1/INT_P11 (0x54)
INT_P11,
//INT_TRD0 (0x56)
INT_TRD0,
//INT_TRD1 (0x58)
INT_TRD1,
//INT_TRG (0x5A)
INT_TRG,
//INT_SRE3/INT_TM13H (0x5C)
INT_TM13H,
//(0x1E)
Dummy_Handler,
//(0x20)
Dummy_Handler,
//(0x22)
Dummy_Handler,
//(0x24)
Dummy_Handler,
//(0x26)
Dummy_Handler,
//(0x28)
Dummy_Handler,
//(0x2A)
Dummy_Handler,
//(0x2C)
Dummy_Handler,
//(0x2E)
Dummy_Handler,
//(0x30)
Dummy_Handler,
//(0x32)
Dummy_Handler,
//(0x34)
Dummy_Handler,
//(0x36)
Dummy_Handler,
//(0x38)
#if INTIT_vect == 0x38
vPortTickISR, /* Note this vector table definition is used with lots of RL78 chips, some of which have the INTIT vector here. */
#else
Dummy_Handler,
#endif
//(0x3A)
Dummy_Handler,
//(0x3C)
#if INTIT_vect == 0x3C
vPortTickISR, /* Note this vector table definition is used with lots of RL78 chips, some of which have the INTIT vector here. */
#else
Dummy_Handler,
#endif
//(0x3E)
Dummy_Handler,
//(0x40)
Dummy_Handler,
//(0x42)
Dummy_Handler,
//(0x44)
Dummy_Handler,
//(0x46)
Dummy_Handler,
//(0x48)
Dummy_Handler,
//(0x4A)
Dummy_Handler,
//(0x4C)
Dummy_Handler,
//(0x4E)
Dummy_Handler,
//(0x50)
Dummy_Handler,
//(0x52)
Dummy_Handler,
//(0x54)
Dummy_Handler,
//(0x56)
Dummy_Handler,
//(0x58)
Dummy_Handler,
//(0x5A)
Dummy_Handler,
//(0x5C)
Dummy_Handler,
// Padding
(void*)0xFFFF,
//INT_IICA1 (0x60)
INT_IICA1,
//INT_FL (0x62)
INT_FL,
//(0x60)
Dummy_Handler,
//(0x62)
Dummy_Handler,
// Padding
(void*)0xFFFF,
// Padding