diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject
index 19414c5c2..fd7ef95e1 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject
@@ -41,7 +41,7 @@
-
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@@ -87,7 +87,7 @@
-
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@@ -99,7 +99,13 @@
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@@ -221,6 +227,96 @@
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diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.project b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.project
index 7e67e3c94..0e8872a4d 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.project
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.project
@@ -214,6 +214,15 @@
1.0-name-matches-false-false-heap_4.c
+
+ 1545005412575
+ FreeRTOS_Source/portable/GCC/RISC-V-RV32
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-CLINT_no_extensions
+
+
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml
index 69a0ac05b..f0af7e9d4 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml
@@ -11,7 +11,7 @@
-
+
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h
index 8dbf46cd4..08df67e18 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h
@@ -90,12 +90,12 @@
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
-#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ ) )
-//#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ / 100 ) ) /*_RB_ Seems to be a factor of 100 between machine timer frequency and CPU frequency. */
+//#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ ) )
+#define configCPU_CLOCK_HZ ( ( unsigned long ) ( SYS_CLK_FREQ / 100 ) ) /*_RB_ Seems to be a factor of 100 between machine timer frequency and CPU frequency. */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 5 )
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 300 * 1024 ) )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 150 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 280 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
@@ -145,7 +145,5 @@ header file. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define handle_m_ext_interrupt vPortHandleInterrupt
-
#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S
index 1a657feb4..fce18d785 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/entry.S
@@ -24,7 +24,7 @@
#endif
.section .text.entry
- .extern vPortTrapHandler
+ .extern vFreeRTOSPortTrapHandler
.globl _start
_start:
@@ -34,10 +34,10 @@ nmi_vector:
j nmi_vector
trap_vector:
- j vPortTrapHandler
+ j vFreeRTOSPortTrapHandler
handle_reset:
- la t0, vPortTrapHandler
+ la t0, vFreeRTOSPortTrapHandler
csrw mtvec, t0
csrwi mstatus, 0
csrwi mie, 0
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/README.md b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/README.md
deleted file mode 100644
index 211d2466d..000000000
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/README.md
+++ /dev/null
@@ -1,48 +0,0 @@
-## FreeRTOS port for Mi-V Soft Processor
-
-### HW Platform and FPGA design:
-This project is tested on following hardware platforms:
-
-RISCV-Creative-Board
-- [RISC-V Creative board Mi-V Sample Design](https://github.com/RISCV-on-Microsemi-FPGA/RISC-V-Creative-Board/tree/master/Programming_The_Target_Device/PROC_SUBSYSTEM_MIV_RV32IMA_BaseDesign)
-
-PolarFire-Eval-Kit
-- [PolarFire Eval Kit RISC-V Sample Design](https://github.com/RISCV-on-Microsemi-FPGA/PolarFire-Eval-Kit/tree/master/Programming_The_Target_Device/MIV_RV32IMA_L1_AHB_BaseDesign)
-
-SmartFusion2-Advanced-Dev-Kit
-- [SmartFusion2 Advanced Development Kit RISC-V Sample Design](https://github.com/RISCV-on-Microsemi-FPGA/SmartFusion2-Advanced-Dev-Kit/tree/master/Programming_The_Target_Device/PROC_SUBSYSTEM_BaseDesign)
-
-### How to run the FreeRTOS RISC-V port:
-To know how to use the SoftConsole workspace, please refer the [Readme.md](https://github.com/RISCV-on-Microsemi-FPGA/SoftConsole/blob/master/README.md)
-
-The miv-rv32im-freertos-port-test is a self contained project. This project demonstrates
-the FreeRTOS running with Microsemi RISC-V processor. This project creates two
-tasks and runs them at regular intervals.
-
-This example project requires USB-UART interface to be connected to a host PC.
-The host PC must connect to the serial port using a terminal emulator such as
-TeraTerm or PuTTY configured as follows:
-
- - 115200 baud
- - 8 data bits
- - 1 stop bit
- - no parity
- - no flow control
-
-The ./hw_platform.h file contains the design related information that is required
-for this project. If you update the design, the hw_platform.h must be updated
-accordingly.
-
-### FreeRTOS Configurations
-You must configure the FreeRTOS as per your applications need. Please read and modify FreeRTOSConfig.h.
-E.g. You must set configCPU_CLOCK_HZ parameter in FreeRTOSConfig.h according to the hardware platform
-design that you are using.
-
-The RISC-V creative board design uses 66Mhz processor clock. The PolarFire Eval Kit design uses 50Mhz processor clock. The SmartFusion2 Adv. Development kit design uses 83Mhz processor clock.
-
-### Microsemi SoftConsole Toolchain
-To know more please refer: [SoftConsole](https://github.com/RISCV-on-Microsemi-FPGA/SoftConsole)
-
-### Documentation for Microsemi RISC-V processor, SoftConsole toochain, Debug Tools, FPGA design etc.
-To know more please refer: [Documentation](https://github.com/RISCV-on-Microsemi-FPGA/Documentation)
-
diff --git a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/RTOSDemo Debug Hardware.launch b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/RTOSDemo Debug Hardware.launch
index 3669d25a7..64767a502 100644
--- a/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/RTOSDemo Debug Hardware.launch
+++ b/FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/RTOSDemo Debug Hardware.launch
@@ -10,7 +10,7 @@
-
+