len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-20 10:08:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

Re-sync with upstream and stripping away none kernel related.

Browse source
This commit is contained in:
Yuhui Zheng 2020-02-10 13:45:57 -08:00
parent 9c0c37ab9b
commit 210b1ffcc8
13732 changed files with 49 additions and 7054697 deletions
Download patch file Download diff file Expand all files Collapse all files

432
portable/MPLAB/PIC32MZ/ISR_Support.h Normal file
View file

@ -0,0 +1,432 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include "FreeRTOSConfig.h"
#define portCONTEXT_SIZE 160
#define portEPC_STACK_LOCATION 152
#define portSTATUS_STACK_LOCATION 156
#define portFPCSR_STACK_LOCATION 0
#define portTASK_HAS_FPU_STACK_LOCATION 0
#define portFPU_CONTEXT_SIZE 264
/******************************************************************/
.macro portSAVE_FPU_REGS offset, base
/* Macro to assist with saving just the FPU registers to the
* specified address and base offset,
* offset is a constant, base is the base pointer register */
sdc1 $f31, \offset + 248(\base)
sdc1 $f30, \offset + 240(\base)
sdc1 $f29, \offset + 232(\base)
sdc1 $f28, \offset + 224(\base)
sdc1 $f27, \offset + 216(\base)
sdc1 $f26, \offset + 208(\base)
sdc1 $f25, \offset + 200(\base)
sdc1 $f24, \offset + 192(\base)
sdc1 $f23, \offset + 184(\base)
sdc1 $f22, \offset + 176(\base)
sdc1 $f21, \offset + 168(\base)
sdc1 $f20, \offset + 160(\base)
sdc1 $f19, \offset + 152(\base)
sdc1 $f18, \offset + 144(\base)
sdc1 $f17, \offset + 136(\base)
sdc1 $f16, \offset + 128(\base)
sdc1 $f15, \offset + 120(\base)
sdc1 $f14, \offset + 112(\base)
sdc1 $f13, \offset + 104(\base)
sdc1 $f12, \offset + 96(\base)
sdc1 $f11, \offset + 88(\base)
sdc1 $f10, \offset + 80(\base)
sdc1 $f9, \offset + 72(\base)
sdc1 $f8, \offset + 64(\base)
sdc1 $f7, \offset + 56(\base)
sdc1 $f6, \offset + 48(\base)
sdc1 $f5, \offset + 40(\base)
sdc1 $f4, \offset + 32(\base)
sdc1 $f3, \offset + 24(\base)
sdc1 $f2, \offset + 16(\base)
sdc1 $f1, \offset + 8(\base)
sdc1 $f0, \offset + 0(\base)
.endm
/******************************************************************/
.macro portLOAD_FPU_REGS offset, base
/* Macro to assist with loading just the FPU registers from the
* specified address and base offset, offset is a constant,
* base is the base pointer register */
ldc1 $f0, \offset + 0(\base)
ldc1 $f1, \offset + 8(\base)
ldc1 $f2, \offset + 16(\base)
ldc1 $f3, \offset + 24(\base)
ldc1 $f4, \offset + 32(\base)
ldc1 $f5, \offset + 40(\base)
ldc1 $f6, \offset + 48(\base)
ldc1 $f7, \offset + 56(\base)
ldc1 $f8, \offset + 64(\base)
ldc1 $f9, \offset + 72(\base)
ldc1 $f10, \offset + 80(\base)
ldc1 $f11, \offset + 88(\base)
ldc1 $f12, \offset + 96(\base)
ldc1 $f13, \offset + 104(\base)
ldc1 $f14, \offset + 112(\base)
ldc1 $f15, \offset + 120(\base)
ldc1 $f16, \offset + 128(\base)
ldc1 $f17, \offset + 136(\base)
ldc1 $f18, \offset + 144(\base)
ldc1 $f19, \offset + 152(\base)
ldc1 $f20, \offset + 160(\base)
ldc1 $f21, \offset + 168(\base)
ldc1 $f22, \offset + 176(\base)
ldc1 $f23, \offset + 184(\base)
ldc1 $f24, \offset + 192(\base)
ldc1 $f25, \offset + 200(\base)
ldc1 $f26, \offset + 208(\base)
ldc1 $f27, \offset + 216(\base)
ldc1 $f28, \offset + 224(\base)
ldc1 $f29, \offset + 232(\base)
ldc1 $f30, \offset + 240(\base)
ldc1 $f31, \offset + 248(\base)
.endm
/******************************************************************/
.macro portSAVE_CONTEXT
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so their original values are
captured. */
mfc0 k0, _CP0_CAUSE
addiu sp, sp, -portCONTEXT_SIZE
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/* Test if we are already using the system stack. Only tasks may use the
FPU so if we are already in a nested interrupt then the FPU context does
not require saving. */
la k1, uxInterruptNesting
lw k1, 0(k1)
bne k1, zero, 2f
nop
/* Test if the current task needs the FPU context saving. */
la k1, ulTaskHasFPUContext
lw k1, 0(k1)
beq k1, zero, 1f
nop
/* Adjust the stack to account for the additional FPU context.*/
addiu sp, sp, -portFPU_CONTEXT_SIZE
1:
/* Save the ulTaskHasFPUContext flag. */
sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
2:
#endif
mfc0 k1, _CP0_STATUS
/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
should maintain the values of these registers across the ISR. */
sw s7, 48(sp)
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Prepare to enable interrupts above the current priority. */
srl k0, k0, 0xa
ins k1, k0, 10, 7
srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
ins k1, k0, 18, 1
ins k1, zero, 1, 4
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Check the nesting count value. */
la k0, uxInterruptNesting
lw s6, (k0)
/* If the nesting count is 0 then swap to the the system stack, otherwise
the system stack is already being used. */
bne s6, zero, 1f
nop
/* Swap to the system stack. */
la sp, xISRStackTop
lw sp, (sp)
/* Increment and save the nesting count. */
1: addiu s6, s6, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. No other s registers need be
saved. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s6, portEPC_STACK_LOCATION(s5)
sw $1, 16(s5)
/* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
scratch register. */
mfhi s6, $ac1
sw s6, 128(s5)
mflo s6, $ac1
sw s6, 124(s5)
mfhi s6, $ac2
sw s6, 136(s5)
mflo s6, $ac2
sw s6, 132(s5)
mfhi s6, $ac3
sw s6, 144(s5)
mflo s6, $ac3
sw s6, 140(s5)
/* Save the DSP Control register */
rddsp s6
sw s6, 148(s5)
/* ac0 is done separately to match the MX port. */
mfhi s6, $ac0
sw s6, 12(s5)
mflo s6, $ac0
sw s6, 8(s5)
/* Save the FPU context if the nesting count was zero. */
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
la s6, uxInterruptNesting
lw s6, 0(s6)
addiu s6, s6, -1
bne s6, zero, 1f
nop
/* Test if the current task needs the FPU context saving. */
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
beq s6, zero, 1f
nop
/* Save the FPU registers. */
portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
/* Save the FPU status register */
cfc1 s6, $f31
sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
1:
#endif
/* Update the task stack pointer value if nesting is zero. */
la s6, uxInterruptNesting
lw s6, (s6)
addiu s6, s6, -1
bne s6, zero, 1f
nop
/* Save the stack pointer. */
la s6, uxSavedTaskStackPointer
sw s5, (s6)
1:
.endm
/******************************************************************/
.macro portRESTORE_CONTEXT
/* Restore the stack pointer from the TCB. This is only done if the
nesting count is 1. */
la s6, uxInterruptNesting
lw s6, (s6)
addiu s6, s6, -1
bne s6, zero, 1f
nop
la s6, uxSavedTaskStackPointer
lw s5, (s6)
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/* Restore the FPU context if required. */
lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
beq s6, zero, 1f
nop
/* Restore the FPU registers. */
portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
/* Restore the FPU status register. */
lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
ctc1 s6, $f31
#endif
1:
/* Restore the context. */
lw s6, 128(s5)
mthi s6, $ac1
lw s6, 124(s5)
mtlo s6, $ac1
lw s6, 136(s5)
mthi s6, $ac2
lw s6, 132(s5)
mtlo s6, $ac2
lw s6, 144(s5)
mthi s6, $ac3
lw s6, 140(s5)
mtlo s6, $ac3
/* Restore DSPControl. */
lw s6, 148(s5)
wrdsp s6
lw s6, 8(s5)
mtlo s6, $ac0
lw s6, 12(s5)
mthi s6, $ac0
lw $1, 16(s5)
/* s6 is loaded as it was used as a scratch register and therefore saved
as part of the interrupt context. */
lw s7, 48(s5)
lw s6, 44(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Decrement the nesting count. */
la k0, uxInterruptNesting
lw k1, (k0)
addiu k1, k1, -1
sw k1, 0(k0)
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/* If the nesting count is now zero then the FPU context may be restored. */
bne k1, zero, 1f
nop
/* Restore the value of ulTaskHasFPUContext */
la k0, ulTaskHasFPUContext
lw k1, 0(s5)
sw k1, 0(k0)
/* If the task does not have an FPU context then adjust the stack normally. */
beq k1, zero, 1f
nop
/* Restore the STATUS and EPC registers */
lw k0, portSTATUS_STACK_LOCATION(s5)
lw k1, portEPC_STACK_LOCATION(s5)
/* Leave the stack in its original state. First load sp from s5, then
restore s5 from the stack. */
add sp, zero, s5
lw s5, 40(sp)
/* Adjust the stack pointer to remove the FPU context */
addiu sp, sp, portFPU_CONTEXT_SIZE
beq zero, zero, 2f
nop
1: /* Restore the STATUS and EPC registers */
lw k0, portSTATUS_STACK_LOCATION(s5)
lw k1, portEPC_STACK_LOCATION(s5)
/* Leave the stack in its original state. First load sp from s5, then
restore s5 from the stack. */
add sp, zero, s5
lw s5, 40(sp)
2: /* Adjust the stack pointer */
addiu sp, sp, portCONTEXT_SIZE
#else
/* Restore the frame when there is no hardware FP support. */
lw k0, portSTATUS_STACK_LOCATION(s5)
lw k1, portEPC_STACK_LOCATION(s5)
/* Leave the stack in its original state. First load sp from s5, then
restore s5 from the stack. */
add sp, zero, s5
lw s5, 40(sp)
addiu sp, sp, portCONTEXT_SIZE
#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
mtc0 k0, _CP0_STATUS
mtc0 k1, _CP0_EPC
ehb
eret
nop
.endm

372
portable/MPLAB/PIC32MZ/port.c Normal file
View file

@ -0,0 +1,372 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the PIC32MZ port.
*----------------------------------------------------------*/
/* Microchip specific headers. */
#include <xc.h>
/* Standard headers. */
#include <string.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#if !defined(__PIC32MZ__)
#error This port is designed to work with XC32 on PIC32MZ MCUs. Please update your C compiler version or settings.
#endif
#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
#endif
/* Hardware specifics. */
#define portTIMER_PRESCALE 8
#define portPRESCALE_BITS 1
/* Bits within various registers. */
#define portIE_BIT ( 0x00000001 )
#define portEXL_BIT ( 0x00000002 )
#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */
#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */
#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */
/* Bits within the CAUSE register. */
#define portCORE_SW_0 ( 0x00000100 )
#define portCORE_SW_1 ( 0x00000200 )
/* The EXL bit is set to ensure interrupts do not occur while the context of
the first task is being restored. */
#if ( __mips_hard_float == 1 )
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
#else
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT )
#endif
/* The initial value to store into the FPU status and control register. This is
only used on parts that support a hardware FPU. */
#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */
/*
By default port.c generates its tick interrupt from TIMER1. The user can
override this behaviour by:
1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
which is the function that configures the timer. The function is defined
as a weak symbol in this file so if the same function name is used in the
application code then the version in the application code will be linked
into the application in preference to the version defined in this file.
2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
to generate the tick interrupt. For example, when timer 1 is used then
configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
timer used to generate the tick interrupt. For example, when timer 1 is
used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
IFS0CLR = _IFS0_T1IF_MASK.
*/
#ifndef configTICK_INTERRUPT_VECTOR
#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
#else
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
#endif
#endif
/* Let the user override the pre-loading of the initial RA with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
stack checking. A problem in the ISR stack will trigger an assert, not call the
stack overflow hook function (because the stack overflow hook is specific to a
task stack, not the ISR stack). */
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
the task stacks, and so will legitimately appear in many positions within
the ISR stack. */
#define portISR_STACK_FILL_BYTE 0xee
static const uint8_t ucExpectedStackBytes[] = {
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
#else
/* Define the function away. */
#define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/*-----------------------------------------------------------*/
/*
* Used to catch tasks that attempt to return from their implementing function.
*/
static void prvTaskExitError( void );
/*-----------------------------------------------------------*/
/* Records the interrupt nesting depth. This is initialised to one as it is
decremented to 0 when the first task starts. */
volatile UBaseType_t uxInterruptNesting = 0x01;
/* Stores the task stack pointer when a switch is made to use the system stack. */
UBaseType_t uxSavedTaskStackPointer = 0;
/* The stack used by interrupt service routines that cause a context switch. */
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
the callers stack, as some functions seem to want to do this. 8 byte alignment
is required to allow double word floating point stack pushes generated by the
compiler. */
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
/* Saved as part of the task context. Set to pdFALSE if the task does not
require an FPU context. */
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
uint32_t ulTaskHasFPUContext = 0;
#endif
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
/* Ensure 8 byte alignment is maintained when leaving this function. */
pxTopOfStack--;
pxTopOfStack--;
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
pxTopOfStack--;
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
pxTopOfStack--;
*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
pxTopOfStack--;
*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
pxTopOfStack--;
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
pxTopOfStack--;
*pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */
pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
pxTopOfStack -= 15;
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
pxTopOfStack -= 15;
*pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxSavedTaskStackPointer == 0UL );
portDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
/*
* Setup a timer for a regular tick. This function uses peripheral timer 1.
* The function is declared weak so an application writer can use a different
* timer by redefining this implementation. If a different timer is used then
* configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
* ensure the RTOS provided tick interrupt handler is installed on the correct
* vector number. When Timer 1 is used the vector number is defined as
* _TIMER_1_VECTOR.
*/
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
{
const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
T1CON = 0x0000;
T1CONbits.TCKPS = portPRESCALE_BITS;
PR1 = ulCompareMatch;
IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
/* Clear the interrupt as a starting condition. */
IFS0bits.T1IF = 0;
/* Enable the interrupt. */
IEC0bits.T1IE = 1;
/* Start the timer. */
T1CONbits.TON = 1;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler(void)
{
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
configASSERT( uxInterruptNesting == 1000UL );
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
extern void *pxCurrentTCB;
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
{
/* Fill the ISR stack to make it easy to asses how much is being used. */
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
}
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/* Clear the software interrupt flag. */
IFS0CLR = _IFS0_CS0IF_MASK;
/* Set software timer priority. */
IPC0CLR = _IPC0_CS0IP_MASK;
IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
/* Enable software interrupt. */
IEC0CLR = _IEC0_CS0IE_MASK;
IEC0SET = 1 << _IEC0_CS0IE_POSITION;
/* Setup the timer to generate the tick. Interrupts will have been
disabled by the time we get here. */
vApplicationSetupTickTimerInterrupt();
/* Kick off the highest priority task that has been created so far.
Its stack location is loaded into uxSavedTaskStackPointer. */
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
vPortStartFirstTask();
/* Should never get here as the tasks will now be executing! Call the task
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. */
prvTaskExitError();
return pdFALSE;
}
/*-----------------------------------------------------------*/
void vPortIncrementTick( void )
{
UBaseType_t uxSavedStatus;
uxSavedStatus = uxPortSetInterruptMaskFromISR();
{
if( xTaskIncrementTick() != pdFALSE )
{
/* Pend a context switch. */
_CP0_BIS_CAUSE( portCORE_SW_0 );
}
}
vPortClearInterruptMaskFromISR( uxSavedStatus );
/* Look for the ISR stack getting near or past its limit. */
portCHECK_ISR_STACK();
/* Clear timer interrupt. */
configCLEAR_TICK_TIMER_INTERRUPT();
}
/*-----------------------------------------------------------*/
UBaseType_t uxPortSetInterruptMaskFromISR( void )
{
UBaseType_t uxSavedStatusRegister;
__builtin_disable_interrupts();
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
/* This clears the IPL bits, then sets them to
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
from an interrupt that has a priority above
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
can only result in the IPL being unchanged or raised, and therefore never
lowered. */
_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
return uxSavedStatusRegister;
}
/*-----------------------------------------------------------*/
void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
{
_CP0_SET_STATUS( uxSavedStatusRegister );
}
/*-----------------------------------------------------------*/
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
void vPortTaskUsesFPU(void)
{
extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
portENTER_CRITICAL();
/* Initialise the floating point status register. */
vPortInitialiseFPSCR(portINITIAL_FPSCR);
/* A task is registering the fact that it needs a FPU context. Set the
FPU flag (saved as part of the task context). */
ulTaskHasFPUContext = pdTRUE;
portEXIT_CRITICAL();
}
#endif /* __mips_hard_float == 1 */
/*-----------------------------------------------------------*/

768
portable/MPLAB/PIC32MZ/port_asm.S Normal file
View file

@ -0,0 +1,768 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include <xc.h>
#include <sys/asm.h>
#include "FreeRTOSConfig.h"
#include "ISR_Support.h"
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vPortIncrementTick
.extern xISRStackTop
.extern ulTaskHasFPUContext
.global vPortStartFirstTask
.global vPortYieldISR
.global vPortTickInterruptHandler
.global vPortInitialiseFPSCR
/******************************************************************/
.set nomips16
.set nomicromips
.set noreorder
.set noat
/***************************************************************
* The following is needed to locate the
* vPortTickInterruptHandler function into the correct vector
***************************************************************/
#ifdef configTICK_INTERRUPT_VECTOR
#if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)
.equ __vector_dispatch_0, vPortTickInterruptHandler
.global __vector_dispatch_0
.section .vector_0, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)
.equ __vector_dispatch_4, vPortTickInterruptHandler
.global __vector_dispatch_4
.section .vector_4, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)
.equ __vector_dispatch_9, vPortTickInterruptHandler
.global __vector_dispatch_9
.section .vector_9, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)
.equ __vector_dispatch_14, vPortTickInterruptHandler
.global __vector_dispatch_14
.section .vector_14, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)
.equ __vector_dispatch_19, vPortTickInterruptHandler
.global __vector_dispatch_19
.section .vector_19, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)
.equ __vector_dispatch_24, vPortTickInterruptHandler
.global __vector_dispatch_24
.section .vector_24, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)
.equ __vector_dispatch_28, vPortTickInterruptHandler
.global __vector_dispatch_28
.section .vector_28, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)
.equ __vector_dispatch_32, vPortTickInterruptHandler
.global __vector_dispatch_32
.section .vector_32, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)
.equ __vector_dispatch_36, vPortTickInterruptHandler
.global __vector_dispatch_36
.section .vector_36, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)
.equ __vector_dispatch_40, vPortTickInterruptHandler
.global __vector_dispatch_40
.section .vector_40, code, keep
#endif
#else
.equ __vector_dispatch_4, vPortTickInterruptHandler
.global __vector_dispatch_4
.section .vector_4, code, keep
#endif
.ent vPortTickInterruptHandler
vPortTickInterruptHandler:
portSAVE_CONTEXT
jal vPortIncrementTick
nop
portRESTORE_CONTEXT
.end vPortTickInterruptHandler
/******************************************************************/
.set noreorder
.set noat
.section .text, code
.ent vPortStartFirstTask
vPortStartFirstTask:
/* Simply restore the context of the highest priority task that has been
created so far. */
portRESTORE_CONTEXT
.end vPortStartFirstTask
/*******************************************************************/
.set nomips16
.set nomicromips
.set noreorder
.set noat
/***************************************************************
* The following is needed to locate the vPortYieldISR function
* into the correct vector
***************************************************************/
.equ __vector_dispatch_1, vPortYieldISR
.global __vector_dispatch_1
.section .vector_1, code
.ent vPortYieldISR
vPortYieldISR:
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/* Code sequence for FPU support, the context save requires advance
knowledge of the stack frame size and if the current task actually uses the
FPU. */
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so their original values are
captured. */
la k0, ulTaskHasFPUContext
lw k0, 0(k0)
beq k0, zero, 1f
addiu sp, sp, -portCONTEXT_SIZE /* always reserve space for the context. */
addiu sp, sp, -portFPU_CONTEXT_SIZE /* reserve additional space for the FPU context. */
1:
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
sw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
/* Prepare to re-enabled interrupts above the kernel priority. */
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved across
nesting interrupts. */
/* Save the AC0, AC1, AC2 and AC3. */
mfhi s7, $ac1
sw s7, 128(s5)
mflo s7, $ac1
sw s7, 124(s5)
mfhi s7, $ac2
sw s7, 136(s5)
mflo s7, $ac2
sw s7, 132(s5)
mfhi s7, $ac3
sw s7, 144(s5)
mflo s7, $ac3
sw s7, 140(s5)
rddsp s7
sw s7, 148(s5)
mfhi s7, $ac0
sw s7, 12(s5)
mflo s7, $ac0
sw s7, 8(s5)
/* Test if FPU context save is required. */
lw s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
beq s7, zero, 1f
nop
/* Save the FPU registers above the normal context. */
portSAVE_FPU_REGS (portCONTEXT_SIZE + 8), s5
/* Save the FPU status register */
cfc1 s7, $f31
sw s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
1:
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API. The
yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
raise the IPL value and never lower it. */
di
ehb
mfc0 s7, _CP0_STATUS
ins s7, zero, 10, 7
ins s7, zero, 18, 1
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
ehb
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
ins s6, zero, 8, 1
mtc0 s6, _CP0_CAUSE
ehb
/* Clear the interrupt in the interrupt controller. */
la s6, IFS0CLR
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7. */
mtc0 s7, _CP0_STATUS
ehb
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Test if the FPU context needs restoring. */
lw s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
beq s0, zero, 1f
nop
/* Restore the FPU status register. */
lw s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
ctc1 s0, $f31
/* Restore the FPU registers. */
portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
1:
/* Restore the rest of the context. */
lw s0, 128(s5)
mthi s0, $ac1
lw s0, 124(s5)
mtlo s0, $ac1
lw s0, 136(s5)
mthi s0, $ac2
lw s0, 132(s5)
mtlo s0, $ac2
lw s0, 144(s5)
mthi s0, $ac3
lw s0, 140(s5)
mtlo s0, $ac3
lw s0, 148(s5)
wrdsp s0
lw s0, 8(s5)
mtlo s0, $ac0
lw s0, 12(s5)
mthi s0, $ac0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the FPU context value from the stack */
lw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
la k1, ulTaskHasFPUContext
sw k0, 0(k1)
beq k0, zero, 1f
nop
/* task has FPU context so adjust the stack frame after popping the
status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
addiu sp, sp, portFPU_CONTEXT_SIZE
beq zero, zero, 2f
nop
1:
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
2:
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
#else
/* Code sequence for no FPU support, the context save requires advance
knowledge of the stack frame size when no FPU is being used */
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so thier original values are
captured. */
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Prepare to re-enabled interrupts above the kernel priority. */
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved across
nesting interrupts. */
/* Save the AC0, AC1, AC2 and AC3. */
mfhi s7, $ac1
sw s7, 128(s5)
mflo s7, $ac1
sw s7, 124(s5)
mfhi s7, $ac2
sw s7, 136(s5)
mflo s7, $ac2
sw s7, 132(s5)
mfhi s7, $ac3
sw s7, 144(s5)
mflo s7, $ac3
sw s7, 140(s5)
rddsp s7
sw s7, 148(s5)
mfhi s7, $ac0
sw s7, 12(s5)
mflo s7, $ac0
sw s7, 8(s5)
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API. The
yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
raise the IPL value and never lower it. */
di
ehb
mfc0 s7, _CP0_STATUS
ins s7, zero, 10, 7
ins s7, zero, 18, 1
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
ehb
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
ins s6, zero, 8, 1
mtc0 s6, _CP0_CAUSE
ehb
/* Clear the interrupt in the interrupt controller. */
la s6, IFS0CLR
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7. */
mtc0 s7, _CP0_STATUS
ehb
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Restore the rest of the context. */
lw s0, 128(s5)
mthi s0, $ac1
lw s0, 124(s5)
mtlo s0, $ac1
lw s0, 136(s5)
mthi s0, $ac2
lw s0, 132(s5)
mtlo s0, $ac2
lw s0, 144(s5)
mthi s0, $ac3
lw s0, 140(s5)
mtlo s0, $ac3
lw s0, 148(s5)
wrdsp s0
lw s0, 8(s5)
mtlo s0, $ac0
lw s0, 12(s5)
mthi s0, $ac0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
/* Restore the status and EPC registers and return */
mtc0 k1, _CP0_STATUS
mtc0 k0, _CP0_EPC
ehb
eret
nop
.end vPortYieldISR
/******************************************************************/
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
.macro portFPUSetAndInc reg, dest
mtc1 \reg, \dest
cvt.d.w \dest, \dest
addiu \reg, \reg, 1
.endm
.set noreorder
.set noat
.section .text, code
.ent vPortInitialiseFPSCR
vPortInitialiseFPSCR:
/* Initialize the floating point status register in CP1. The initial
value is passed in a0. */
ctc1 a0, $f31
/* Clear the FPU registers */
addiu a0, zero, 0x0000
portFPUSetAndInc a0, $f0
portFPUSetAndInc a0, $f1
portFPUSetAndInc a0, $f2
portFPUSetAndInc a0, $f3
portFPUSetAndInc a0, $f4
portFPUSetAndInc a0, $f5
portFPUSetAndInc a0, $f6
portFPUSetAndInc a0, $f7
portFPUSetAndInc a0, $f8
portFPUSetAndInc a0, $f9
portFPUSetAndInc a0, $f10
portFPUSetAndInc a0, $f11
portFPUSetAndInc a0, $f12
portFPUSetAndInc a0, $f13
portFPUSetAndInc a0, $f14
portFPUSetAndInc a0, $f15
portFPUSetAndInc a0, $f16
portFPUSetAndInc a0, $f17
portFPUSetAndInc a0, $f18
portFPUSetAndInc a0, $f19
portFPUSetAndInc a0, $f20
portFPUSetAndInc a0, $f21
portFPUSetAndInc a0, $f22
portFPUSetAndInc a0, $f23
portFPUSetAndInc a0, $f24
portFPUSetAndInc a0, $f25
portFPUSetAndInc a0, $f26
portFPUSetAndInc a0, $f27
portFPUSetAndInc a0, $f28
portFPUSetAndInc a0, $f29
portFPUSetAndInc a0, $f30
portFPUSetAndInc a0, $f31
jr ra
nop
.end vPortInitialiseFPSCR
#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/**********************************************************************/
/* Test read back */
/* a0 = address to store registers */
.set noreorder
.set noat
.section .text, code
.ent vPortFPUReadback
.global vPortFPUReadback
vPortFPUReadback:
sdc1 $f0, 0(a0)
sdc1 $f1, 8(a0)
sdc1 $f2, 16(a0)
sdc1 $f3, 24(a0)
sdc1 $f4, 32(a0)
sdc1 $f5, 40(a0)
sdc1 $f6, 48(a0)
sdc1 $f7, 56(a0)
sdc1 $f8, 64(a0)
sdc1 $f9, 72(a0)
sdc1 $f10, 80(a0)
sdc1 $f11, 88(a0)
sdc1 $f12, 96(a0)
sdc1 $f13, 104(a0)
sdc1 $f14, 112(a0)
sdc1 $f15, 120(a0)
sdc1 $f16, 128(a0)
sdc1 $f17, 136(a0)
sdc1 $f18, 144(a0)
sdc1 $f19, 152(a0)
sdc1 $f20, 160(a0)
sdc1 $f21, 168(a0)
sdc1 $f22, 176(a0)
sdc1 $f23, 184(a0)
sdc1 $f24, 192(a0)
sdc1 $f25, 200(a0)
sdc1 $f26, 208(a0)
sdc1 $f27, 216(a0)
sdc1 $f28, 224(a0)
sdc1 $f29, 232(a0)
sdc1 $f30, 240(a0)
sdc1 $f31, 248(a0)
jr ra
nop
.end vPortFPUReadback
#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */

215
portable/MPLAB/PIC32MZ/portmacro.h Normal file
View file

@ -0,0 +1,215 @@
/*
* FreeRTOS Kernel V10.3.0
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* System include files */
#include <xc.h>
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
#if( configUSE_16_BIT_TICKS == 1 )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
#else
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
#define portBYTE_ALIGNMENT 8
#define portSTACK_GROWTH -1
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
/*-----------------------------------------------------------*/
/* Critical section management. */
#define portIPL_SHIFT ( 10UL )
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
never have higher IPL bits set anyway. */
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
#define portSW0_BIT ( 0x01 << 8 )
/* This clears the IPL bits, then sets them to
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
configASSERT() is defined to ensure an assertion handler does not inadvertently
attempt to lower the IPL when the call to assert was triggered because the IPL
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
ensure API function and interrupt entry is as fast and as simple as possible. */
#ifdef configASSERT
#define portDISABLE_INTERRUPTS() \
{ \
uint32_t ulStatus; \
\
/* Mask interrupts at and below the kernel interrupt priority. */ \
ulStatus = _CP0_GET_STATUS(); \
\
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
{ \
ulStatus &= ~portALL_IPL_BITS; \
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
} \
}
#else /* configASSERT */
#define portDISABLE_INTERRUPTS() \
{ \
uint32_t ulStatus; \
\
/* Mask interrupts at and below the kernel interrupt priority. */ \
ulStatus = _CP0_GET_STATUS(); \
ulStatus &= ~portALL_IPL_BITS; \
_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
}
#endif /* configASSERT */
#define portENABLE_INTERRUPTS() \
{ \
uint32_t ulStatus; \
\
/* Unmask all interrupts. */ \
ulStatus = _CP0_GET_STATUS(); \
ulStatus &= ~portALL_IPL_BITS; \
_CP0_SET_STATUS( ulStatus ); \
}
extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void );
#define portCRITICAL_NESTING_IN_TCB 1
#define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical()
extern UBaseType_t uxPortSetInterruptMaskFromISR();
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
#error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
#endif
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
void vPortTaskUsesFPU( void );
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
#endif
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
#if( configMAX_PRIORITIES > 32 )
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#endif
/* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task utilities. */
#define portYIELD() \
{ \
uint32_t ulCause; \
\
/* Trigger software interrupt. */ \
ulCause = _CP0_GET_CAUSE(); \
ulCause |= portSW0_BIT; \
_CP0_SET_CAUSE( ulCause ); \
}
extern volatile UBaseType_t uxInterruptNesting;
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
#define portNOP() __asm volatile ( "nop" )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \
{ \
portYIELD(); \
}
/* Required by the kernel aware debugger. */
#ifdef __DEBUG
#define portREMOVE_STATIC_QUALIFIER
#endif
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */