len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-20 10:08:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add IAR RISC-V 32 Embedded Extension Support (#588)

Browse source 
Adds RV32E support to the IAR port. This is done by
reducing our register usage to the first 16 registers
only.

Influenced by changes in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/543

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Kody Stribrny 2022-11-29 14:55:18 -08:00 • committed by GitHub
parent b213ad8b6e
commit 1d59f65007
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
4 changed files with 53 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

24
portable/IAR/RISC-V/portContext.h
View file

@ -48,7 +48,15 @@
* portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
* specific version of freertos_risc_v_chip_specific_extensions.h. See the
* notes at the top of portASM.S file. */
#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
#ifdef __riscv_32e
#define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
#define portCRITICAL_NESTING_OFFSET 13
#define portMSTATUS_OFFSET 14
#else
#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
#define portCRITICAL_NESTING_OFFSET 29
#define portMSTATUS_OFFSET 30
#endif
EXTERN pxCurrentTCB
EXTERN xISRStackTop
@ -71,6 +79,7 @@ portcontextSAVE_CONTEXT_INTERNAL MACRO
store_x x13, 10 * portWORD_SIZE( sp )
store_x x14, 11 * portWORD_SIZE( sp )
store_x x15, 12 * portWORD_SIZE( sp )
#ifndef __riscv_32e
store_x x16, 13 * portWORD_SIZE( sp )
store_x x17, 14 * portWORD_SIZE( sp )
store_x x18, 15 * portWORD_SIZE( sp )
@ -87,12 +96,13 @@ portcontextSAVE_CONTEXT_INTERNAL MACRO
store_x x29, 26 * portWORD_SIZE( sp )
store_x x30, 27 * portWORD_SIZE( sp )
store_x x31, 28 * portWORD_SIZE( sp )
#endif
load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
store_x t0, 29 * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
csrr t0, mstatus /* Required for MPIE bit. */
store_x t0, 30 * portWORD_SIZE( sp )
store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
@ -123,7 +133,7 @@ portcontextSAVE_INTERRUPT_CONTEXT MACRO
portcontextRESTORE_CONTEXT MACRO
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
/* Load mepc with the address of the instruction in the task to run next. */
load_x t0, 0( sp )
@ -133,10 +143,10 @@ portcontextRESTORE_CONTEXT MACRO
portasmRESTORE_ADDITIONAL_REGISTERS
/* Load mstatus with the interrupt enable bits used by the task. */
load_x t0, 30 * portWORD_SIZE( sp )
load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
csrw mstatus, t0 /* Required for MPIE bit. */
load_x t0, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */
@ -152,6 +162,7 @@ portcontextRESTORE_CONTEXT MACRO
load_x x13, 10 * portWORD_SIZE( sp )
load_x x14, 11 * portWORD_SIZE( sp )
load_x x15, 12 * portWORD_SIZE( sp )
#ifndef __riscv_32e
load_x x16, 13 * portWORD_SIZE( sp )
load_x x17, 14 * portWORD_SIZE( sp )
load_x x18, 15 * portWORD_SIZE( sp )
@ -168,6 +179,7 @@ portcontextRESTORE_CONTEXT MACRO
load_x x29, 26 * portWORD_SIZE( sp )
load_x x30, 27 * portWORD_SIZE( sp )
load_x x31, 28 * portWORD_SIZE( sp )
#endif
addi sp, sp, portCONTEXT_SIZE
mret