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Add IAR RISC-V 32 Embedded Extension Support (#588)

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Adds RV32E support to the IAR port. This is done by
reducing our register usage to the first 16 registers
only.

Influenced by changes in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/543

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Kody Stribrny 2022-11-29 14:55:18 -08:00 • committed by GitHub
parent b213ad8b6e
commit 1d59f65007
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4 changed files with 53 additions and 31 deletions
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6
portable/GCC/RISC-V/portASM.S
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@ -208,12 +208,12 @@ pxPortInitialiseStack:
store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
#ifdef __riscv_32e
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x11-x15. */
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-x15. */
#else
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
#endif
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
load_x t0, xTaskReturnAddress
store_x t0, 0(a0) /* Return address onto the stack. */
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */