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Continue work on MCF52233 demo.
This commit is contained in:
Richard Barry
parent
31606543da
commit
18f84c805f
32 changed files with 3949 additions and 438 deletions
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@ -60,31 +60,35 @@ infinite. */
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#define netifBLOCK_TIME_WAITING_FOR_INPUT fecLINK_DELAY
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/* Constants used to delay while waiting for a tx descriptor to be free. */
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#define fecMAX_TX_WAIT_ATTEMPTS 4
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#define fecTX_BUFFER_WAIT ( 10 / portTICK_RATE_MS )
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#define fecTX_BUFFER_WAIT ( 200 / portTICK_RATE_MS )
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/* We only use a single Tx descriptor - the duplicate send silicon errata
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actually assists in this case. */
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#define fecNUM_FEC_TX_BUFFERS ( 1 )
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#define fecTX_BUFFER_TO_USE ( 0 )
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/*-----------------------------------------------------------*/
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/* The semaphore used to wake the uIP task when data arrives. */
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xSemaphoreHandle xFECSemaphore = NULL;
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xSemaphoreHandle xFECSemaphore = NULL, xTxSemaphore = NULL;
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/* The buffer used by the uIP stack. In this case the pointer is used to
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point to one of the Rx buffers. */
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unsigned portCHAR *uip_buf;
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/* The DMA descriptors. This is a char array to allow us to align it correctly. */
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static unsigned portCHAR xFECTxDescriptors_unaligned[ ( configNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ];
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static unsigned portCHAR xFECTxDescriptors_unaligned[ ( fecNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ];
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static unsigned portCHAR xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_BUFFERS * sizeof( FECBD ) ) + 16 ];
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static FECBD *xFECTxDescriptors;
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static FECBD *xFECRxDescriptors;
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/* The DMA buffers. These are char arrays to allow them to be alligned correctly. */
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static unsigned portCHAR ucFECRxBuffers[ ( configNUM_FEC_RX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
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static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxNextTxBuffer = 0, uxIndexToBufferOwner = 0;
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static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxIndexToBufferOwner = 0;
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/*-----------------------------------------------------------*/
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static void prvEnableFECInterrupts( void );
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static void prvResetFEC( portBASE_TYPE xCalledFromISR );
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/********************************************************************/
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/*
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@ -319,7 +323,7 @@ unsigned portCHAR *pcBufPointer;
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/* Setup the buffers and descriptors. The data member does not point
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anywhere yet as there is not yet anything to send and a zero copy policy
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is used. */
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for( ux = 0; ux < configNUM_FEC_TX_BUFFERS; ux++ )
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for( ux = 0; ux < fecNUM_FEC_TX_BUFFERS; ux++ )
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{
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xFECTxDescriptors[ ux ].status = TX_BD_TC;
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xFECTxDescriptors[ ux ].data = NULL;
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@ -341,11 +345,10 @@ unsigned portCHAR *pcBufPointer;
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}
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/* Set the wrap bit in the last descriptors to form a ring. */
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xFECTxDescriptors[ configNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W;
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xFECTxDescriptors[ fecNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W;
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xFECRxDescriptors[ configNUM_FEC_RX_BUFFERS - 1 ].status |= RX_BD_W;
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uxNextRxBuffer = 0;
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uxNextTxBuffer = 0;
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}
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/*-----------------------------------------------------------*/
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@ -360,6 +363,7 @@ const unsigned portCHAR ucMACAddress[6] =
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/* Create the semaphore used by the ISR to wake the uIP task. */
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vSemaphoreCreateBinary( xFECSemaphore );
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vSemaphoreCreateBinary( xTxSemaphore );
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prvInitialiseFECBuffers();
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@ -517,7 +521,8 @@ unsigned portBASE_TYPE ux;
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MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK33 | MCF_INTC_IMRH_INT_MASK34 | MCF_INTC_IMRH_INT_MASK35 );
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MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK26 | MCF_INTC_IMRL_INT_MASK27
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| MCF_INTC_IMRL_INT_MASK28 | MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK30
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| MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_MASKALL );
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| MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_INT_MASK23 | MCF_INTC_IMRL_INT_MASK24
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| MCF_INTC_IMRL_MASKALL );
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/* Clear any pending FEC interrupt events */
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MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;
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@ -527,6 +532,38 @@ unsigned portBASE_TYPE ux;
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}
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/*-----------------------------------------------------------*/
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static void prvResetFEC( portBASE_TYPE xCalledFromISR )
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{
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portBASE_TYPE x;
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if( xCalledFromISR == pdFALSE )
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{
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taskENTER_CRITICAL();
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}
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{
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prvInitialiseFECBuffers();
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/* Set the Reset bit and clear the Enable bit */
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MCF_FEC_ECR = MCF_FEC_ECR_RESET;
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/* Wait at least 8 clock cycles */
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for( x = 0; x < 10; x++ )
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{
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asm( "NOP" );
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}
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MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
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MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
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}
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if( xCalledFromISR == pdFALSE )
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{
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taskEXIT_CRITICAL();
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}
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}
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/*-----------------------------------------------------------*/
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unsigned short usGetFECRxData( void )
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{
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unsigned portSHORT usLen;
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@ -562,37 +599,31 @@ void vDiscardRxData( void )
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void vSendBufferToFEC( void )
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{
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portLONG l;
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/* Get a DMA buffer into which we can write the data to send. */
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for( l = 0; l < fecMAX_TX_WAIT_ATTEMPTS; l++ )
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/* Ensure no Tx frames are outstanding. */
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if( xSemaphoreTake( xTxSemaphore, fecTX_BUFFER_WAIT ) == pdPASS )
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{
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if( xFECTxDescriptors[ uxNextTxBuffer ].status & TX_BD_R )
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/* Get a DMA buffer into which we can write the data to send. */
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if( xFECTxDescriptors[ fecTX_BUFFER_TO_USE ].status & TX_BD_R )
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{
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/* Wait for the buffer to become available. */
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vTaskDelay( fecTX_BUFFER_WAIT );
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/*** ERROR didn't expect this. Sledge hammer error handling. ***/
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prvResetFEC( pdFALSE );
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/* Make sure we leave the semaphore in the expected state as nothing
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is being transmitted this will not happen in the Tx ISR. */
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xSemaphoreGive( xTxSemaphore );
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}
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else
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{
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/* Setup the buffer descriptor for transmission. The data being
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sent is actually stored in one of the Rx descripter buffers,
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pointed to by uip_buf. */
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xFECTxDescriptors[ uxNextTxBuffer ].length = uip_len;
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xFECTxDescriptors[ uxNextTxBuffer ].status |= (TX_BD_R | TX_BD_L);
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xFECTxDescriptors[ uxNextTxBuffer ].data = uip_buf;
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/* Continue the Tx DMA (in case it was waiting for a new TxBD) */
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MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
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xFECTxDescriptors[ fecTX_BUFFER_TO_USE ].length = uip_len;
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xFECTxDescriptors[ fecTX_BUFFER_TO_USE ].status |= ( TX_BD_R | TX_BD_L );
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xFECTxDescriptors[ fecTX_BUFFER_TO_USE ].data = uip_buf;
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/* Remember which Rx descriptor owns the buffer we are sending. */
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uxIndexToBufferOwner = uxNextRxBuffer;
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uxNextTxBuffer++;
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if( uxNextTxBuffer >= configNUM_FEC_TX_BUFFERS )
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{
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uxNextTxBuffer = 0;
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}
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/* We have finished with this Rx descriptor now. */
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uxNextRxBuffer++;
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if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS )
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@ -600,9 +631,14 @@ portLONG l;
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uxNextRxBuffer = 0;
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}
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break;
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/* Continue the Tx DMA (in case it was waiting for a new TxBD) */
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MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
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}
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}
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else
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{
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vDiscardRxData();
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}
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}
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/*-----------------------------------------------------------*/
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@ -623,8 +659,7 @@ portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;
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if( ulEvent & ( MCF_FEC_EIR_UN | MCF_FEC_EIR_RL | MCF_FEC_EIR_LC | MCF_FEC_EIR_EBERR | MCF_FEC_EIR_BABT | MCF_FEC_EIR_BABR | MCF_FEC_EIR_HBERR ) )
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{
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/* Sledge hammer error handling. */
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prvInitialiseFECBuffers();
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MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
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prvResetFEC( pdTRUE );
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}
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if( ( ulEvent & MCF_FEC_EIR_TXF ) || ( ulEvent & MCF_FEC_EIR_TXB ) )
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@ -633,12 +668,14 @@ portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;
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buffer has been sent we can mark the Rx descriptor as free again. */
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xFECRxDescriptors[ uxIndexToBufferOwner ].status |= RX_BD_E;
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MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
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xSemaphoreGiveFromISR( xTxSemaphore, &xHighPriorityTaskWoken );
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}
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portEND_SWITCHING_ISR( xHighPriorityTaskWoken );
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}
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/*-----------------------------------------------------------*/
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_87( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_88( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_89( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_90( void ) { vFEC_ISR(); }
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@ -651,5 +688,5 @@ void __attribute__ ((interrupt)) __cs3_isr_interrupt_96( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_97( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_98( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_99( void ) { vFEC_ISR(); }
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void __attribute__ ((interrupt)) __cs3_isr_interrupt_100( void ) { vFEC_ISR(); }
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