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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Temporarily revert the AVR32 port back to the V6.0.5 files. Work will continue on the reverted files following the next release.
This commit is contained in:
Richard Barry
parent
8f6f5820aa
commit
18f5af7195
3 changed files with 462 additions and 33 deletions
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@ -1,3 +1,17 @@
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS port source for AVR32 UC3.
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*
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* - Compiler: GNU GCC for AVR32
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* - Supported devices: All AVR32 devices can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/*
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FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.
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@ -51,8 +65,10 @@
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licensing and training services.
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*/
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/* Standard includes. */
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/* Standard includes. */
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#include <sys/cpu.h>
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#include <sys/usart.h>
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#include <malloc.h>
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/* Scheduler includes. */
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@ -62,8 +78,10 @@
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/* AVR32 UC3 includes. */
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#include <avr32/io.h>
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#include "gpio.h"
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#include <nlao_cpu.h>
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#include <nlao_usart.h>
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#if( configTICK_USE_TC==1 )
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#include "tc.h"
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#endif
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/* Constants required to setup the task context. */
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#define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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@ -73,8 +91,11 @@
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#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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volatile unsigned long ulCriticalNesting = 9999UL;
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/* Clear the COUNT&COMPARE match Interrupt Flag. */
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static void prvClearCcInt( void );
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#if( configTICK_USE_TC==0 )
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static void prvScheduleNextTick( void );
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#else
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static void prvClearTcInt( void );
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#endif
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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@ -119,8 +140,8 @@ void _init_startup(void)
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#endif
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/* Give the used PBA clock frequency to Newlib, so it can work properly. */
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set_cpu_hz( configPBA_CLOCK_HZ );
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/* Give the used CPU clock frequency to Newlib, so it can work properly. */
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set_cpu_hz( configCPU_CLOCK_HZ );
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/* Code section present if and only if the debug trace is activated. */
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#if configDBG
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@ -192,16 +213,22 @@ void *pvReturn;
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/*-----------------------------------------------------------*/
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/* The cooperative scheduler requires a normal IRQ service routine to
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simply increment the system tick.
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The preemptive scheduler is defined as "naked" as the full context is saved
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simply increment the system tick. */
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/* The preemptive scheduler is defined as "naked" as the full context is saved
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on entry as part of the context switch. */
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__attribute__((__naked__)) static void vTick( void )
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{
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/* Save the context of the interrupted task. */
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portSAVE_CONTEXT_OS_INT();
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/* Clear the interrupt flag. */
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prvClearCcInt();
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#if( configTICK_USE_TC==1 )
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/* Clear the interrupt flag. */
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prvClearTcInt();
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#else
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/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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clock cycles from now. */
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prvScheduleNextTick();
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#endif
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/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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calls in a critical section . */
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@ -214,13 +241,6 @@ __attribute__((__naked__)) static void vTick( void )
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}
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/*-----------------------------------------------------------*/
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/* Note that the scall handler in the framework 'exception.x' must
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* jump to this handler.
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* In file: 'AVR32_UC3/Drivers/INTC/exception.x' replace the line after
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* '_handle_Supervisor_Call:' which might be 'rjmp $'
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* with the instruction:
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* 'lda.w pc, SCALLYield'
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*/
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__attribute__((__naked__)) void SCALLYield( void )
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{
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/* Save the context of the interrupted task. */
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@ -288,7 +308,7 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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*pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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*pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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*pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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*pxTopOfStack-- = ( portSTACK_TYPE ) 0x00000000; /* R7 aka Frame Pointer */
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*pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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*pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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return pxTopOfStack;
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@ -318,28 +338,124 @@ void vPortEndScheduler( void )
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/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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clock cycles from now. */
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static void prvScheduleFirstTick(void)
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{
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Set_system_register(AVR32_COMPARE, configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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Set_system_register(AVR32_COUNT, 0);
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}
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/*-----------------------------------------------------------*/
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#if( configTICK_USE_TC==0 )
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static void prvScheduleFirstTick(void)
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{
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unsigned long lCycles;
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__attribute__((__noinline__)) static void prvClearCcInt(void)
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{
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Set_system_register(AVR32_COMPARE, Get_system_register(AVR32_COMPARE));
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}
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lCycles = Get_system_register(AVR32_COUNT);
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lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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// generation feature does not get disabled.
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if(0 == lCycles)
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{
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lCycles++;
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}
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Set_system_register(AVR32_COMPARE, lCycles);
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}
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__attribute__((__noinline__)) static void prvScheduleNextTick(void)
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{
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unsigned long lCycles, lCount;
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lCycles = Get_system_register(AVR32_COMPARE);
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lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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// generation feature does not get disabled.
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if(0 == lCycles)
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{
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lCycles++;
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}
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lCount = Get_system_register(AVR32_COUNT);
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if( lCycles < lCount )
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{ // We missed a tick, recover for the next.
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lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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}
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Set_system_register(AVR32_COMPARE, lCycles);
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}
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#else
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__attribute__((__noinline__)) static void prvClearTcInt(void)
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{
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AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
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}
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#endif
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/*-----------------------------------------------------------*/
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt(void)
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{
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#if( configTICK_USE_TC==1 )
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volatile avr32_tc_t *tc = &AVR32_TC;
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// Options for waveform genration.
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tc_waveform_opt_t waveform_opt =
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{
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.channel = configTICK_TC_CHANNEL, /* Channel selection. */
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.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
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.enetrg = FALSE, /* External event trigger enable. */
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.eevt = 0, /* External event selection. */
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.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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.cpcdis = FALSE, /* Counter disable when RC compare. */
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.cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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.burst = FALSE, /* Burst signal selection. */
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.clki = FALSE, /* Clock inversion. */
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.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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};
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tc_interrupt_t tc_interrupt =
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{
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.etrgs=0,
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.ldrbs=0,
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.ldras=0,
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.cpcs =1,
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.cpbs =0,
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.cpas =0,
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.lovrs=0,
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.covfs=0,
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};
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#endif
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/* Disable all interrupt/exception. */
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portDISABLE_INTERRUPTS();
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/* Register the compare interrupt handler to the interrupt controller and
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enable the compare interrupt. */
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INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT0);
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prvScheduleFirstTick();
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#if( configTICK_USE_TC==1 )
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{
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INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
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/* Initialize the timer/counter. */
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tc_init_waveform(tc, &waveform_opt);
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/* Set the compare triggers.
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Remember TC counter is 16-bits, so counting second is not possible!
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That's why we configure it to count ms. */
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tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
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tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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/* Start the timer/counter. */
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tc_start(tc, configTICK_TC_CHANNEL);
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}
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#else
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{
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INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
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prvScheduleFirstTick();
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}
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#endif
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}
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/*-----------------------------------------------------------*/
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