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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Rename the RISC-V_RV32_SiFive_Hifive1_GCC folder to RISC-V_RV32_SiFive_HiFive1_FreedomStudio as it is built with Freedom Studio.
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/* Copyright 2019 SiFive, Inc */
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/* SPDX-License-Identifier: Apache-2.0 */
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/* ----------------------------------- */
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/* ----------------------------------- */
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OUTPUT_ARCH("riscv")
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ENTRY(_enter)
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MEMORY
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{
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ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
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flash (rxai!w) : ORIGIN = 0x20010000, LENGTH = 0x6a120
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}
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PHDRS
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{
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flash PT_LOAD;
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ram_init PT_LOAD;
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itim_init PT_LOAD;
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ram PT_NULL;
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itim PT_NULL;
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}
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SECTIONS
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{
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__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
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PROVIDE(__stack_size = __stack_size);
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__heap_size = DEFINED(__heap_size) ? __heap_size : 0x4;
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PROVIDE(__metal_boot_hart = 0);
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PROVIDE(__metal_chicken_bit = 0);
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.init :
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{
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KEEP (*(.text.metal.init.enter))
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KEEP (*(SORT_NONE(.init)))
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KEEP (*(.text.libgloss.start))
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} >flash AT>flash :flash
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.text :
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{
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*(.text.unlikely .text.unlikely.*)
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*(.text.startup .text.startup.*)
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*(.text .text.*)
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*(.itim .itim.*)
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*(.gnu.linkonce.t.*)
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} >flash AT>flash :flash
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.fini :
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{
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KEEP (*(SORT_NONE(.fini)))
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} >flash AT>flash :flash
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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. = ALIGN(8);
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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} >flash AT>flash :flash
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. = ALIGN(4);
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >flash AT>flash :flash
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >flash AT>flash :flash
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >flash AT>flash :flash
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of
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the constructors, so we make sure it is
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first. Because this is a wildcard, it
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doesn't matter if the user does not
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actually link against crtbegin.o; the
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linker won't look for a file to match a
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wildcard. The wildcard also means that it
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doesn't matter which directory crtbegin.o
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is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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the crtend.o file until after the sorted ctors.
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The .ctor section from the crtend file contains the
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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} >flash AT>flash :flash
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*crtbegin?.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >flash AT>flash :flash
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.litimalign :
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{
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. = ALIGN(4);
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PROVIDE( metal_segment_itim_source_start = . );
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} >flash AT>flash :flash
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.ditimalign :
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{
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. = ALIGN(4);
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PROVIDE( metal_segment_itim_target_start = . );
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} >ram AT>flash :ram_init
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.itim :
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{
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*(.itim .itim.*)
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} >flash AT>flash :flash
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. = ALIGN(8);
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PROVIDE( metal_segment_itim_target_end = . );
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.lalign :
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{
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. = ALIGN(4);
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PROVIDE( _data_lma = . );
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PROVIDE( metal_segment_data_source_start = . );
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} >flash AT>flash :flash
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE( metal_segment_data_target_start = . );
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} >ram AT>flash :ram_init
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.data :
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{
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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. = ALIGN(8);
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PROVIDE( __global_pointer$ = . + 0x800 );
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*(.sdata .sdata.* .sdata2.*)
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*(.gnu.linkonce.s.*)
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} >ram AT>flash :ram_init
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. = ALIGN(4);
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PROVIDE( _edata = . );
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PROVIDE( edata = . );
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PROVIDE( metal_segment_data_target_end = . );
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PROVIDE( _fbss = . );
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PROVIDE( __bss_start = . );
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PROVIDE( metal_segment_bss_target_start = . );
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.bss :
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{
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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} >ram AT>ram :ram
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. = ALIGN(8);
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PROVIDE( _end = . );
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PROVIDE( end = . );
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PROVIDE( metal_segment_bss_target_end = . );
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.stack :
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{
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. = ALIGN(16);
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metal_segment_stack_begin = .;
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. += __stack_size;
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. = ALIGN(16);
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_sp = .;
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PROVIDE(metal_segment_stack_end = .);
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__freertos_irq_stack_top = .;
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} >ram AT>ram :ram
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.heap :
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{
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PROVIDE( metal_segment_heap_target_start = . );
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. = __heap_size;
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PROVIDE( metal_segment_heap_target_end = . );
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PROVIDE( _heap_end = . );
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} >ram AT>ram :ram
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}
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