From 1531d52a1412ef646f639f14cfd09aee6b26becc Mon Sep 17 00:00:00 2001 From: Alfred Gedeon Date: Thu, 13 Aug 2020 12:16:28 -0700 Subject: [PATCH] Style: add uncrustify disable parsing for asm --- portable/ARMv8M/non_secure/port.c | 4 +- portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 4 +- portable/GCC/ARM_CM33/non_secure/port.c | 4 +- portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 4 +- portable/GCC/ARM_CM4_MPU/port.c | 6 +- portable/GCC/ARM_CM4_MPU/portmacro.h | 499 ++++++++--------- portable/GCC/ARM_CR5/port.c | 4 +- portable/GCC/AVR_AVRDx/port.c | 2 +- portable/GCC/AVR_AVRDx/portmacro.h | 88 +-- portable/GCC/AVR_Mega0/port.c | 4 +- portable/GCC/AVR_Mega0/portmacro.h | 80 +-- portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 64 +-- portable/IAR/ARM_CM33/non_secure/port.c | 64 +-- portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 64 +-- portable/IAR/ARM_CM4F_MPU/portmacro.h | 417 +++++++------- portable/IAR/AVR_AVRDx/port.c | 181 ++++--- portable/IAR/AVR_AVRDx/portmacro.h | 64 +-- portable/IAR/AVR_Mega0/port.c | 183 ++++--- portable/IAR/AVR_Mega0/portmacro.h | 64 +-- portable/MikroC/ARM_CM4F/port.c | 60 ++- portable/RVDS/ARM_CM0/port.c | 18 +- portable/RVDS/ARM_CM3/port.c | 26 +- portable/RVDS/ARM_CM4F/port.c | 32 +- portable/RVDS/ARM_CM4_MPU/port.c | 194 ++++--- portable/RVDS/ARM_CM4_MPU/portmacro.h | 507 +++++++++--------- portable/RVDS/ARM_CM7/r0p1/port.c | 44 +- .../ThirdParty/GCC/ARC_EM_HS/freertos_tls.c | 3 +- portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h | 148 ++--- .../GCC/Xtensa_ESP32/include/portmacro.h | 502 ++++++++--------- 29 files changed, 1751 insertions(+), 1583 deletions(-) diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 3f39bc3b1..c104064f3 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 3f39bc3b1..c104064f3 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 3f39bc3b1..c104064f3 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 3f39bc3b1..c104064f3 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index af9b53e1f..d1cf78133 100644 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -941,10 +941,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, * be set to a value equal to or numerically *higher* than * configMAX_SYSCALL_INTERRUPT_PRIORITY. * - * Interrupts that use the FreeRTOS API must not be left at their - * default priority of zero as that is the highest possible priority, + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, - * and therefore also guaranteed to be invalid. + * and therefore also guaranteed to be invalid. * * FreeRTOS maintains separate thread and ISR API functions to ensure * interrupt entry is as fast and simple as possible. diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h index 4588dd2c0..7f247a2c7 100644 --- a/portable/GCC/ARM_CM4_MPU/portmacro.h +++ b/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -27,11 +27,14 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H - #ifdef __cplusplus - extern "C" { - #endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -44,169 +47,170 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configUSE_16_BIT_TICKS == 1 ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #else - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ - #define portUSING_MPU_WRAPPERS 1 - #define portPRIVILEGE_BIT ( 0x80000000UL ) +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) - #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) - #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) - #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) - #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size - * Register (RASR). */ - #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) - #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - /* MPU settings that can be overriden in FreeRTOSConfig.h. */ - #ifndef configTOTAL_MPU_REGIONS - /* Define to 8 for backward compatibility. */ - #define configTOTAL_MPU_REGIONS ( 8UL ) - #endif +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) - /* - * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the - * memory type, and where necessary the cacheable and shareable properties - * of the memory region. - * - * The TEX, C, and B bits together indicate the memory type of the region, - * and: - * - For Normal memory, the cacheable properties of the region. - * - For Device memory, whether the region is shareable. - * - * For Normal memory regions, the S bit indicates whether the region is - * shareable. For Strongly-ordered and Device memory, the S bit is ignored. - * - * See the following two tables for setting TEX, S, C and B bits for - * unprivileged flash, privileged flash and privileged RAM regions. - * - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 0 | 1 | Device | Shared device | Shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 0 | 1 | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 0 | 0 | Device | Non-shared device | Not shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 0 | 1 | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 1 | X | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 011 | X | X | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | - | | | | | outer cacheability rules that must be exported on the | | - | | | | | bus. See the table below for the cacheability policy | | - | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif - +-----------------------------------------+----------------------------------------+ - | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | - +-----------------------------------------+----------------------------------------+ - | 00 | Non-cacheable | - +-----------------------------------------+----------------------------------------+ - | 01 | Write-back, write and read allocate | - +-----------------------------------------+----------------------------------------+ - | 10 | Write-through, no write allocate | - +-----------------------------------------+----------------------------------------+ - | 11 | Write-back, no write allocate | - +-----------------------------------------+----------------------------------------+ - */ +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ - /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash - * region. */ - #ifndef configTEX_S_C_B_FLASH - /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ - #define configTEX_S_C_B_FLASH ( 0x07UL ) - #endif +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif - /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM - * region. */ - #ifndef configTEX_S_C_B_SRAM - /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ - #define configTEX_S_C_B_SRAM ( 0x07UL ) - #endif +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif - #define portUNPRIVILEGED_FLASH_REGION ( 0UL ) - #define portPRIVILEGED_FLASH_REGION ( 1UL ) - #define portPRIVILEGED_RAM_REGION ( 2UL ) - #define portGENERAL_PERIPHERALS_REGION ( 3UL ) - #define portSTACK_REGION ( 4UL ) - #define portFIRST_CONFIGURABLE_REGION ( 5UL ) - #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS ) - #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION ) - #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 ) +#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) +#define portPRIVILEGED_FLASH_REGION ( 1UL ) +#define portPRIVILEGED_RAM_REGION ( 2UL ) +#define portGENERAL_PERIPHERALS_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS ) +#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION ) +#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 ) - #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) - typedef struct MPU_REGION_REGISTERS - { - uint32_t ulRegionBaseAddress; - uint32_t ulRegionAttribute; - } xMPU_REGION_REGISTERS; +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; /* Plus 1 to create space for the stack region. */ - typedef struct MPU_SETTINGS - { - xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; - } xMPU_SETTINGS; +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; +} xMPU_SETTINGS; /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portDONT_DISCARD __attribute__( ( used ) ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) /*-----------------------------------------------------------*/ /* SVC numbers for various services. */ - #define portSVC_START_SCHEDULER 0 - #define portSVC_YIELD 1 - #define portSVC_RAISE_PRIVILEGE 2 +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 /* Scheduler utilities. */ - #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) - #define portYIELD_WITHIN_API() \ +#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -217,178 +221,181 @@ __asm volatile ( "isb" ); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ - __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) - { - uint8_t ucReturn; + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; - __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); - return ucReturn; - } + return ucReturn; + } /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - extern BaseType_t xIsPrivileged( void ); - extern void vResetPrivilege( void ); +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ - #define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ - #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ - #define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; } -/*-----------------------------------------------------------*/ - - portFORCE_INLINE static void vPortRaiseBASEPRI( void ) - { - uint32_t ulNewBASEPRI; - - __asm volatile - ( - " mov %0, %1 \n"\ - " msr basepri, %0 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); - } + return xReturn; +} /*-----------------------------------------------------------*/ - portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) - { - uint32_t ulOriginalBASEPRI, ulNewBASEPRI; +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; - __asm volatile - ( - " mrs %0, basepri \n"\ - " mov %1, %2 \n"\ - " msr basepri, %1 \n"\ - " isb \n"\ - " dsb \n"\ - : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" - ); + __asm volatile + ( + " mov %0, %1 \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} - /* This return will not be reached but is necessary to prevent compiler - * warnings. */ - return ulOriginalBASEPRI; - } /*-----------------------------------------------------------*/ - portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) - { - __asm volatile - ( - " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" - ); - } +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} /*-----------------------------------------------------------*/ - #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) - - #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */ - #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 - #endif +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" + ); +} /*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */ + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ #ifdef __cplusplus } #endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c index 0658218a0..474c3b824 100644 --- a/portable/GCC/ARM_CR5/port.c +++ b/portable/GCC/ARM_CR5/port.c @@ -482,12 +482,12 @@ uint32_t ulPortSetInterruptMask( void ) { uint32_t ulReturn; uint32_t wasIRQDisabled; - + /* We keep track of if the IRQ are enabled in the CPU (as opposed to interrupts masked in the interrupt controller, like the intend of this function). * This is very important because when the CPU is interrupted, among other things, the hardware clears the IRQ Enable bit in the CPSR of the IRQ CPU Mode in which * we enter. */ wasIRQDisabled = IS_IRQ_DISABLED(); - + /* Interrupt in the CPU must be turned off while the ICCPMR is being * updated. */ portCPU_IRQ_DISABLE(); diff --git a/portable/GCC/AVR_AVRDx/port.c b/portable/GCC/AVR_AVRDx/port.c index 9d5cb9683..42e03de69 100644 --- a/portable/GCC/AVR_AVRDx/port.c +++ b/portable/GCC/AVR_AVRDx/port.c @@ -206,7 +206,7 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC pxTopOfStack--; *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ pxTopOfStack--; - + /* Now the remaining registers. The compiler expects R1 to be 0. */ *pxTopOfStack = (StackType_t)0x00; /* R1 */ diff --git a/portable/GCC/AVR_AVRDx/portmacro.h b/portable/GCC/AVR_AVRDx/portmacro.h index 085a27fc1..99fd4b3ad 100644 --- a/portable/GCC/AVR_AVRDx/portmacro.h +++ b/portable/GCC/AVR_AVRDx/portmacro.h @@ -23,14 +23,16 @@ * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! -*/ + */ #ifndef PORTMACRO_H #define PORTMACRO_H -#ifdef __cplusplus -extern "C" { -#endif +/* *INDENT-OFF* */ + #ifdef __cplusplus + extern "C" { + #endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -43,64 +45,66 @@ extern "C" { */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char -#define portPOINTER_SIZE_TYPE uint16_t +#define portPOINTER_SIZE_TYPE uint16_t -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; -#if (configUSE_16_BIT_TICKS == 1) -typedef uint16_t TickType_t; -#define portMAX_DELAY (TickType_t)0xffff +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #else -typedef uint32_t TickType_t; -#define portMAX_DELAY (TickType_t)0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #endif /*-----------------------------------------------------------*/ /* Critical section management. */ -#define portENTER_CRITICAL() \ - asm volatile("in __tmp_reg__, __SREG__"); \ - asm volatile("cli"); \ - asm volatile("push __tmp_reg__") +#define portENTER_CRITICAL() \ + asm volatile ( "in __tmp_reg__, __SREG__" ); \ + asm volatile ( "cli" ); \ + asm volatile ( "push __tmp_reg__" ) -#define portEXIT_CRITICAL() \ - asm volatile("pop __tmp_reg__"); \ - asm volatile("out __SREG__, __tmp_reg__") +#define portEXIT_CRITICAL() \ + asm volatile ( "pop __tmp_reg__" ); \ + asm volatile ( "out __SREG__, __tmp_reg__" ) -#define portDISABLE_INTERRUPTS() asm volatile("cli" ::); -#define portENABLE_INTERRUPTS() asm volatile("sei" ::); +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" ::); /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH (-1) -#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm volatile("nop"); +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); /*-----------------------------------------------------------*/ /* Kernel utilities. */ -extern void vPortYield(void) __attribute__((naked)); -#define portYIELD() vPortYield() +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() -extern void vPortYieldFromISR(void) __attribute__((naked)); -#define portYIELD_FROM_ISR() vPortYieldFromISR() +extern void vPortYieldFromISR( void ) __attribute__( ( naked ) ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) -#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#ifdef __cplusplus -} -#endif +/* *INDENT-OFF* */ + #ifdef __cplusplus + } + #endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/GCC/AVR_Mega0/port.c b/portable/GCC/AVR_Mega0/port.c index 8c4684294..83d36da12 100644 --- a/portable/GCC/AVR_Mega0/port.c +++ b/portable/GCC/AVR_Mega0/port.c @@ -172,14 +172,14 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC uint16_t usAddress; /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ - + /* Place a few bytes of known values on the bottom of the stack. This is just useful for debugging. Uncomment if needed. */ // *pxTopOfStack = 0x11; // pxTopOfStack--; // *pxTopOfStack = 0x22; // pxTopOfStack--; - // *pxTopOfStack = 0x33; + // *pxTopOfStack = 0x33; // pxTopOfStack--; /* The start of the task code will be popped off the stack last, so place diff --git a/portable/GCC/AVR_Mega0/portmacro.h b/portable/GCC/AVR_Mega0/portmacro.h index 085a27fc1..a464215de 100644 --- a/portable/GCC/AVR_Mega0/portmacro.h +++ b/portable/GCC/AVR_Mega0/portmacro.h @@ -23,14 +23,16 @@ * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! -*/ + */ #ifndef PORTMACRO_H #define PORTMACRO_H +/* *INDENT-OFF* */ #ifdef __cplusplus -extern "C" { + extern "C" { #endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -43,64 +45,66 @@ extern "C" { */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char -#define portPOINTER_SIZE_TYPE uint16_t +#define portPOINTER_SIZE_TYPE uint16_t -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; -#if (configUSE_16_BIT_TICKS == 1) -typedef uint16_t TickType_t; -#define portMAX_DELAY (TickType_t)0xffff +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #else -typedef uint32_t TickType_t; -#define portMAX_DELAY (TickType_t)0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #endif /*-----------------------------------------------------------*/ /* Critical section management. */ -#define portENTER_CRITICAL() \ - asm volatile("in __tmp_reg__, __SREG__"); \ - asm volatile("cli"); \ - asm volatile("push __tmp_reg__") +#define portENTER_CRITICAL() \ + asm volatile ( "in __tmp_reg__, __SREG__" ); \ + asm volatile ( "cli" ); \ + asm volatile ( "push __tmp_reg__" ) -#define portEXIT_CRITICAL() \ - asm volatile("pop __tmp_reg__"); \ - asm volatile("out __SREG__, __tmp_reg__") +#define portEXIT_CRITICAL() \ + asm volatile ( "pop __tmp_reg__" ); \ + asm volatile ( "out __SREG__, __tmp_reg__" ) -#define portDISABLE_INTERRUPTS() asm volatile("cli" ::); -#define portENABLE_INTERRUPTS() asm volatile("sei" ::); +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" ::); /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH (-1) -#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm volatile("nop"); +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); /*-----------------------------------------------------------*/ /* Kernel utilities. */ -extern void vPortYield(void) __attribute__((naked)); -#define portYIELD() vPortYield() +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() -extern void vPortYieldFromISR(void) __attribute__((naked)); -#define portYIELD_FROM_ISR() vPortYieldFromISR() +extern void vPortYieldFromISR( void ) __attribute__( ( naked ) ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) -#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/* *INDENT-OFF* */ #ifdef __cplusplus -} + } #endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 3f39bc3b1..9ee28cde2 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch @@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1091,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 3f39bc3b1..9ee28cde2 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch @@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1091,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 3f39bc3b1..9ee28cde2 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch @@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1091,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h index dc72bb934..df776db56 100644 --- a/portable/IAR/ARM_CM4F_MPU/portmacro.h +++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h @@ -27,11 +27,13 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H - #ifdef __cplusplus - extern "C" { - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -44,171 +46,172 @@ */ /* IAR includes. */ - #include +#include /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configUSE_16_BIT_TICKS == 1 ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #else - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ - #define portUSING_MPU_WRAPPERS 1 - #define portPRIVILEGE_BIT ( 0x80000000UL ) +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) - #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) - #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) - #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) - #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size - * Register (RASR). */ - #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) - #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - /* MPU settings that can be overriden in FreeRTOSConfig.h. */ - #ifndef configTOTAL_MPU_REGIONS - /* Define to 8 for backward compatibility. */ - #define configTOTAL_MPU_REGIONS ( 8UL ) - #endif +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) - /* - * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the - * memory type, and where necessary the cacheable and shareable properties - * of the memory region. - * - * The TEX, C, and B bits together indicate the memory type of the region, - * and: - * - For Normal memory, the cacheable properties of the region. - * - For Device memory, whether the region is shareable. - * - * For Normal memory regions, the S bit indicates whether the region is - * shareable. For Strongly-ordered and Device memory, the S bit is ignored. - * - * See the following two tables for setting TEX, S, C and B bits for - * unprivileged flash, privileged flash and privileged RAM regions. - * - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 0 | 1 | Device | Shared device | Shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 0 | 1 | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 0 | 0 | Device | Non-shared device | Not shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 0 | 1 | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 1 | X | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 011 | X | X | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | - | | | | | outer cacheability rules that must be exported on the | | - | | | | | bus. See the table below for the cacheability policy | | - | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif - +-----------------------------------------+----------------------------------------+ - | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | - +-----------------------------------------+----------------------------------------+ - | 00 | Non-cacheable | - +-----------------------------------------+----------------------------------------+ - | 01 | Write-back, write and read allocate | - +-----------------------------------------+----------------------------------------+ - | 10 | Write-through, no write allocate | - +-----------------------------------------+----------------------------------------+ - | 11 | Write-back, no write allocate | - +-----------------------------------------+----------------------------------------+ - */ +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ - /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash - * region. */ - #ifndef configTEX_S_C_B_FLASH - /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ - #define configTEX_S_C_B_FLASH ( 0x07UL ) - #endif +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif - /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM - * region. */ - #ifndef configTEX_S_C_B_SRAM - /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ - #define configTEX_S_C_B_SRAM ( 0x07UL ) - #endif +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif - #define portUNPRIVILEGED_FLASH_REGION ( 0UL ) - #define portPRIVILEGED_FLASH_REGION ( 1UL ) - #define portPRIVILEGED_RAM_REGION ( 2UL ) - #define portGENERAL_PERIPHERALS_REGION ( 3UL ) - #define portSTACK_REGION ( 4UL ) - #define portFIRST_CONFIGURABLE_REGION ( 5UL ) - #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS ) - #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION ) - #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) +#define portPRIVILEGED_FLASH_REGION ( 1UL ) +#define portPRIVILEGED_RAM_REGION ( 2UL ) +#define portGENERAL_PERIPHERALS_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS ) +#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION ) +#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL ) - #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) - typedef struct MPU_REGION_REGISTERS - { - uint32_t ulRegionBaseAddress; - uint32_t ulRegionAttribute; - } xMPU_REGION_REGISTERS; +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; /* Plus 1 to create space for the stack region. */ - typedef struct MPU_SETTINGS - { - xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; - } xMPU_SETTINGS; +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; +} xMPU_SETTINGS; /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* SVC numbers for various services. */ - #define portSVC_START_SCHEDULER 0 - #define portSVC_YIELD 1 - #define portSVC_RAISE_PRIVILEGE 2 +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 /* Scheduler utilities. */ - #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) - #define portYIELD_WITHIN_API() \ +#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -216,137 +219,139 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API() - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ __DSB(); \ __ISB(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; } + return xReturn; +} + /*-----------------------------------------------------------*/ - extern BaseType_t xIsPrivileged( void ); - extern void vResetPrivilege( void ); +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ - #define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ - #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ - #define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() /*-----------------------------------------------------------*/ - #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */ - #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 - #endif +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */ + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 - #pragma diag_suppress=Be006 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 +#pragma diag_suppress=Be006 /*-----------------------------------------------------------*/ - #ifdef __cplusplus - } - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/IAR/AVR_AVRDx/port.c b/portable/IAR/AVR_AVRDx/port.c index 824c1aa4e..6c4d79fcc 100644 --- a/portable/IAR/AVR_AVRDx/port.c +++ b/portable/IAR/AVR_AVRDx/port.c @@ -32,11 +32,11 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enables. */ -#define portFLAGS_INT_ENABLED ((StackType_t) 0x80) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) /*-----------------------------------------------------------*/ @@ -45,12 +45,13 @@ #define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) /* Stores the critical section nesting. This must not be initialised to 0. -It will be initialised when a task starts. */ + * It will be initialised when a task starts. */ UBaseType_t uxCriticalNesting = 0x50; + /* * Setup timer to generate a tick interrupt. */ -static void prvSetupTimerInterrupt(void); +static void prvSetupTimerInterrupt( void ); /* * The IAR compiler does not have full support for inline assembler, so @@ -64,37 +65,40 @@ extern void vPortStart( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint16_t usAddress; -StackType_t *pxTopOfHardwareStack; + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + /* Simulate how the stack would look after a call to vPortYield(). */ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ /* The IAR compiler requires two stacks per task. First there is the - hardware call stack which uses the AVR stack pointer. Second there is the - software stack (local variables, parameter passing, etc.) which uses the - AVR Y register. - This function places both stacks within the memory block passed in as the - first parameter. The hardware stack is placed at the bottom of the memory - block. A gap is then left for the hardware stack to grow. Next the software - stack is placed. The amount of space between the software and hardware - stacks is defined by configCALL_STACK_SIZE. - The first part of the stack is the hardware stack. Place the start - address of the task on the hardware stack. */ + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - //*pxTopOfStack = 0x11; - //pxTopOfStack--; - //*pxTopOfStack = 0x22; - //pxTopOfStack--; - //*pxTopOfStack = 0x33; - //pxTopOfStack--; - + * This is just useful for debugging. */ + /**pxTopOfStack = 0x11; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x22; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x33; */ + /*pxTopOfStack--; */ + /* Remember where the top of the hardware stack is - this is required - below. */ + * below. */ pxTopOfHardwareStack = pxTopOfStack; usAddress = ( uint16_t ) pxCode; @@ -104,25 +108,25 @@ StackType_t *pxTopOfHardwareStack; usAddress >>= 8; *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; - + /* Leave enough space for the hardware stack before starting the software - stack. The '- 2' is because we have already used two spaces for the - address of the start of the task. */ + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ pxTopOfStack--; - + /* Next place the address of the hardware stack. This is required so - the AVR stack pointer can be restored to point to the hardware stack. */ + * the AVR stack pointer can be restored to point to the hardware stack. */ pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; usAddress = ( uint16_t ) pxTopOfHardwareStack; @@ -136,91 +140,91 @@ StackType_t *pxTopOfHardwareStack; pxTopOfStack--; /* Now the remaining registers. */ - *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ pxTopOfStack--; /* Place the parameter on the stack in the expected location. */ - usAddress = (uint16_t) pvParameters; - *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff); + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; - *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff); + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ pxTopOfStack--; /* The Y register is not stored as it is used as the software stack and - gets saved into the task control block. */ + * gets saved into the task control block. */ - *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ pxTopOfStack--; - *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ - + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + /*lint +e950 +e611 +e923 */ return pxTopOfStack; } /*-----------------------------------------------------------*/ -BaseType_t xPortStartScheduler(void) +BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. */ prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. - Normally we would just call portRESTORE_CONTEXT() here, but as the IAR - compiler does not fully support inline assembler we have to make a call.*/ + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ vPortStart(); /* Should not get here. */ @@ -228,7 +232,7 @@ BaseType_t xPortStartScheduler(void) } /*-----------------------------------------------------------*/ -void vPortEndScheduler(void) +void vPortEndScheduler( void ) { /* vPortEndScheduler is not implemented in this port. */ } @@ -238,7 +242,7 @@ void vPortEndScheduler(void) /* * Setup timer to generate a tick interrupt. */ -static void prvSetupTimerInterrupt(void) +static void prvSetupTimerInterrupt( void ) { TICK_init(); } @@ -246,32 +250,34 @@ static void prvSetupTimerInterrupt(void) /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 1 + /* * Tick ISR for preemptive scheduler. We can use a naked attribute as * the context is saved at the start of vPortYieldFromTick(). The tick * count is incremented after the context is saved. */ -__task void TICK_INT(void) -{ - vPortYieldFromTick(); - asm("reti"); -} + __task void TICK_INT( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } #else + /* * Tick ISR for the cooperative scheduler. All this does is increment the * tick count. We don't need to switch context, this can only be done by * manual calls to taskYIELD(); */ -__interrupt void TICK_INT(void) -{ - /* Clear tick interrupt flag. */ - INT_FLAGS = INT_MASK; + __interrupt void TICK_INT( void ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; - xTaskIncrementTick(); -} -#endif + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ /*-----------------------------------------------------------*/ @@ -286,6 +292,7 @@ void vPortEnterCritical( void ) void vPortExitCritical( void ) { uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) { portENABLE_INTERRUPTS(); diff --git a/portable/IAR/AVR_AVRDx/portmacro.h b/portable/IAR/AVR_AVRDx/portmacro.h index 555f41e10..1c383b9ed 100644 --- a/portable/IAR/AVR_AVRDx/portmacro.h +++ b/portable/IAR/AVR_AVRDx/portmacro.h @@ -29,9 +29,11 @@ #ifndef PORTMACRO_H #define PORTMACRO_H +/* *INDENT-OFF* */ #ifdef __cplusplus -extern "C" { + extern "C" { #endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -44,26 +46,26 @@ extern "C" { */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char -#define portPOINTER_SIZE_TYPE uint16_t +#define portPOINTER_SIZE_TYPE uint16_t -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; -#if (configUSE_16_BIT_TICKS == 1) - typedef uint16_t TickType_t; - #define portMAX_DELAY (TickType_t)0xffff +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #else - typedef uint32_t TickType_t; - #define portMAX_DELAY (TickType_t)0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #endif /*-----------------------------------------------------------*/ @@ -75,31 +77,33 @@ extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() -#define portDISABLE_INTERRUPTS() asm( "cli" ) -#define portENABLE_INTERRUPTS() asm( "sei" ) +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH (-1) -#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm( "nop" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) /*-----------------------------------------------------------*/ /* Kernel utilities. */ -extern void vPortYield(void); -#define portYIELD() vPortYield() +extern void vPortYield( void ); +#define portYIELD() vPortYield() -extern void vPortYieldFromISR(void); -#define portYIELD_FROM_ISR() vPortYieldFromISR() +extern void vPortYieldFromISR( void ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) -#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/* *INDENT-OFF* */ #ifdef __cplusplus -} + } #endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/IAR/AVR_Mega0/port.c b/portable/IAR/AVR_Mega0/port.c index 9e34e1b5e..5af99c1ad 100644 --- a/portable/IAR/AVR_Mega0/port.c +++ b/portable/IAR/AVR_Mega0/port.c @@ -32,11 +32,11 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enables. */ -#define portFLAGS_INT_ENABLED ((StackType_t) 0x80) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) /*-----------------------------------------------------------*/ @@ -45,12 +45,13 @@ #define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) /* Stores the critical section nesting. This must not be initialised to 0. -It will be initialised when a task starts. */ + * It will be initialised when a task starts. */ UBaseType_t uxCriticalNesting = 0x50; + /* * Setup timer to generate a tick interrupt. */ -static void prvSetupTimerInterrupt(void); +static void prvSetupTimerInterrupt( void ); /* * The IAR compiler does not have full support for inline assembler, so @@ -64,37 +65,40 @@ extern void vPortStart( void ); /* * See header file for description. */ -StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { -uint16_t usAddress; -StackType_t *pxTopOfHardwareStack; + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + /* Simulate how the stack would look after a call to vPortYield(). */ /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ - + /* The IAR compiler requires two stacks per task. First there is the - hardware call stack which uses the AVR stack pointer. Second there is the - software stack (local variables, parameter passing, etc.) which uses the - AVR Y register. - This function places both stacks within the memory block passed in as the - first parameter. The hardware stack is placed at the bottom of the memory - block. A gap is then left for the hardware stack to grow. Next the software - stack is placed. The amount of space between the software and hardware - stacks is defined by configCALL_STACK_SIZE. - The first part of the stack is the hardware stack. Place the start - address of the task on the hardware stack. */ - + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ + /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - //*pxTopOfStack = 0x11; - //pxTopOfStack--; - //*pxTopOfStack = 0x22; - //pxTopOfStack--; - //*pxTopOfStack = 0x33; - //pxTopOfStack--; - + * This is just useful for debugging. */ + /**pxTopOfStack = 0x11; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x22; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x33; */ + /*pxTopOfStack--; */ + /* Remember where the top of the hardware stack is - this is required - below. */ + * below. */ pxTopOfHardwareStack = pxTopOfStack; usAddress = ( uint16_t ) pxCode; @@ -106,21 +110,21 @@ StackType_t *pxTopOfHardwareStack; pxTopOfStack--; /* Leave enough space for the hardware stack before starting the software - stack. The '- 2' is because we have already used two spaces for the - address of the start of the task. */ + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; /* Next place the address of the hardware stack. This is required so - the AVR stack pointer can be restored to point to the hardware stack. */ + * the AVR stack pointer can be restored to point to the hardware stack. */ pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; usAddress = ( uint16_t ) pxTopOfHardwareStack; @@ -134,76 +138,76 @@ StackType_t *pxTopOfHardwareStack; pxTopOfStack--; /* Now the remaining registers. */ - *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ pxTopOfStack--; /* Place the parameter on the stack in the expected location. */ - usAddress = (uint16_t) pvParameters; - *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff); + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; - *pxTopOfStack = (StackType_t) (usAddress & (uint16_t) 0x00ff); + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ pxTopOfStack--; /* The Y register is not stored as it is used as the software stack and - gets saved into the task control block. */ + * gets saved into the task control block. */ - *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ - - pxTopOfStack--; - *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ /*lint +e950 +e611 +e923 */ @@ -211,14 +215,14 @@ StackType_t *pxTopOfHardwareStack; } /*-----------------------------------------------------------*/ -BaseType_t xPortStartScheduler(void) +BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. */ prvSetupTimerInterrupt(); /* Restore the context of the first task that is going to run. - Normally we would just call portRESTORE_CONTEXT() here, but as the IAR - compiler does not fully support inline assembler we have to make a call.*/ + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ vPortStart(); /* Should not get here. */ @@ -226,7 +230,7 @@ BaseType_t xPortStartScheduler(void) } /*-----------------------------------------------------------*/ -void vPortEndScheduler(void) +void vPortEndScheduler( void ) { /* vPortEndScheduler is not implemented in this port. */ } @@ -236,7 +240,7 @@ void vPortEndScheduler(void) /* * Setup timer to generate a tick interrupt. */ -static void prvSetupTimerInterrupt(void) +static void prvSetupTimerInterrupt( void ) { TICK_init(); } @@ -244,32 +248,34 @@ static void prvSetupTimerInterrupt(void) /*-----------------------------------------------------------*/ #if configUSE_PREEMPTION == 1 + /* * Tick ISR for preemptive scheduler. We can use a naked attribute as * the context is saved at the start of vPortYieldFromTick(). The tick * count is incremented after the context is saved. */ -__task void TICK_INT(void) -{ - vPortYieldFromTick(); - asm("reti"); -} + __task void TICK_INT( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } #else + /* * Tick ISR for the cooperative scheduler. All this does is increment the * tick count. We don't need to switch context, this can only be done by * manual calls to taskYIELD(); */ -__interrupt void TICK_INT(void) -{ - /* Clear tick interrupt flag. */ - INT_FLAGS = INT_MASK; - - xTaskIncrementTick(); -} -#endif + __interrupt void TICK_INT( void ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ /*-----------------------------------------------------------*/ @@ -284,6 +290,7 @@ void vPortEnterCritical( void ) void vPortExitCritical( void ) { uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) { portENABLE_INTERRUPTS(); diff --git a/portable/IAR/AVR_Mega0/portmacro.h b/portable/IAR/AVR_Mega0/portmacro.h index 555f41e10..1c383b9ed 100644 --- a/portable/IAR/AVR_Mega0/portmacro.h +++ b/portable/IAR/AVR_Mega0/portmacro.h @@ -29,9 +29,11 @@ #ifndef PORTMACRO_H #define PORTMACRO_H +/* *INDENT-OFF* */ #ifdef __cplusplus -extern "C" { + extern "C" { #endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -44,26 +46,26 @@ extern "C" { */ /* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE char +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char -#define portPOINTER_SIZE_TYPE uint16_t +#define portPOINTER_SIZE_TYPE uint16_t -typedef portSTACK_TYPE StackType_t; -typedef signed char BaseType_t; -typedef unsigned char UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; -#if (configUSE_16_BIT_TICKS == 1) - typedef uint16_t TickType_t; - #define portMAX_DELAY (TickType_t)0xffff +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff #else - typedef uint32_t TickType_t; - #define portMAX_DELAY (TickType_t)0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL #endif /*-----------------------------------------------------------*/ @@ -75,31 +77,33 @@ extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() -#define portDISABLE_INTERRUPTS() asm( "cli" ) -#define portENABLE_INTERRUPTS() asm( "sei" ) +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) /*-----------------------------------------------------------*/ /* Architecture specifics. */ -#define portSTACK_GROWTH (-1) -#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm( "nop" ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) /*-----------------------------------------------------------*/ /* Kernel utilities. */ -extern void vPortYield(void); -#define portYIELD() vPortYield() +extern void vPortYield( void ); +#define portYIELD() vPortYield() -extern void vPortYieldFromISR(void); -#define portYIELD_FROM_ISR() vPortYieldFromISR() +extern void vPortYieldFromISR( void ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) -#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/* *INDENT-OFF* */ #ifdef __cplusplus -} + } #endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index 73b62c498..e61fc40b2 100644 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -246,15 +246,17 @@ static void prvTaskExitError( void ) void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF { __asm { - ldr r3, = _pxCurrentTCB /* Restore the context. */ - ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ +/* *INDENT-OFF* */ + ldr r3, =_pxCurrentTCB /* Restore the context. */ + ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ ldm r0 !, ( r4 - r11, r14 ) /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ msr psp, r0 /* Restore the task stack pointer. */ isb - mov r0, # 0 + mov r0, #0 msr basepri, r0 bx r14 +/* *INDENT-ON* */ }; } /*-----------------------------------------------------------*/ @@ -262,8 +264,9 @@ void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF static void prvPortStartFirstTask( void ) { __asm { - ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */ - ldr r0, [ r0 ] +/* *INDENT-OFF* */ + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [ r0 ] ldr r0, [ r0 ] msr msp, r0 /* Set the msp back to the start of the stack. */ @@ -271,14 +274,15 @@ static void prvPortStartFirstTask( void ) * before the scheduler was started - which would otherwise result in the * unnecessary leaving of space in the SVC stack for lazy saving of FPU * registers. */ - mov r0, # 0 + mov r0, #0 msr control, r0 cpsie i /* Globally enable interrupts. */ cpsie f dsb isb - svc # 0 /* System call to start first task. */ + svc #0 /* System call to start first task. */ nop +/* *INDENT-ON* */ }; } /*-----------------------------------------------------------*/ @@ -432,18 +436,19 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF { __asm { #ifdef HW_DEBUG +/* *INDENT-OFF* */ /* The function is not truly naked, so add back the 4 bytes subtracted - * from the stack pointer by the function prologue. */ + * from the stack pointer by the function prologue. */ add sp, sp, # 4 #endif mrs r0, psp isb - ldr r3, = _pxCurrentTCB /* Get the location of the current TCB. */ - ldr r2, [ r3 ] + ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] - tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ it eq vstmdbeq r0 !, ( s16 - s31 ) @@ -453,12 +458,12 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF stmdb sp !, ( r0, r3 ) ldr r0, = _ucMaxSyscallInterruptPriority - ldr r1, [ r0 ] + ldr r1, [ r0 ] msr basepri, r1 dsb isb bl _vTaskSwitchContext - mov r0, # 0 + mov r0, #0 msr basepri, r0 ldm sp !, ( r0, r3 ) @@ -467,13 +472,14 @@ void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */ - tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ it eq vldmiaeq r0 !, ( s16 - s31 ) msr psp, r0 isb bx r14 +/* *INDENT-ON* */ } } /*-----------------------------------------------------------*/ @@ -499,7 +505,7 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO } /*-----------------------------------------------------------*/ -#if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) ) + #if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { @@ -694,14 +700,14 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO } } -#endif /* #if configUSE_TICKLESS_IDLE */ + #endif /* #if configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ -#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) void vPortSetupTimerInterrupt( void ) { @@ -723,19 +729,21 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); } -#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ + #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm { - ldr r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */ - ldr r1, [ r0 ] +/* *INDENT-OFF* */ + ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr r1, [ r0 ] - orr r1, r1, # 0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */ str r1, [ r0 ] bx r14 +/* *INDENT-ON* */ }; } /*-----------------------------------------------------------*/ @@ -758,7 +766,7 @@ BaseType_t xPortIsInsideInterrupt( void ) } /*-----------------------------------------------------------*/ -#if ( configASSERT_DEFINED == 1 ) + #if ( configASSERT_DEFINED == 1 ) /* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be * global - which makes vPortValidateInterruptPriority() non re-entrant. @@ -772,11 +780,13 @@ BaseType_t xPortIsInsideInterrupt( void ) { /* Obtain the number of the currently executing interrupt. */ __asm { +/* *INDENT-OFF* */ push( r0, r1 ) mrs r0, ipsr - ldr r1, = _ulCurrentInterrupt - str r0, [ r1 ] + ldr r1, =_ulCurrentInterrupt + str r0, [ r1 ] pop( r0, r1 ) +/* *INDENT-ON* */ }; /* Is the interrupt number a user defined interrupt? */ @@ -827,4 +837,4 @@ BaseType_t xPortIsInsideInterrupt( void ) configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* configASSERT_DEFINED */ + #endif /* configASSERT_DEFINED */ diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c index 88d0b120f..d4e76eedc 100644 --- a/portable/RVDS/ARM_CM0/port.c +++ b/portable/RVDS/ARM_CM0/port.c @@ -177,20 +177,21 @@ __asm void prvPortStartFirstTask( void ) /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector * table offset register that can be used to locate the initial stack value. * Not all M0 parts have the application vector table at address 0. */ + /* *INDENT-OFF* */ ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */ - ldr r1, [ r3 ] + ldr r1, [ r3 ] ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ adds r0, # 32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ movs r0, # 2 /* Switch to the psp stack. */ msr CONTROL, r0 isb - pop { + pop { r0 - r5 } /* Pop the registers that are saved automatically. */ mov lr, r5 /* lr is now in r5. */ - pop { + pop { r3 } /* The return address is now in r3. */ pop { @@ -199,7 +200,8 @@ __asm void prvPortStartFirstTask( void ) cpsie i /* The first task has its context and interrupts can be enabled. */ bx r3 /* Finally, jump to the user defined task code. */ - ALIGN + ALIGN +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -289,12 +291,13 @@ __asm void xPortPendSVHandler( void ) extern vTaskSwitchContext extern pxCurrentTCB +/* *INDENT-OFF* */ PRESERVE8 mrs r0, psp ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */ - ldr r2, [ r3 ] + ldr r2, [ r3 ] subs r0, # 32 /* Make space for the remaining low registers. */ str r0, [ r2 ] /* Save the new top of stack. */ @@ -315,7 +318,7 @@ __asm void xPortPendSVHandler( void ) cpsid i bl vTaskSwitchContext cpsie i - pop { + pop { r2, r3 } /* lr goes in r3. r2 now holds tcb pointer. */ @@ -338,7 +341,8 @@ __asm void xPortPendSVHandler( void ) } /* Pop low registers. */ bx r3 - ALIGN + ALIGN +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index 5ac9d2c60..ead2869a7 100644 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -213,10 +213,11 @@ static void prvTaskExitError( void ) __asm void vPortSVCHandler( void ) { +/* *INDENT-OFF* */ PRESERVE8 ldr r3, = pxCurrentTCB /* Restore the context. */ - ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ ldmia r0 !, { r4 - r11 @@ -227,16 +228,18 @@ __asm void vPortSVCHandler( void ) msr basepri, r0 orr r14, # 0xd bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void prvStartFirstTask( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* Use the NVIC offset register to locate the stack. */ ldr r0, = 0xE000ED08 - ldr r0, [ r0 ] + ldr r0, [ r0 ] ldr r0, [ r0 ] /* Set the msp back to the start of the stack. */ @@ -247,9 +250,10 @@ __asm void prvStartFirstTask( void ) dsb isb /* Call SVC to start the first task. */ - svc 0 + svc 0 nop - nop + nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -388,13 +392,14 @@ __asm void xPortPendSVHandler( void ) extern pxCurrentTCB; extern vTaskSwitchContext; +/* *INDENT-OFF* */ PRESERVE8 mrs r0, psp isb - ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */ - ldr r2, [ r3 ] + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] stmdb r0 !, { r4 - r11 @@ -404,12 +409,12 @@ __asm void xPortPendSVHandler( void ) stmdb sp !, { r3, r14 } - mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 dsb isb bl vTaskSwitchContext - mov r0, # 0 + mov r0, #0 msr basepri, r0 ldmia sp !, { r3, r14 @@ -423,7 +428,8 @@ __asm void xPortPendSVHandler( void ) msr psp, r0 isb bx r14 - nop + nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -651,10 +657,12 @@ void xPortSysTickHandler( void ) __asm uint32_t vPortGetIPSR( void ) { +/* *INDENT-OFF* */ PRESERVE8 mrs r0, ipsr bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c index 488e516b7..9bf92e6fa 100644 --- a/portable/RVDS/ARM_CM4F/port.c +++ b/portable/RVDS/ARM_CM4F/port.c @@ -240,6 +240,7 @@ static void prvTaskExitError( void ) __asm void vPortSVCHandler( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* Get the location of the current TCB. */ @@ -255,16 +256,18 @@ __asm void vPortSVCHandler( void ) mov r0, # 0 msr basepri, r0 bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void prvStartFirstTask( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* Use the NVIC offset register to locate the stack. */ - ldr r0, = 0xE000ED08 - ldr r0, [ r0 ] + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] ldr r0, [ r0 ] /* Set the msp back to the start of the stack. */ msr msp, r0 @@ -273,7 +276,7 @@ __asm void prvStartFirstTask( void ) * before the scheduler was started - which would otherwise result in the * unnecessary leaving of space in the SVC stack for lazy saving of FPU * registers. */ - mov r0, # 0 + mov r0, #0 msr control, r0 /* Globally enable interrupts. */ cpsie i @@ -281,25 +284,28 @@ __asm void prvStartFirstTask( void ) dsb isb /* Call SVC to start the first task. */ - svc 0 + svc 0 nop - nop + nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void prvEnableVFP( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* The FPU enable bits are in the CPACR. */ - ldr.w r0, = 0xE000ED88 - ldr r1, [ r0 ] + ldr.w r0, =0xE000ED88 + ldr r1, [ r0 ] /* Enable CP10 and CP11 coprocessors, then save back. */ orr r1, r1, # ( 0xf << 20 ) str r1, [ r0 ] bx r14 nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -453,16 +459,17 @@ __asm void xPortPendSVHandler( void ) extern pxCurrentTCB; extern vTaskSwitchContext; +/* *INDENT-OFF* */ PRESERVE8 mrs r0, psp isb /* Get the location of the current TCB. */ - ldr r3, = pxCurrentTCB - ldr r2, [ r3 ] + ldr r3, =pxCurrentTCB + ldr r2, [ r3 ] /* Is the task using the FPU context? If so, push high vfp registers. */ - tst r14, # 0x10 + tst r14, #0x10 it eq vstmdbeq r0 !, { s16 - s31 @@ -508,7 +515,7 @@ __asm void xPortPendSVHandler( void ) } msr psp, r0 - isb + isb #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ #if WORKAROUND_PMU_CM001 == 1 push { @@ -522,6 +529,7 @@ __asm void xPortPendSVHandler( void ) #endif bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -749,10 +757,12 @@ void xPortSysTickHandler( void ) __asm uint32_t vPortGetIPSR( void ) { +/* *INDENT-OFF* */ PRESERVE8 mrs r0, ipsr bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index 18228f45e..005881a58 100644 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -310,7 +310,8 @@ __asm void vPortSVCHandler( void ) { extern prvSVCHandler - PRESERVE8 +/* *INDENT-OFF* */ + PRESERVE8 /* Assumes psp was in use. */ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ @@ -323,52 +324,69 @@ __asm void vPortSVCHandler( void ) #endif b prvSVCHandler +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void prvRestoreContextOfFirstTask( void ) { +/* *INDENT-OFF* */ PRESERVE8 - ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ ldr r0, [ r0 ] ldr r0, [ r0 ] - msr msp, r0 /* Set the msp back to the start of the stack. */ - ldr r3, = pxCurrentTCB /* Restore the context. */ + msr msp, r0 /* Set the msp back to the start of the stack. */ + ldr r3, =pxCurrentTCB /* Restore the context. */ ldr r1, [ r3 ] - ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ - add r1, r1, # 4 /* Move onto the second item in the TCB... */ + ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ + add r1, r1, #4 /* Move onto the second item in the TCB... */ - dmb /* Complete outstanding transfers before disabling MPU. */ - ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ - ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ - bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ - str r3, [ r2 ] /* Disable MPU. */ + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [ r2 ] /* Disable MPU. */ - ldr r2, = 0xe000ed9c /* Region Base Address register. */ - ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldr r2, =0xe000ed9c /* Region Base Address register. */ + ldmia r1 !, { + r4 - r11 + } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r2, { + r4 - r11 + } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ -#if ( portTOTAL_NUM_REGIONS == 16 ) - ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ - stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ -#endif /* portTOTAL_NUM_REGIONS == 16. */ + #if ( portTOTAL_NUM_REGIONS == 16 ) + ldmia r1 !, { + r4 - r11 + } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r2, { + r4 - r11 + } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + ldmia r1 !, { + r4 - r11 + } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + stmia r2, { + r4 - r11 + } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + #endif /* portTOTAL_NUM_REGIONS == 16. */ - ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ - ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ - orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ - str r3, [ r2 ] /* Enable MPU. */ - dsb /* Force memory writes before continuing. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [ r2 ] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ - ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */ + ldmia r0 !, { + r3 - r11, r14 + } /* Pop the registers that are not automatically saved on exception entry. */ msr control, r3 - msr psp, r0 /* Restore the task stack pointer. */ - mov r0, # 0 + msr psp, r0 /* Restore the task stack pointer. */ + mov r0, #0 msr basepri, r0 bx r14 nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -476,10 +494,11 @@ BaseType_t xPortStartScheduler( void ) __asm void prvStartFirstTask( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* Use the NVIC offset register to locate the stack. */ - ldr r0, = 0xE000ED08 + ldr r0, =0xE000ED08 ldr r0, [ r0 ] ldr r0, [ r0 ] /* Set the msp back to the start of the stack. */ @@ -489,7 +508,7 @@ __asm void prvStartFirstTask( void ) * before the scheduler was started - which would otherwise result in the * unnecessary leaving of space in the SVC stack for lazy saving of FPU * registers. */ - mov r0, # 0 + mov r0, #0 msr control, r0 /* Globally enable interrupts. */ cpsie i @@ -499,6 +518,7 @@ __asm void prvStartFirstTask( void ) svc portSVC_START_SCHEDULER /* System call to start first task. */ nop nop +/* *INDENT-ON* */ } void vPortEndScheduler( void ) @@ -542,68 +562,94 @@ __asm void xPortPendSVHandler( void ) extern pxCurrentTCB; extern vTaskSwitchContext; +/* *INDENT-OFF* */ PRESERVE8 mrs r0, psp - ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ ldr r2, [ r3 ] - tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ it eq - vstmdbeq r0!, {s16-s31} + vstmdbeq r0 !, { + s16 - s31 + } mrs r1, control - stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */ - str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ + stmdb r0 !, { + r1, r4 - r11, r14 + } /* Save the remaining registers. */ + str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ - stmdb sp!, {r0, r3} + stmdb sp !, { + r0, r3 + } mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 dsb isb bl vTaskSwitchContext - mov r0, # 0 + mov r0, #0 msr basepri, r0 - ldmia sp!, {r0, r3} + ldmia sp !, { + r0, r3 + } /* Restore the context. */ ldr r1, [ r3 ] - ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ - add r1, r1, # 4 /* Move onto the second item in the TCB... */ + ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ + add r1, r1, #4 /* Move onto the second item in the TCB... */ - dmb /* Complete outstanding transfers before disabling MPU. */ - ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ - ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ - bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ - str r3, [ r2 ] /* Disable MPU. */ + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [ r2 ] /* Disable MPU. */ - ldr r2, = 0xe000ed9c /* Region Base Address register. */ - ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldr r2, =0xe000ed9c /* Region Base Address register. */ + ldmia r1 !, { + r4 - r11 + } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r2, { + r4 - r11 + } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ -#if ( portTOTAL_NUM_REGIONS == 16 ) - ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ - stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ -#endif /* portTOTAL_NUM_REGIONS == 16. */ + #if ( portTOTAL_NUM_REGIONS == 16 ) + ldmia r1 !, { + r4 - r11 + } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r2, { + r4 - r11 + } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + ldmia r1 !, { + r4 - r11 + } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + stmia r2, { + r4 - r11 + } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + #endif /* portTOTAL_NUM_REGIONS == 16. */ - ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ - ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ - orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ - str r3, [ r2 ] /* Enable MPU. */ - dsb /* Force memory writes before continuing. */ + ldr r2, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [ r2 ] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ - ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */ + ldmia r0 !, { + r3 - r11, r14 + } /* Pop the registers that are not automatically saved on exception entry. */ msr control, r3 - tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ it eq - vldmiaeq r0!, {s16-s31} + vldmiaeq r0 !, { + s16 - s31 + } msr psp, r0 bx r14 nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -642,27 +688,31 @@ __weak void vSetupTimerInterrupt( void ) __asm void vPortSwitchToUserMode( void ) { + /* *INDENT-OFF* */ PRESERVE8 mrs r0, control - orr r0, # 1 + orr r0, #1 msr control, r0 bx r14 + /* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void vPortEnableVFP( void ) { +/* *INDENT-OFF* */ PRESERVE8 - ldr.w r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ ldr r1, [ r0 ] - orr r1, r1, # ( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ str r1, [ r0 ] bx r14 nop nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -761,25 +811,29 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) __asm BaseType_t xIsPrivileged( void ) { +/* *INDENT-OFF* */ PRESERVE8 mrs r0, control /* r0 = CONTROL. */ - tst r0, # 1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ ite ne - movne r0, # 0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ - moveq r0, # 1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ bx lr /* Return. */ +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void vResetPrivilege( void ) { +/* *INDENT-OFF* */ PRESERVE8 mrs r0, control /* r0 = CONTROL. */ - orrs r0, # 1 /* r0 = r0 | 1. */ + orrs r0, #1 /* r0 = r0 | 1. */ msr control, r0 /* CONTROL = r0. */ bx lr /* Return. */ +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -886,10 +940,12 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, __asm uint32_t prvPortGetIPSR( void ) { +/* *INDENT-OFF* */ PRESERVE8 mrs r0, ipsr bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h index e5f5b1234..589e4eb22 100644 --- a/portable/RVDS/ARM_CM4_MPU/portmacro.h +++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -27,11 +27,13 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H - #ifdef __cplusplus - extern "C" { - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ /*----------------------------------------------------------- * Port specific definitions. @@ -44,173 +46,174 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configUSE_16_BIT_TICKS == 1 ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #else - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ - #define portUSING_MPU_WRAPPERS 1 - #define portPRIVILEGE_BIT ( 0x80000000UL ) +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) - #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) - #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) - #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) - #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) - #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size - * Register (RASR). */ - #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) - #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - /* MPU settings that can be overriden in FreeRTOSConfig.h. */ - #ifndef configTOTAL_MPU_REGIONS - /* Define to 8 for backward compatibility. */ - #define configTOTAL_MPU_REGIONS ( 8UL ) - #endif +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) - /* - * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the - * memory type, and where necessary the cacheable and shareable properties - * of the memory region. - * - * The TEX, C, and B bits together indicate the memory type of the region, - * and: - * - For Normal memory, the cacheable properties of the region. - * - For Device memory, whether the region is shareable. - * - * For Normal memory regions, the S bit indicates whether the region is - * shareable. For Strongly-ordered and Device memory, the S bit is ignored. - * - * See the following two tables for setting TEX, S, C and B bits for - * unprivileged flash, privileged flash and privileged RAM regions. - * - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 0 | 1 | Device | Shared device | Shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 0 | 1 | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 0 | 0 | Device | Non-shared device | Not shareable | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 0 | 1 | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 010 | 1 | X | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 011 | X | X | Reserved | Reserved | Reserved | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ - | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | - | | | | | outer cacheability rules that must be exported on the | | - | | | | | bus. See the table below for the cacheability policy | | - | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | - +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ +/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif - +-----------------------------------------+----------------------------------------+ - | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | - +-----------------------------------------+----------------------------------------+ - | 00 | Non-cacheable | - +-----------------------------------------+----------------------------------------+ - | 01 | Write-back, write and read allocate | - +-----------------------------------------+----------------------------------------+ - | 10 | Write-through, no write allocate | - +-----------------------------------------+----------------------------------------+ - | 11 | Write-back, no write allocate | - +-----------------------------------------+----------------------------------------+ - */ +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ - /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash - * region. */ - #ifndef configTEX_S_C_B_FLASH - /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ - #define configTEX_S_C_B_FLASH ( 0x07UL ) - #endif +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif - /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM - * region. */ - #ifndef configTEX_S_C_B_SRAM - /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ - #define configTEX_S_C_B_SRAM ( 0x07UL ) - #endif +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif - #define portUNPRIVILEGED_FLASH_REGION ( 0UL ) - #define portPRIVILEGED_FLASH_REGION ( 1UL ) - #define portPRIVILEGED_RAM_REGION ( 2UL ) - #define portGENERAL_PERIPHERALS_REGION ( 3UL ) - #define portSTACK_REGION ( 4UL ) - #define portFIRST_CONFIGURABLE_REGION ( 5UL ) - #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS ) - #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION ) - #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 ) +#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) +#define portPRIVILEGED_FLASH_REGION ( 1UL ) +#define portPRIVILEGED_RAM_REGION ( 2UL ) +#define portGENERAL_PERIPHERALS_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS ) +#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION ) +#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 ) - void vPortSwitchToUserMode( void ); - #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() +void vPortSwitchToUserMode( void ); +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() - typedef struct MPU_REGION_REGISTERS - { - uint32_t ulRegionBaseAddress; - uint32_t ulRegionAttribute; - } xMPU_REGION_REGISTERS; +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; /* Plus 1 to create space for the stack region. */ - typedef struct MPU_SETTINGS - { - xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; - } xMPU_SETTINGS; +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; +} xMPU_SETTINGS; /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /* Constants used with memory barrier intrinsics. */ - #define portSY_FULL_READ_WRITE ( 15 ) +#define portSY_FULL_READ_WRITE ( 15 ) /*-----------------------------------------------------------*/ /* SVC numbers for various services. */ - #define portSVC_START_SCHEDULER 0 - #define portSVC_YIELD 1 - #define portSVC_RAISE_PRIVILEGE 2 +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 /* Scheduler utilities. */ - #define portYIELD() __asm{ SVC portSVC_YIELD } - #define portYIELD_WITHIN_API() \ +#define portYIELD() __asm{ SVC portSVC_YIELD } +#define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -222,180 +225,190 @@ } /*-----------------------------------------------------------*/ - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() - #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE __forceinline - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif /*-----------------------------------------------------------*/ - extern BaseType_t xIsPrivileged( void ); - extern void vResetPrivilege( void ); +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ - #define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ - #define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE } +#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE } /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ - #define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm { - __asm - { - /* Barrier instructions are not used as this function is only used to - * lower the BASEPRI value. */ - msr basepri, ulBASEPRI - } + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm { - uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ - msr basepri, ulNewBASEPRI - dsb - isb - } + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm { - __asm - { - /* Set BASEPRI to 0 so no interrupts are masked. This function is only - * used to lower the mask in an interrupt, so memory barriers are not - * used. */ - msr basepri, # 0 - } + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ } +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm { - uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; - - __asm - { - /* Set BASEPRI to the max syscall priority to effect a critical - * section. */ - mrs ulReturn, basepri - msr basepri, ulNewBASEPRI - dsb - isb - } - - return ulReturn; + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ } + + return ulReturn; +} /*-----------------------------------------------------------*/ - static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm - { - mrs ulCurrentInterrupt, ipsr - } - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + mrs ulCurrentInterrupt, ipsr } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} /*-----------------------------------------------------------*/ - #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */ - #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 - #endif +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https: /*www.freertos.org/FreeRTOS-V10.3.x.html" */ + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif /*-----------------------------------------------------------*/ - #ifdef __cplusplus - } - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c index d20696431..0519cace4 100644 --- a/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -236,9 +236,10 @@ __asm void vPortSVCHandler( void ) { PRESERVE8 +/* *INDENT-OFF* */ /* Get the location of the current TCB. */ - ldr r3, = pxCurrentTCB - ldr r1, [ r3 ] + ldr r3, =pxCurrentTCB + ldr r1, [ r3 ] ldr r0, [ r1 ] /* Pop the core registers. */ ldmia r0 !, { @@ -246,19 +247,21 @@ __asm void vPortSVCHandler( void ) } msr psp, r0 isb - mov r0, # 0 + mov r0, #0 msr basepri, r0 bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void prvStartFirstTask( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* Use the NVIC offset register to locate the stack. */ - ldr r0, = 0xE000ED08 - ldr r0, [ r0 ] + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] ldr r0, [ r0 ] /* Set the msp back to the start of the stack. */ msr msp, r0 @@ -267,7 +270,7 @@ __asm void prvStartFirstTask( void ) * before the scheduler was started - which would otherwise result in the * unnecessary leaving of space in the SVC stack for lazy saving of FPU * registers. */ - mov r0, # 0 + mov r0, #0 msr control, r0 /* Globally enable interrupts. */ cpsie i @@ -277,23 +280,26 @@ __asm void prvStartFirstTask( void ) /* Call SVC to start the first task. */ svc 0 nop - nop + nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ __asm void prvEnableVFP( void ) { +/* *INDENT-OFF* */ PRESERVE8 /* The FPU enable bits are in the CPACR. */ - ldr.w r0, = 0xE000ED88 - ldr r1, [ r0 ] + ldr.w r0, =0xE000ED88 + ldr r1, [ r0 ] /* Enable CP10 and CP11 coprocessors, then save back. */ - orr r1, r1, # ( 0xf << 20 ) + orr r1, r1, #( 0xf << 20 ) str r1, [ r0 ] bx r14 nop +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -438,16 +444,17 @@ __asm void xPortPendSVHandler( void ) extern pxCurrentTCB; extern vTaskSwitchContext; +/* *INDENT-OFF* */ PRESERVE8 mrs r0, psp isb /* Get the location of the current TCB. */ - ldr r3, = pxCurrentTCB - ldr r2, [ r3 ] + ldr r3, =pxCurrentTCB + ldr r2, [ r3 ] /* Is the task using the FPU context? If so, push high vfp registers. */ - tst r14, # 0x10 + tst r14, #0x10 it eq vstmdbeq r0 !, { s16 - s31 @@ -464,14 +471,14 @@ __asm void xPortPendSVHandler( void ) stmdb sp !, { r0, r3 } - mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY cpsid i msr basepri, r0 dsb isb cpsie i bl vTaskSwitchContext - mov r0, # 0 + mov r0, #0 msr basepri, r0 ldmia sp !, { r0, r3 @@ -488,14 +495,14 @@ __asm void xPortPendSVHandler( void ) /* Is the task using the FPU context? If so, pop the high vfp registers * too. */ - tst r14, # 0x10 + tst r14, #0x10 it eq vldmiaeq r0 !, { s16 - s31 } msr psp, r0 - isb + isb #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ #if WORKAROUND_PMU_CM001 == 1 push { @@ -509,6 +516,7 @@ __asm void xPortPendSVHandler( void ) #endif bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ @@ -736,10 +744,12 @@ void xPortSysTickHandler( void ) __asm uint32_t vPortGetIPSR( void ) { +/* *INDENT-OFF* */ PRESERVE8 mrs r0, ipsr bx r14 +/* *INDENT-ON* */ } /*-----------------------------------------------------------*/ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c index 900691ca0..28bf0482b 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c @@ -54,7 +54,8 @@ extern void __mw_run_tls_dtor(); extern void __mw_run_tls_ctor(); -extern uint32_t exc_nest_count; + extern uint32_t exc_nest_count; + /* * Linker generated symbols to mark .tls section addresses * first byte .. last byte diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h index 6b52deb2d..5cc3f4665 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h +++ b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h @@ -26,16 +26,18 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H - #ifdef __cplusplus - extern "C" { - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ /* record stack high address for stack check */ - #ifndef configRECORD_STACK_HIGH_ADDRESS - #define configRECORD_STACK_HIGH_ADDRESS 1 - #endif +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 +#endif /*----------------------------------------------------------- * Port specific definitions. @@ -48,78 +50,78 @@ */ /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE unsigned int - #define portBASE_TYPE portLONG +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE portLONG - #ifndef Asm - #define Asm __asm__ volatile - #endif +#ifndef Asm + #define Asm __asm__ volatile +#endif /* * normal constants */ - #ifndef NULL - #define NULL 0 /* invalid pointer */ - #endif /* NULL */ +#ifndef NULL + #define NULL 0 /* invalid pointer */ +#endif /* NULL */ - #ifndef true - #define true 1 /* true */ - #endif /* true */ +#ifndef true + #define true 1 /* true */ +#endif /* true */ - #ifndef false - #define false 0 /* false */ - #endif /* false */ +#ifndef false + #define false 0 /* false */ +#endif /* false */ - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configUSE_16_BIT_TICKS == 1 ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #else - typedef unsigned int TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - #endif +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif - #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 - #define portNOP() Asm( "nop_s" ); - #define IPM_ENABLE_ALL 1 +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() Asm( "nop_s" ); +#define IPM_ENABLE_ALL 1 - #define portYIELD_FROM_ISR() vPortYieldFromIsr() - #define portYIELD() vPortYield() +#define portYIELD_FROM_ISR() vPortYieldFromIsr() +#define portYIELD() vPortYield() /* Critical section management. */ - #define portDISABLE_INTERRUPTS() \ - { \ - Asm( "clri" ); \ - Asm( "" ::: "memory" ); \ - } \ +#define portDISABLE_INTERRUPTS() \ + { \ + Asm( "clri" ); \ + Asm( "" ::: "memory" ); \ + } \ - #define portENABLE_INTERRUPTS() \ - { \ - Asm( "" ::: "memory" ); \ - Asm( "seti" ); \ - } \ +#define portENABLE_INTERRUPTS() \ + { \ + Asm( "" ::: "memory" ); \ + Asm( "seti" ); \ + } \ - extern volatile unsigned int ulCriticalNesting; +extern volatile unsigned int ulCriticalNesting; - #define portENTER_CRITICAL() \ +#define portENTER_CRITICAL() \ { \ portDISABLE_INTERRUPTS() \ ulCriticalNesting++; \ } - #define portEXIT_CRITICAL() \ +#define portEXIT_CRITICAL() \ { \ if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \ { \ @@ -132,24 +134,26 @@ } - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ - #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ +#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) - #if defined( __MW__ ) - extern void task_end_hook( void * pxTCB ); - #define portCLEAN_UP_TCB( pxTCB ) task_end_hook( ( void * ) pxTCB ) - #else - #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB - #endif +#if defined( __MW__ ) + extern void task_end_hook( void * pxTCB ); + #define portCLEAN_UP_TCB( pxTCB ) task_end_hook( ( void * ) pxTCB ) +#else + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif - void vPortYield( void ); - void vPortYieldFromIsr( void ); +void vPortYield( void ); +void vPortYieldFromIsr( void ); - #ifdef __cplusplus - } - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ #endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h index cce0bd02c..dc0c71c6d 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h @@ -64,26 +64,28 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H - #ifdef __cplusplus - extern "C" { - #endif +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ - #ifndef __ASSEMBLER__ +#ifndef __ASSEMBLER__ - #include + #include - #include - #include - #include /* required for XSHAL_CLIB */ - #include - #include "esp_timer.h" /* required for FreeRTOS run time stats */ - #include "esp_system.h" + #include + #include + #include /* required for XSHAL_CLIB */ + #include + #include "esp_timer.h" /* required for FreeRTOS run time stats */ + #include "esp_system.h" - #include - #include "soc/soc_memory_layout.h" + #include + #include "soc/soc_memory_layout.h" /*#include "xtensa_context.h" */ @@ -99,84 +101,84 @@ /* Type definitions. */ - #define portCHAR int8_t - #define portFLOAT float - #define portDOUBLE double - #define portLONG int32_t - #define portSHORT int16_t - #define portSTACK_TYPE uint8_t - #define portBASE_TYPE int + #define portCHAR int8_t + #define portFLOAT float + #define portDOUBLE double + #define portLONG int32_t + #define portSHORT int16_t + #define portSTACK_TYPE uint8_t + #define portBASE_TYPE int - typedef portSTACK_TYPE StackType_t; - typedef portBASE_TYPE BaseType_t; - typedef unsigned portBASE_TYPE UBaseType_t; + typedef portSTACK_TYPE StackType_t; + typedef portBASE_TYPE BaseType_t; + typedef unsigned portBASE_TYPE UBaseType_t; - #if ( configUSE_16_BIT_TICKS == 1 ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #else - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - #endif + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + #endif /*-----------------------------------------------------------*/ /* portbenchmark */ - #include "portbenchmark.h" + #include "portbenchmark.h" - #include "sdkconfig.h" - #include "esp_attr.h" + #include "sdkconfig.h" + #include "esp_attr.h" /* "mux" data structure (spinlock) */ - typedef struct - { - /* owner field values: - * 0 - Uninitialized (invalid) - * portMUX_FREE_VAL - Mux is free, can be locked by either CPU - * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core - * - * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption - */ - uint32_t owner; + typedef struct + { + /* owner field values: + * 0 - Uninitialized (invalid) + * portMUX_FREE_VAL - Mux is free, can be locked by either CPU + * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core + * + * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption + */ + uint32_t owner; - /* count field: - * If mux is unlocked, count should be zero. - * If mux is locked, count is non-zero & represents the number of recursive locks on the mux. - */ - uint32_t count; - #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG - const char * lastLockedFn; - int lastLockedLine; - #endif - } portMUX_TYPE; + /* count field: + * If mux is unlocked, count should be zero. + * If mux is locked, count is non-zero & represents the number of recursive locks on the mux. + */ + uint32_t count; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + const char * lastLockedFn; + int lastLockedLine; + #endif + } portMUX_TYPE; - #define portMUX_FREE_VAL 0xB33FFFFF + #define portMUX_FREE_VAL 0xB33FFFFF /* Special constants for vPortCPUAcquireMutexTimeout() */ - #define portMUX_NO_TIMEOUT ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */ - #define portMUX_TRY_LOCK 0 /* Try to acquire the spinlock a single time only */ + #define portMUX_NO_TIMEOUT ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */ + #define portMUX_TRY_LOCK 0 /* Try to acquire the spinlock a single time only */ /* Keep this in sync with the portMUX_TYPE struct definition please. */ - #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG - #define portMUX_INITIALIZER_UNLOCKED \ - { \ - .owner = portMUX_FREE_VAL, \ - .count = 0, \ + #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG + #define portMUX_INITIALIZER_UNLOCKED \ + { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ } - #else - #define portMUX_INITIALIZER_UNLOCKED \ - { \ - .owner = portMUX_FREE_VAL, \ - .count = 0, \ - .lastLockedFn = "(never locked)", \ - .lastLockedLine = -1 \ + #else + #define portMUX_INITIALIZER_UNLOCKED \ + { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ + .lastLockedFn = "(never locked)", \ + .lastLockedLine = -1 \ } - #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */ + #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */ - #define portASSERT_IF_IN_ISR() vPortAssertIfInISR() - void vPortAssertIfInISR(); + #define portASSERT_IF_IN_ISR() vPortAssertIfInISR() + void vPortAssertIfInISR(); - #define portCRITICAL_NESTING_IN_TCB 1 + #define portCRITICAL_NESTING_IN_TCB 1 /* * Modifications to portENTER_CRITICAL. @@ -204,17 +206,17 @@ * that either function can be called both from ISR as well as task context. This is not standard FreeRTOS * behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations. */ - void vPortCPUInitializeMutex( portMUX_TYPE * mux ); - #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG - #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS - #endif + void vPortCPUInitializeMutex( portMUX_TYPE * mux ); + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS + #endif - void vTaskExitCritical(); - void vTaskEnterCritical(); - static inline void vPortConsumeSpinlockArg( int unused, - ... ) - { - } + void vTaskExitCritical(); + void vTaskEnterCritical(); + static inline void vPortConsumeSpinlockArg( int unused, + ... ) + { + } /** @brief Acquire a portmux spinlock with a timeout * @@ -224,35 +226,35 @@ * * @return true if mutex is successfully acquired, false on timeout. */ - bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, - int timeout_cycles ); - void vPortCPUReleaseMutex( portMUX_TYPE * mux ); + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles ); + void vPortCPUReleaseMutex( portMUX_TYPE * mux ); - #define portENTER_CRITICAL( ... ) do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) - #define portEXIT_CRITICAL( ... ) do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) + #define portENTER_CRITICAL( ... ) do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) + #define portEXIT_CRITICAL( ... ) do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) - #define portENTER_CRITICAL_ISR( mux ) vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT ) - #define portEXIT_CRITICAL_ISR( mux ) vPortCPUReleaseMutex( mux ) + #define portENTER_CRITICAL_ISR( mux ) vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT ) + #define portEXIT_CRITICAL_ISR( mux ) vPortCPUReleaseMutex( mux ) - #define portENTER_CRITICAL_SAFE( mux ) \ - do { \ - if( xPortInIsrContext() ) { \ - portENTER_CRITICAL_ISR( mux ); \ - } \ - else { \ - portENTER_CRITICAL( mux ); \ - } \ + #define portENTER_CRITICAL_SAFE( mux ) \ + do { \ + if( xPortInIsrContext() ) { \ + portENTER_CRITICAL_ISR( mux ); \ + } \ + else { \ + portENTER_CRITICAL( mux ); \ + } \ } while( 0 ) - #define portEXIT_CRITICAL_SAFE( mux ) \ - do { \ - if( xPortInIsrContext() ) { \ - portEXIT_CRITICAL_ISR( mux ); \ - } \ - else { \ - portEXIT_CRITICAL( mux ); \ - } \ + #define portEXIT_CRITICAL_SAFE( mux ) \ + do { \ + if( xPortInIsrContext() ) { \ + portEXIT_CRITICAL_ISR( mux ); \ + } \ + else { \ + portEXIT_CRITICAL( mux ); \ + } \ } while( 0 ) @@ -260,37 +262,37 @@ /* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */ /* */ /* Only applies to one CPU. See notes above & below for reasons not to use these. */ - #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 ) - #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) + #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 ) + #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) /* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */ /* They can be called from interrupts too. */ /* WARNING: Only applies to current CPU. See notes above. */ - static inline unsigned portENTER_CRITICAL_NESTED() - { - unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); + static inline unsigned portENTER_CRITICAL_NESTED() + { + unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); - portbenchmarkINTERRUPT_DISABLE(); - return state; - } - #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 ) + portbenchmarkINTERRUPT_DISABLE(); + return state; + } + #define portEXIT_CRITICAL_NESTED( state ) do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 ) /* These FreeRTOS versions are similar to the nested versions above */ - #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state ) + #define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state ) portEXIT_CRITICAL_NESTED( state ) /*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */ /*the stack memory to always be internal. */ - #define pvPortMallocTcbMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) - #define pvPortMallocStackMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) + #define pvPortMallocTcbMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) + #define pvPortMallocStackMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) /*xTaskCreateStatic uses these functions to check incoming memory. */ - #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) - #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY - #define portVALID_STACK_MEM( ptr ) esp_ptr_byte_accessible( ptr ) - #else - #define portVALID_STACK_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) - #endif + #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) + #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + #define portVALID_STACK_MEM( ptr ) esp_ptr_byte_accessible( ptr ) + #else + #define portVALID_STACK_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) + #endif /* * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare @@ -301,118 +303,118 @@ * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the * ESP32 (portMUX assertions would fail). */ - static inline void uxPortCompareSet( volatile uint32_t * addr, - uint32_t compare, - uint32_t * set ) - { - #if ( XCHAL_HAVE_S32C1I > 0 ) - __asm__ __volatile__ ( - "WSR %2,SCOMPARE1 \n" - "S32C1I %0, %1, 0 \n" - : "=r" ( *set ) - : "r" ( addr ), "r" ( compare ), "0" ( *set ) - ); - #else - /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */ - uint32_t intlevel, old_value; - __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n" - : "=r" ( intlevel ) ); + static inline void uxPortCompareSet( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + #if ( XCHAL_HAVE_S32C1I > 0 ) + __asm__ __volatile__ ( + "WSR %2,SCOMPARE1 \n" + "S32C1I %0, %1, 0 \n" + : "=r" ( *set ) + : "r" ( addr ), "r" ( compare ), "0" ( *set ) + ); + #else + /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */ + uint32_t intlevel, old_value; + __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n" + : "=r" ( intlevel ) ); - old_value = *addr; + old_value = *addr; - if( old_value == compare ) - { - *addr = *set; - } + if( old_value == compare ) + { + *addr = *set; + } - __asm__ __volatile__ ( "memw \n" - "wsr %0, ps\n" - : : "r" ( intlevel ) ); + __asm__ __volatile__ ( "memw \n" + "wsr %0, ps\n" + : : "r" ( intlevel ) ); - *set = old_value; - #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */ - } + *set = old_value; + #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */ + } - void uxPortCompareSetExtram( volatile uint32_t * addr, - uint32_t compare, - uint32_t * set ); + void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ); /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 4 - #define portNOP() XT_NOP() + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 4 + #define portNOP() XT_NOP() /*-----------------------------------------------------------*/ /* Fine resolution time */ - #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() + #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() /*ccount or esp_timer are initialized elsewhere */ - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() - #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER + #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER /* Coarse resolution time (us) */ - #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) x = ( uint32_t ) esp_timer_get_time() - #endif + #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) x = ( uint32_t ) esp_timer_get_time() + #endif /* Kernel utilities. */ - void vPortYield( void ); - void _frxt_setup_switch( void ); - #define portYIELD() vPortYield() - #define portYIELD_FROM_ISR() { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); } + void vPortYield( void ); + void _frxt_setup_switch( void ); + #define portYIELD() vPortYield() + #define portYIELD_FROM_ISR() { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); } - static inline uint32_t xPortGetCoreID(); + static inline uint32_t xPortGetCoreID(); /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /* When coprocessors are defined, we to maintain a pointer to coprocessors area. */ /* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */ /* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */ /* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */ - typedef struct - { - #if XCHAL_CP_NUM > 0 - volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */ - #endif - - #if portUSING_MPU_WRAPPERS - /* Define here mpu_settings, which is port dependent */ - int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */ - #endif - - #if configUSE_TRACE_FACILITY_2 - struct - { - /* Cf. porttraceStamp() */ - int taskstamp; /* Stamp from inside task to see where we are */ - int taskstampcount; /* A counter usually incremented when we restart the task's loop */ - } porttrace; - #endif - } xMPU_SETTINGS; - -/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */ - #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */ - #undef portUSING_MPU_WRAPPERS - #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */ - #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */ - #define PRIVILEGED_FUNCTION - #define PRIVILEGED_DATA + typedef struct + { + #if XCHAL_CP_NUM > 0 + volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */ #endif - bool vApplicationSleep( TickType_t xExpectedIdleTime ); + #if portUSING_MPU_WRAPPERS + /* Define here mpu_settings, which is port dependent */ + int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */ + #endif - #define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime ) + #if configUSE_TRACE_FACILITY_2 + struct + { + /* Cf. porttraceStamp() */ + int taskstamp; /* Stamp from inside task to see where we are */ + int taskstampcount; /* A counter usually incremented when we restart the task's loop */ + } porttrace; + #endif + } xMPU_SETTINGS; + +/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */ + #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */ + #undef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */ + #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #endif + + bool vApplicationSleep( TickType_t xExpectedIdleTime ); + + #define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime ) - void _xt_coproc_release( volatile void * coproc_sa_base ); + void _xt_coproc_release( volatile void * coproc_sa_base ); /* @@ -422,29 +424,29 @@ * non-FreeRTOS-specific code, and behave the same as * pvPortMalloc()/vPortFree(). */ - #define pvPortMalloc heap_caps_malloc_default - #define vPortFree heap_caps_free - #define xPortGetFreeHeapSize esp_get_free_heap_size - #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size + #define pvPortMalloc heap_caps_malloc_default + #define vPortFree heap_caps_free + #define xPortGetFreeHeapSize esp_get_free_heap_size + #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size /* * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack * watchpoint around. */ - void vPortSetStackWatchpoint( void * pxStackStart ); + void vPortSetStackWatchpoint( void * pxStackStart ); /* * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. */ - BaseType_t xPortInIsrContext(); + BaseType_t xPortInIsrContext(); /* * This function will be called in High prio ISRs. Returns true if the current core was in ISR context * before calling into high prio ISR context. */ - BaseType_t xPortInterruptedFromISRContext(); + BaseType_t xPortInterruptedFromISRContext(); /* * The structures and methods of manipulating the MPU are contained within the @@ -453,46 +455,48 @@ * Fills the xMPUSettings structure with the memory region information * contained in xRegions. */ - #if ( portUSING_MPU_WRAPPERS == 1 ) - struct xMEMORY_REGION; - void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, - const struct xMEMORY_REGION * const xRegions, - StackType_t * pxBottomOfStack, - uint32_t usStackDepth ) PRIVILEGED_FUNCTION; - void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings ); - #endif - -/* Multi-core: get current core ID */ - static inline uint32_t IRAM_ATTR xPortGetCoreID() - { - int id; - - asm ( - "rsr.prid %0\n" - " extui %0,%0,13,1" - : "=r" ( id ) ); - return id; - } - -/* Get tick rate per second */ - uint32_t xPortGetTickRateHz( void ); - -/* porttrace */ - #if configUSE_TRACE_FACILITY_2 - #include "porttrace.h" - #endif - -/* configASSERT_2 if requested */ - #if configASSERT_2 - #include - void exit( int ); - #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); } - #endif - - #endif // __ASSEMBLER__ - - #ifdef __cplusplus - } + #if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t usStackDepth ) PRIVILEGED_FUNCTION; + void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings ); #endif +/* Multi-core: get current core ID */ + static inline uint32_t IRAM_ATTR xPortGetCoreID() + { + int id; + + asm ( + "rsr.prid %0\n" + " extui %0,%0,13,1" + : "=r" ( id ) ); + return id; + } + +/* Get tick rate per second */ + uint32_t xPortGetTickRateHz( void ); + +/* porttrace */ + #if configUSE_TRACE_FACILITY_2 + #include "porttrace.h" + #endif + +/* configASSERT_2 if requested */ + #if configASSERT_2 + #include + void exit( int ); + #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); } + #endif + +#endif // __ASSEMBLER__ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + #endif /* PORTMACRO_H */