mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2026-01-22 01:30:31 -05:00
* Revert "Remove coroutines (#874)"
This reverts commit 569c78fd8c.
* Update freertos Kernel submodule to latest head
* Remove temporary files
* Fix MingW demos and spell check
* Fix manifest version; fix headers
* Add ignore files and paths to core-checker.py
* Fix copyright in remaining files
* Fix PR check build failure
1. Remove defining `inline` in Makefile. This was causing build
warnings.
2. Ensure that the linker removed unused functions from various
compilation units.
3. Update the linker script so that all the functions are correctly
placed in FLASH section.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---------
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Aniruddha Kanhere
GitHub
parent
9ccae851e7
commit
1277ba1661
605 changed files with 11240 additions and 3628 deletions
|
|
@ -36,7 +36,7 @@
|
|||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html
|
||||
*----------------------------------------------------------*/
|
||||
|
|
@ -60,6 +60,9 @@
|
|||
#define configUSE_FPU 1
|
||||
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 4 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
|
|
|||
|
|
@ -27,36 +27,36 @@
|
|||
/*
|
||||
* Tests the floating point context save and restore mechanism.
|
||||
*
|
||||
* Two tasks are created - each of which is allocated a buffer of
|
||||
* Two tasks are created - each of which is allocated a buffer of
|
||||
* portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context
|
||||
* of the task is saved when the task is switched out, and from which the
|
||||
* flop context of the task is restored when the task is switch in. Prior to
|
||||
* the tasks being created each position in the two buffers is filled with a
|
||||
* flop context of the task is restored when the task is switch in. Prior to
|
||||
* the tasks being created each position in the two buffers is filled with a
|
||||
* unique value - this way the flop context of each task is different.
|
||||
*
|
||||
* The two test tasks never block so are always in either the Running or
|
||||
* Ready state. They execute at the lowest priority so will get pre-empted
|
||||
* regularly, although the yield frequently so will not get much execution
|
||||
* time. The lack of execution time is not a problem as its only the
|
||||
* time. The lack of execution time is not a problem as its only the
|
||||
* switching in and out that is being tested.
|
||||
*
|
||||
* Whenever a task is moved from the Ready to the Running state its flop
|
||||
* Whenever a task is moved from the Ready to the Running state its flop
|
||||
* context will be loaded from the buffer, but while the task is in the
|
||||
* Running state the buffer is not used and can contain any value - in this
|
||||
* case and for test purposes the task itself clears the buffer to zero.
|
||||
* case and for test purposes the task itself clears the buffer to zero.
|
||||
* The next time the task is moved out of the Running state into the
|
||||
* Ready state the flop context will once more get saved to the buffer -
|
||||
* Ready state the flop context will once more get saved to the buffer -
|
||||
* overwriting the zeros.
|
||||
*
|
||||
* Therefore whenever the task is not in the Running state its buffer contains
|
||||
* the most recent values of its floating point registers - the zeroing out
|
||||
* of the buffer while the task was executing being used to ensure the values
|
||||
* of the buffer while the task was executing being used to ensure the values
|
||||
* the buffer contains are not stale.
|
||||
*
|
||||
* When neither test task is in the Running state the buffers should contain
|
||||
* the unique values allocated before the tasks were created. If so then
|
||||
* the floating point context has been maintained. This check is performed
|
||||
* by the 'check' task (defined in main.c) by calling
|
||||
* by the 'check' task (defined in main.c) by calling
|
||||
* xAreFlopRegisterTestsStillRunning().
|
||||
*
|
||||
* The test tasks also increment a value each time they execute.
|
||||
|
|
@ -84,7 +84,7 @@ static void vFlopTest2( void *pvParameters );
|
|||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Buffers into which the flop registers will be saved. There is a buffer for
|
||||
/* Buffers into which the flop registers will be saved. There is a buffer for
|
||||
both tasks. */
|
||||
static volatile unsigned long ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ];
|
||||
|
||||
|
|
@ -99,7 +99,7 @@ void vStartFlopRegTests( void )
|
|||
TaskHandle_t xTaskJustCreated;
|
||||
unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
|
||||
|
||||
/* Fill the arrays into which the flop registers are to be saved with
|
||||
/* Fill the arrays into which the flop registers are to be saved with
|
||||
known values. These are the values that will be written to the flop
|
||||
registers when the tasks start, and as the tasks do not perform any
|
||||
flop operations the values should never change. Each position in the
|
||||
|
|
@ -118,7 +118,7 @@ unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
|
|||
/* Create the first task. */
|
||||
xTaskCreate( vFlopTest1, "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated );
|
||||
|
||||
/* The task tag value is a value that can be associated with a task, but
|
||||
/* The task tag value is a value that can be associated with a task, but
|
||||
is not used by the scheduler itself. Its use is down to the application so
|
||||
it makes a convenient place in this case to store the pointer to the buffer
|
||||
into which the flop context of the task will be stored. The first created
|
||||
|
|
@ -146,7 +146,7 @@ static void vFlopTest1( void *pvParameters )
|
|||
memset( ( void * ) ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) );
|
||||
portEXIT_CRITICAL();
|
||||
|
||||
/* We don't have to do anything other than indicate that we are
|
||||
/* We don't have to do anything other than indicate that we are
|
||||
still running. */
|
||||
ulFlop1CycleCount++;
|
||||
taskYIELD();
|
||||
|
|
@ -168,7 +168,7 @@ static void vFlopTest2( void *pvParameters )
|
|||
memset( ( void * ) ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) );
|
||||
portEXIT_CRITICAL();
|
||||
|
||||
/* We don't have to do anything other than indicate that we are
|
||||
/* We don't have to do anything other than indicate that we are
|
||||
still running. */
|
||||
ulFlop2CycleCount++;
|
||||
taskYIELD();
|
||||
|
|
@ -183,7 +183,7 @@ unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
|
|||
static unsigned long ulLastFlop1CycleCount = 0, ulLastFlop2CycleCount = 0;
|
||||
|
||||
/* Called from the 'check' task.
|
||||
|
||||
|
||||
The flop tasks cannot be currently running, check their saved registers
|
||||
are as expected. The tests tasks do not perform any flop operations so
|
||||
their registers should be as per their initial setting. */
|
||||
|
|
|
|||
|
|
@ -28,12 +28,12 @@
|
|||
* Creates eight tasks, each of which loops continuously performing a
|
||||
* floating point calculation.
|
||||
*
|
||||
* All the tasks run at the idle priority and never block or yield. This causes
|
||||
* all eight tasks to time slice with the idle task. Running at the idle priority
|
||||
* All the tasks run at the idle priority and never block or yield. This causes
|
||||
* all eight tasks to time slice with the idle task. Running at the idle priority
|
||||
* means that these tasks will get pre-empted any time another task is ready to run
|
||||
* or a time slice occurs. More often than not the pre-emption will occur mid
|
||||
* calculation, creating a good test of the schedulers context switch mechanism - a
|
||||
* calculation producing an unexpected result could be a symptom of a corruption in
|
||||
* or a time slice occurs. More often than not the pre-emption will occur mid
|
||||
* calculation, creating a good test of the schedulers context switch mechanism - a
|
||||
* calculation producing an unexpected result could be a symptom of a corruption in
|
||||
* the context of a task.
|
||||
*
|
||||
* This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and
|
||||
|
|
@ -54,18 +54,18 @@
|
|||
#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
|
||||
#define mathNUMBER_OF_TASKS ( 8 )
|
||||
|
||||
/* Four tasks, each of which performs a different floating point calculation.
|
||||
/* Four tasks, each of which performs a different floating point calculation.
|
||||
Each of the four is created twice. */
|
||||
static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
|
||||
static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
|
||||
static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
|
||||
static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
|
||||
|
||||
/* These variables are used to check that all the tasks are still running. If a
|
||||
/* These variables are used to check that all the tasks are still running. If a
|
||||
task gets a calculation wrong it will stop incrementing its check variable. */
|
||||
static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
|
||||
|
||||
/* Buffers into which the flop registers will be saved. There is a buffer for
|
||||
/* Buffers into which the flop registers will be saved. There is a buffer for
|
||||
each task created within this file. Zeroing out this array is the normal and
|
||||
safe option as this will cause the task to start with all zeros in its flop
|
||||
context. */
|
||||
|
|
@ -78,11 +78,11 @@ void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
|
|||
TaskHandle_t xTaskJustCreated;
|
||||
portBASE_TYPE x, y;
|
||||
|
||||
/* Place known values into the buffers into which the flop registers are
|
||||
/* Place known values into the buffers into which the flop registers are
|
||||
to be saved. This is for debug purposes only, it is not normally
|
||||
required. The last position in each array is left at zero as the status
|
||||
register will be loaded from there.
|
||||
|
||||
register will be loaded from there.
|
||||
|
||||
It is intended that these values can be viewed being loaded into the
|
||||
flop registers when a task is started - however the Insight debugger
|
||||
does not seem to want to show the flop register values. */
|
||||
|
|
@ -95,11 +95,11 @@ portBASE_TYPE x, y;
|
|||
}
|
||||
|
||||
/* Create the first task - passing it the address of the check variable
|
||||
that it is going to increment. This check variable is used as an
|
||||
that it is going to increment. This check variable is used as an
|
||||
indication that the task is still running. */
|
||||
xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated );
|
||||
|
||||
/* The task tag value is a value that can be associated with a task, but
|
||||
/* The task tag value is a value that can be associated with a task, but
|
||||
is not used by the scheduler itself. Its use is down to the application so
|
||||
it makes a convenient place in this case to store the pointer to the buffer
|
||||
into which the flop context of the task will be stored. The first created
|
||||
|
|
@ -143,7 +143,7 @@ short sError = pdFALSE;
|
|||
|
||||
fAnswer = ( ff1 + ff2 ) * ff3;
|
||||
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
as the parameter. */
|
||||
pusTaskCheckVariable = ( unsigned short * ) pvParameters;
|
||||
|
||||
|
|
@ -160,7 +160,7 @@ short sError = pdFALSE;
|
|||
taskYIELD();
|
||||
#endif
|
||||
|
||||
/* If the calculation does not match the expected constant, stop the
|
||||
/* If the calculation does not match the expected constant, stop the
|
||||
increment of the check variable. */
|
||||
if( fabs( ff4 - fAnswer ) > 0.001F )
|
||||
{
|
||||
|
|
@ -169,7 +169,7 @@ short sError = pdFALSE;
|
|||
|
||||
if( sError == pdFALSE )
|
||||
{
|
||||
/* If the calculation has always been correct, increment the check
|
||||
/* If the calculation has always been correct, increment the check
|
||||
variable so we know this task is still running okay. */
|
||||
( *pusTaskCheckVariable )++;
|
||||
}
|
||||
|
|
@ -196,7 +196,7 @@ short sError = pdFALSE;
|
|||
fAnswer = ( ff1 / ff2 ) * ff3;
|
||||
|
||||
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
as the parameter. */
|
||||
pusTaskCheckVariable = ( unsigned short * ) pvParameters;
|
||||
|
||||
|
|
@ -212,8 +212,8 @@ short sError = pdFALSE;
|
|||
#if configUSE_PREEMPTION == 0
|
||||
taskYIELD();
|
||||
#endif
|
||||
|
||||
/* If the calculation does not match the expected constant, stop the
|
||||
|
||||
/* If the calculation does not match the expected constant, stop the
|
||||
increment of the check variable. */
|
||||
if( fabs( ff4 - fAnswer ) > 0.001F )
|
||||
{
|
||||
|
|
@ -222,7 +222,7 @@ short sError = pdFALSE;
|
|||
|
||||
if( sError == pdFALSE )
|
||||
{
|
||||
/* If the calculation has always been correct, increment the check
|
||||
/* If the calculation has always been correct, increment the check
|
||||
variable so we know
|
||||
this task is still running okay. */
|
||||
( *pusTaskCheckVariable )++;
|
||||
|
|
@ -243,14 +243,14 @@ const size_t xArraySize = 10;
|
|||
size_t xPosition;
|
||||
short sError = pdFALSE;
|
||||
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
as the parameter. */
|
||||
pusTaskCheckVariable = ( unsigned short * ) pvParameters;
|
||||
|
||||
pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) );
|
||||
|
||||
/* Keep filling an array, keeping a running total of the values placed in the
|
||||
array. Then run through the array adding up all the values. If the two totals
|
||||
/* Keep filling an array, keeping a running total of the values placed in the
|
||||
array. Then run through the array adding up all the values. If the two totals
|
||||
do not match, stop the check variable from incrementing. */
|
||||
for( ;; )
|
||||
{
|
||||
|
|
@ -260,7 +260,7 @@ short sError = pdFALSE;
|
|||
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
|
||||
{
|
||||
pfArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5F;
|
||||
fTotal1 += ( portFLOAT ) xPosition + 5.5F;
|
||||
fTotal1 += ( portFLOAT ) xPosition + 5.5F;
|
||||
}
|
||||
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
|
@ -284,7 +284,7 @@ short sError = pdFALSE;
|
|||
|
||||
if( sError == pdFALSE )
|
||||
{
|
||||
/* If the calculation has always been correct, increment the check
|
||||
/* If the calculation has always been correct, increment the check
|
||||
variable so we know this task is still running okay. */
|
||||
( *pusTaskCheckVariable )++;
|
||||
}
|
||||
|
|
@ -300,14 +300,14 @@ const size_t xArraySize = 10;
|
|||
size_t xPosition;
|
||||
short sError = pdFALSE;
|
||||
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
/* The variable this task increments to show it is still running is passed in
|
||||
as the parameter. */
|
||||
pusTaskCheckVariable = ( unsigned short * ) pvParameters;
|
||||
|
||||
pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) );
|
||||
|
||||
/* Keep filling an array, keeping a running total of the values placed in the
|
||||
array. Then run through the array adding up all the values. If the two totals
|
||||
/* Keep filling an array, keeping a running total of the values placed in the
|
||||
array. Then run through the array adding up all the values. If the two totals
|
||||
do not match, stop the check variable from incrementing. */
|
||||
for( ;; )
|
||||
{
|
||||
|
|
@ -317,7 +317,7 @@ short sError = pdFALSE;
|
|||
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
|
||||
{
|
||||
pfArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123F;
|
||||
fTotal1 += ( portFLOAT ) xPosition * 12.123F;
|
||||
fTotal1 += ( portFLOAT ) xPosition * 12.123F;
|
||||
}
|
||||
|
||||
#if configUSE_PREEMPTION == 0
|
||||
|
|
@ -341,23 +341,23 @@ short sError = pdFALSE;
|
|||
|
||||
if( sError == pdFALSE )
|
||||
{
|
||||
/* If the calculation has always been correct, increment the check
|
||||
/* If the calculation has always been correct, increment the check
|
||||
variable so we know this task is still running okay. */
|
||||
( *pusTaskCheckVariable )++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This is called to check that all the created tasks are still running. */
|
||||
portBASE_TYPE xAreMathsTaskStillRunning( void )
|
||||
{
|
||||
/* Keep a history of the check variables so we know if they have been incremented
|
||||
/* Keep a history of the check variables so we know if they have been incremented
|
||||
since the last call. */
|
||||
static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
|
||||
portBASE_TYPE xReturn = pdTRUE, xTask;
|
||||
|
||||
/* Check the maths tasks are still running by ensuring their check variables
|
||||
/* Check the maths tasks are still running by ensuring their check variables
|
||||
are still incrementing. */
|
||||
for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
|
||||
{
|
||||
|
|
|
|||
|
|
@ -27,19 +27,19 @@
|
|||
/*
|
||||
* Creates all the demo application tasks, then starts the scheduler. The WEB
|
||||
* documentation provides more details of the demo application tasks.
|
||||
*
|
||||
*
|
||||
* In addition to the standard demo tasks, the follow demo specific tasks are
|
||||
* create:
|
||||
*
|
||||
* The "Check" task. This only executes every three seconds but has the highest
|
||||
* priority so is guaranteed to get processor time. Its main function is to
|
||||
* check that all the other tasks are still operational. Most tasks maintain
|
||||
* a unique count that is incremented each time the task successfully completes
|
||||
* its function. Should any error occur within such a task the count is
|
||||
* permanently halted. The check task inspects the count of each task to ensure
|
||||
* it has changed since the last time the check task executed. If all the count
|
||||
* variables have changed all the tasks are still executing error free, and the
|
||||
* check task toggles the onboard LED. Should any task contain an error at any time
|
||||
* The "Check" task. This only executes every three seconds but has the highest
|
||||
* priority so is guaranteed to get processor time. Its main function is to
|
||||
* check that all the other tasks are still operational. Most tasks maintain
|
||||
* a unique count that is incremented each time the task successfully completes
|
||||
* its function. Should any error occur within such a task the count is
|
||||
* permanently halted. The check task inspects the count of each task to ensure
|
||||
* it has changed since the last time the check task executed. If all the count
|
||||
* variables have changed all the tasks are still executing error free, and the
|
||||
* check task toggles the onboard LED. Should any task contain an error at any time
|
||||
* the LED toggle rate will change from 3 seconds to 500ms.
|
||||
*
|
||||
* The "Register Check" tasks. These tasks fill the CPU registers with known
|
||||
|
|
@ -96,15 +96,15 @@ baud rate parameters passed into the comtest initialisation has no effect. */
|
|||
|
||||
/* Delay periods used by the check task. If no errors have been found then
|
||||
the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an
|
||||
error has been found at any time then the toggle rate will increase to
|
||||
error has been found at any time then the toggle rate will increase to
|
||||
mainERROR_CHECK_DELAY milliseconds. */
|
||||
#define mainNO_ERROR_CHECK_DELAY ( ( TickType_t ) 3000 / portTICK_PERIOD_MS )
|
||||
#define mainERROR_CHECK_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
|
||||
|
||||
|
||||
/*
|
||||
/*
|
||||
* The tasks defined within this file - described within the comments at the
|
||||
* head of this page.
|
||||
* head of this page.
|
||||
*/
|
||||
static void prvRegTestTask1( void *pvParameters );
|
||||
static void prvRegTestTask2( void *pvParameters );
|
||||
|
|
@ -145,12 +145,12 @@ int main( void )
|
|||
/* Start the standard demo application tasks. Note that the baud rate used
|
||||
by the comtest tasks is set by the hardware, so the baud rate parameter
|
||||
passed has no effect. */
|
||||
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
|
||||
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED );
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY );
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY );
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );
|
||||
vStartQueuePeekTasks();
|
||||
vCreateBlockTimeTasks();
|
||||
|
|
@ -173,10 +173,10 @@ int main( void )
|
|||
vCreateSuicidalTasks( mainDEATH_PRIORITY );
|
||||
|
||||
/* Now start the scheduler. Following this call the created tasks should
|
||||
be executing. */
|
||||
be executing. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* vTaskStartScheduler() will only return if an error occurs while the
|
||||
/* vTaskStartScheduler() will only return if an error occurs while the
|
||||
idle task is being created. */
|
||||
for( ;; );
|
||||
|
||||
|
|
@ -190,7 +190,7 @@ portBASE_TYPE lReturn = pdPASS;
|
|||
static unsigned long ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL;
|
||||
|
||||
/* The demo tasks maintain a count that increments every cycle of the task
|
||||
provided that the task has never encountered an error. This function
|
||||
provided that the task has never encountered an error. This function
|
||||
checks the counts maintained by the tasks to ensure they are still being
|
||||
incremented. A count remaining at the same value between calls therefore
|
||||
indicates that an error has been detected. */
|
||||
|
|
@ -204,37 +204,37 @@ static unsigned long ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL;
|
|||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xIsCreateTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
}
|
||||
|
||||
|
||||
if( xAreQueuePeekTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
lReturn = pdFAIL;
|
||||
|
|
@ -319,14 +319,14 @@ volatile unsigned portBASE_TYPE uxFreeStack;
|
|||
uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
|
||||
|
||||
/* Wait until it is time to check again. The time we wait here depends
|
||||
on whether an error has been detected or not. When an error is
|
||||
on whether an error has been detected or not. When an error is
|
||||
detected the time is shortened resulting in a faster LED flash rate. */
|
||||
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
|
||||
|
||||
/* See if the other tasks are all ok. */
|
||||
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
|
||||
{
|
||||
/* An error occurred in one of the tasks so shorten the delay
|
||||
/* An error occurred in one of the tasks so shorten the delay
|
||||
period - which has the effect of increasing the frequency of the
|
||||
LED toggle. */
|
||||
xDelayPeriod = mainERROR_CHECK_DELAY;
|
||||
|
|
@ -378,7 +378,7 @@ static void prvRegTestTask1( void *pvParameters )
|
|||
( void ) pvParameters;
|
||||
|
||||
/* The first register test task as described at the top of this file. The
|
||||
values used in the registers are different to those use in the second
|
||||
values used in the registers are different to those use in the second
|
||||
register test task. Also, unlike the second register test task, this task
|
||||
yields between setting the register values and subsequently checking the
|
||||
register values. */
|
||||
|
|
@ -518,7 +518,7 @@ static void prvRegTestTask2( void *pvParameters )
|
|||
/* Just to remove compiler warning. */
|
||||
( void ) pvParameters;
|
||||
|
||||
/* The second register test task as described at the top of this file.
|
||||
/* The second register test task as described at the top of this file.
|
||||
Note that this task fills the registers with different values to the
|
||||
first register test task. */
|
||||
asm volatile
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
#define partstCHANNEL_1 0x01
|
||||
#define partstMAX_8BIT_LED 0x07
|
||||
|
||||
/* The outputs are split into two IO sections, these variables maintain the
|
||||
/* The outputs are split into two IO sections, these variables maintain the
|
||||
current value of either section. */
|
||||
static unsigned portBASE_TYPE uxCurrentOutput8Bit, uxCurrentOutput5Bit;
|
||||
|
||||
|
|
@ -74,7 +74,7 @@ unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
|
|||
{
|
||||
uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR;
|
||||
puxCurrentValue = &uxCurrentOutput5Bit;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
|
||||
|
|
@ -115,7 +115,7 @@ unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
|
|||
|
||||
uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR;
|
||||
puxCurrentValue = &uxCurrentOutput5Bit;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
*/
|
||||
|
||||
|
||||
/*
|
||||
/*
|
||||
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
|
||||
*/
|
||||
|
||||
|
|
@ -46,8 +46,8 @@
|
|||
|
||||
/* Queues used to hold received characters, and characters waiting to be
|
||||
transmitted. */
|
||||
static QueueHandle_t xRxedChars;
|
||||
static QueueHandle_t xCharsForTx;
|
||||
static QueueHandle_t xRxedChars;
|
||||
static QueueHandle_t xCharsForTx;
|
||||
|
||||
/* Structure that maintains information on the UART being used. */
|
||||
static XUartLite xUART;
|
||||
|
|
@ -82,13 +82,13 @@ xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned port
|
|||
|
||||
if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_1_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS )
|
||||
{
|
||||
/* xPortInstallInterruptHandler() could fail if
|
||||
vPortSetupInterruptController() has not been called prior to this
|
||||
/* xPortInstallInterruptHandler() could fail if
|
||||
vPortSetupInterruptController() has not been called prior to this
|
||||
function. */
|
||||
XUartLite_EnableInterrupt( &xUART );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* There is only one port so the handle is not used. */
|
||||
return ( xComPortHandle ) 0;
|
||||
}
|
||||
|
|
@ -131,17 +131,17 @@ portBASE_TYPE xReturn = pdTRUE;
|
|||
}
|
||||
}
|
||||
/* Otherwise, if there is data already in the queue we should add the
|
||||
new data to the back of the queue to ensure the sequencing is
|
||||
new data to the back of the queue to ensure the sequencing is
|
||||
maintained. */
|
||||
else if( uxQueueMessagesWaiting( xCharsForTx ) )
|
||||
{
|
||||
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* If the UART FIFO is not full and there is no data already in the
|
||||
queue we can write directly to the FIFO without disrupting the
|
||||
queue we can write directly to the FIFO without disrupting the
|
||||
sequence. */
|
||||
else
|
||||
{
|
||||
|
|
@ -179,13 +179,13 @@ char cChar;
|
|||
if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 )
|
||||
{
|
||||
/* A character is available - place it in the queue of received
|
||||
characters. This might wake a task that was blocked waiting for
|
||||
characters. This might wake a task that was blocked waiting for
|
||||
data. */
|
||||
cChar = ( char ) XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_RX_FIFO_OFFSET );
|
||||
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
|
||||
lDidSomething = pdTRUE;
|
||||
}
|
||||
|
||||
|
||||
if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
|
||||
{
|
||||
/* There is space in the FIFO - if there are any characters queue for
|
||||
|
|
@ -195,7 +195,7 @@ char cChar;
|
|||
{
|
||||
XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
|
||||
lDidSomething = pdTRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
} while( lDidSomething == pdTRUE );
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,474 @@
|
|||
|
||||
# ##############################################################################
|
||||
# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1
|
||||
# Sat Jun 13 13:14:11 2009
|
||||
# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A
|
||||
# Family: virtex5
|
||||
# Device: xc5vfx70t
|
||||
# Package: ff1136
|
||||
# Speed Grade: -1
|
||||
# Processor number: 1
|
||||
# Processor 1: ppc440_0
|
||||
# Processor clock frequency: 125.0
|
||||
# Bus clock frequency: 125.0
|
||||
# Debug Interface: FPGA JTAG
|
||||
# ##############################################################################
|
||||
PARAMETER VERSION = 2.1.0
|
||||
|
||||
|
||||
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
|
||||
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
|
||||
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
|
||||
PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
|
||||
PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]
|
||||
PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
|
||||
PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
|
||||
PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
|
||||
PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
|
||||
PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
|
||||
PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
|
||||
PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
|
||||
PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
|
||||
PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
|
||||
PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
|
||||
PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
|
||||
PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
|
||||
PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I
|
||||
PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I
|
||||
PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O
|
||||
PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O
|
||||
PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
|
||||
PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
|
||||
PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
|
||||
PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
|
||||
PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
|
||||
PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
|
||||
PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
|
||||
PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
|
||||
PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
|
||||
PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
|
||||
PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]
|
||||
PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
|
||||
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
|
||||
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
|
||||
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
|
||||
PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
|
||||
PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK
|
||||
|
||||
|
||||
BEGIN ppc440_virtex5
|
||||
PARAMETER INSTANCE = ppc440_0
|
||||
PARAMETER C_IDCR_BASEADDR = 0b0000000000
|
||||
PARAMETER C_IDCR_HIGHADDR = 0b0011111111
|
||||
PARAMETER C_APU_CONTROL = 0b00000010000000001
|
||||
PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
|
||||
PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
|
||||
PARAMETER C_PPC440MC_CONTROL = 0xF810008F
|
||||
PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
|
||||
PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
|
||||
PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
|
||||
PARAMETER HW_VER = 1.01.a
|
||||
PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
|
||||
PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
|
||||
PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000
|
||||
PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff
|
||||
BUS_INTERFACE MPLB = plb_v46_0
|
||||
BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
|
||||
BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
|
||||
BUS_INTERFACE MFCB = ppc440_0_fcb_v20
|
||||
BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
|
||||
BUS_INTERFACE RESETPPC = ppc_reset_bus
|
||||
PORT CPMC440CLK = clk_125_0000MHzPLL0
|
||||
PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
|
||||
PORT CPMINTERCONNECTCLKNTO1 = net_vcc
|
||||
PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
|
||||
PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST
|
||||
END
|
||||
|
||||
BEGIN plb_v46
|
||||
PARAMETER INSTANCE = plb_v46_0
|
||||
PARAMETER C_DCR_INTFCE = 0
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 1.04.a
|
||||
PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT SYS_Rst = sys_bus_reset
|
||||
END
|
||||
|
||||
BEGIN xps_bram_if_cntlr
|
||||
PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
||||
PARAMETER C_SPLB_NATIVE_DWIDTH = 64
|
||||
PARAMETER C_SPLB_SUPPORT_BURSTS = 1
|
||||
PARAMETER C_SPLB_P2P = 0
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 1.00.b
|
||||
PARAMETER C_BASEADDR = 0xffffe000
|
||||
PARAMETER C_HIGHADDR = 0xffffffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
||||
END
|
||||
|
||||
BEGIN bram_block
|
||||
PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 1.00.a
|
||||
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
||||
END
|
||||
|
||||
BEGIN xps_uartlite
|
||||
PARAMETER INSTANCE = RS232_Uart_1
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_BAUDRATE = 9600
|
||||
PARAMETER C_DATA_BITS = 8
|
||||
PARAMETER C_USE_PARITY = 0
|
||||
PARAMETER C_ODD_PARITY = 0
|
||||
PARAMETER HW_VER = 1.01.a
|
||||
PARAMETER C_BASEADDR = 0x84000000
|
||||
PARAMETER C_HIGHADDR = 0x8400ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT RX = fpga_0_RS232_Uart_1_RX_pin
|
||||
PORT TX = fpga_0_RS232_Uart_1_TX_pin
|
||||
PORT Interrupt = RS232_Uart_1_Interrupt
|
||||
END
|
||||
|
||||
BEGIN xps_gpio
|
||||
PARAMETER INSTANCE = LEDs_8Bit
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_ALL_INPUTS = 0
|
||||
PARAMETER C_GPIO_WIDTH = 8
|
||||
PARAMETER C_INTERRUPT_PRESENT = 0
|
||||
PARAMETER C_IS_DUAL = 0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_BASEADDR = 0x81440000
|
||||
PARAMETER C_HIGHADDR = 0x8144ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
|
||||
END
|
||||
|
||||
BEGIN xps_gpio
|
||||
PARAMETER INSTANCE = LEDs_Positions
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_ALL_INPUTS = 0
|
||||
PARAMETER C_GPIO_WIDTH = 5
|
||||
PARAMETER C_INTERRUPT_PRESENT = 0
|
||||
PARAMETER C_IS_DUAL = 0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_BASEADDR = 0x81420000
|
||||
PARAMETER C_HIGHADDR = 0x8142ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
|
||||
END
|
||||
|
||||
BEGIN xps_gpio
|
||||
PARAMETER INSTANCE = Push_Buttons_5Bit
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_ALL_INPUTS = 1
|
||||
PARAMETER C_GPIO_WIDTH = 5
|
||||
PARAMETER C_INTERRUPT_PRESENT = 0
|
||||
PARAMETER C_IS_DUAL = 0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_BASEADDR = 0x81400000
|
||||
PARAMETER C_HIGHADDR = 0x8140ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
|
||||
END
|
||||
|
||||
BEGIN xps_gpio
|
||||
PARAMETER INSTANCE = DIP_Switches_8Bit
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_ALL_INPUTS = 1
|
||||
PARAMETER C_GPIO_WIDTH = 8
|
||||
PARAMETER C_INTERRUPT_PRESENT = 0
|
||||
PARAMETER C_IS_DUAL = 0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_BASEADDR = 0x81460000
|
||||
PARAMETER C_HIGHADDR = 0x8146ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin
|
||||
END
|
||||
|
||||
BEGIN xps_iic
|
||||
PARAMETER INSTANCE = IIC_EEPROM
|
||||
PARAMETER C_IIC_FREQ = 100000
|
||||
PARAMETER C_TEN_BIT_ADR = 0
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 2.01.a
|
||||
PARAMETER C_BASEADDR = 0x81600000
|
||||
PARAMETER C_HIGHADDR = 0x8160ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
|
||||
PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
|
||||
END
|
||||
|
||||
BEGIN xps_mch_emc
|
||||
PARAMETER INSTANCE = SRAM
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_NUM_BANKS_MEM = 1
|
||||
PARAMETER C_NUM_CHANNELS = 0
|
||||
PARAMETER C_MEM0_WIDTH = 32
|
||||
PARAMETER C_MAX_MEM_WIDTH = 32
|
||||
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
|
||||
PARAMETER C_SYNCH_MEM_0 = 1
|
||||
PARAMETER C_TCEDV_PS_MEM_0 = 0
|
||||
PARAMETER C_TAVDV_PS_MEM_0 = 0
|
||||
PARAMETER C_THZCE_PS_MEM_0 = 0
|
||||
PARAMETER C_THZOE_PS_MEM_0 = 0
|
||||
PARAMETER C_TWC_PS_MEM_0 = 0
|
||||
PARAMETER C_TWP_PS_MEM_0 = 0
|
||||
PARAMETER C_TLZWE_PS_MEM_0 = 0
|
||||
PARAMETER HW_VER = 3.00.a
|
||||
PARAMETER C_MEM0_BASEADDR = 0xf8000000
|
||||
PARAMETER C_MEM0_HIGHADDR = 0xf80fffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT RdClk = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
|
||||
PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
|
||||
PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
|
||||
PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
|
||||
PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
|
||||
PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
|
||||
PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
|
||||
END
|
||||
|
||||
BEGIN plbv46_pcie
|
||||
PARAMETER INSTANCE = PCIe_Bridge
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER C_IPIFBAR_NUM = 2
|
||||
PARAMETER C_PCIBAR_NUM = 1
|
||||
PARAMETER C_DEVICE_ID = 0x0505
|
||||
PARAMETER C_VENDOR_ID = 0x10EE
|
||||
PARAMETER C_CLASS_CODE = 0x058000
|
||||
PARAMETER C_REV_ID = 0x00
|
||||
PARAMETER C_SUBSYSTEM_ID = 0x0000
|
||||
PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000
|
||||
PARAMETER C_COMP_TIMEOUT = 1
|
||||
PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
|
||||
PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
|
||||
PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000
|
||||
PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000
|
||||
PARAMETER C_PCIBAR_LEN_0 = 20
|
||||
PARAMETER C_PCIBAR_LEN_1 = 28
|
||||
PARAMETER C_BOARD = ml507
|
||||
PARAMETER HW_VER = 3.00.b
|
||||
PARAMETER C_BASEADDR = 0x85c00000
|
||||
PARAMETER C_HIGHADDR = 0x85c0ffff
|
||||
PARAMETER C_IPIFBAR_0 = 0xc0000000
|
||||
PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
|
||||
PARAMETER C_IPIFBAR_1 = 0xe0000000
|
||||
PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
BUS_INTERFACE MPLB = ppc440_0_SPLB0
|
||||
PORT PERSTN = net_vcc
|
||||
PORT REFCLK = PCIe_Diff_Clk
|
||||
PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
|
||||
PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
|
||||
PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
|
||||
PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
|
||||
PORT MSI_request = net_gnd
|
||||
END
|
||||
|
||||
BEGIN plb_v46
|
||||
PARAMETER INSTANCE = ppc440_0_SPLB0
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 1.04.a
|
||||
PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT SYS_Rst = sys_bus_reset
|
||||
END
|
||||
|
||||
BEGIN xps_ethernetlite
|
||||
PARAMETER INSTANCE = Ethernet_MAC
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 2.01.a
|
||||
PARAMETER C_BASEADDR = 0x81000000
|
||||
PARAMETER C_HIGHADDR = 0x8100ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
|
||||
PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
|
||||
PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
|
||||
PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
|
||||
PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
|
||||
PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
|
||||
PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
|
||||
PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
|
||||
PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
|
||||
PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
|
||||
END
|
||||
|
||||
BEGIN ppc440mc_ddr2
|
||||
PARAMETER INSTANCE = DDR2_SDRAM
|
||||
PARAMETER C_DDR_BAWIDTH = 2
|
||||
PARAMETER C_NUM_CLK_PAIRS = 2
|
||||
PARAMETER C_DDR_DWIDTH = 64
|
||||
PARAMETER C_DDR_CAWIDTH = 10
|
||||
PARAMETER C_NUM_RANKS_MEM = 1
|
||||
PARAMETER C_CS_BITS = 0
|
||||
PARAMETER C_DDR_DM_WIDTH = 8
|
||||
PARAMETER C_DQ_BITS = 8
|
||||
PARAMETER C_DDR2_ODT_WIDTH = 2
|
||||
PARAMETER C_DDR2_ADDT_LAT = 0
|
||||
PARAMETER C_INCLUDE_ECC_SUPPORT = 0
|
||||
PARAMETER C_DDR2_ODT_SETTING = 1
|
||||
PARAMETER C_DQS_BITS = 3
|
||||
PARAMETER C_DDR_DQS_WIDTH = 8
|
||||
PARAMETER C_DDR_RAWIDTH = 13
|
||||
PARAMETER C_DDR_BURST_LENGTH = 4
|
||||
PARAMETER C_DDR_CAS_LAT = 4
|
||||
PARAMETER C_REG_DIMM = 0
|
||||
PARAMETER C_MIB_MC_CLOCK_RATIO = 1
|
||||
PARAMETER C_DDR_TREFI = 3900
|
||||
PARAMETER C_DDR_TRAS = 40000
|
||||
PARAMETER C_DDR_TRCD = 15000
|
||||
PARAMETER C_DDR_TRFC = 75000
|
||||
PARAMETER C_DDR_TRP = 15000
|
||||
PARAMETER C_DDR_TRTP = 7500
|
||||
PARAMETER C_DDR_TWR = 15000
|
||||
PARAMETER C_DDR_TWTR = 7500
|
||||
PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000
|
||||
PARAMETER C_IDEL_HIGH_PERF = TRUE
|
||||
PARAMETER C_NUM_IDELAYCTRL = 3
|
||||
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
|
||||
PARAMETER C_DQS_IO_COL = 0b000000000000000000
|
||||
PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_MEM_BASEADDR = 0x00000000
|
||||
PARAMETER C_MEM_HIGHADDR = 0x0fffffff
|
||||
BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
|
||||
PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST
|
||||
PORT mi_mcreset = sys_bus_reset
|
||||
PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST
|
||||
PORT mi_mcclk_200 = clk_200_0000MHz
|
||||
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
|
||||
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
|
||||
PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin
|
||||
PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin
|
||||
PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin
|
||||
PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin
|
||||
PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin
|
||||
PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin
|
||||
PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin
|
||||
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
|
||||
PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin
|
||||
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
|
||||
PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin
|
||||
PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin
|
||||
END
|
||||
|
||||
BEGIN xps_sysace
|
||||
PARAMETER INSTANCE = SysACE_CompactFlash
|
||||
PARAMETER C_MEM_WIDTH = 16
|
||||
PARAMETER C_FAMILY = virtex5
|
||||
PARAMETER HW_VER = 1.01.a
|
||||
PARAMETER C_BASEADDR = 0x83600000
|
||||
PARAMETER C_HIGHADDR = 0x8360ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
|
||||
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
|
||||
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
|
||||
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
|
||||
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
|
||||
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
|
||||
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
|
||||
END
|
||||
|
||||
BEGIN fcb_v20
|
||||
PARAMETER INSTANCE = ppc440_0_fcb_v20
|
||||
PARAMETER HW_VER = 1.00.a
|
||||
PORT FCB_CLK = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT SYS_RST = sys_bus_reset
|
||||
END
|
||||
|
||||
BEGIN apu_fpu_virtex5
|
||||
PARAMETER INSTANCE = ppc440_0_apu_fpu_virtex5
|
||||
PARAMETER C_DOUBLE_PRECISION = 0
|
||||
PARAMETER HW_VER = 1.01.a
|
||||
BUS_INTERFACE SFCB2 = ppc440_0_fcb_v20
|
||||
END
|
||||
|
||||
BEGIN clock_generator
|
||||
PARAMETER INSTANCE = clock_generator_0
|
||||
PARAMETER C_CLKIN_FREQ = 100000000
|
||||
PARAMETER C_CLKFBIN_FREQ = 125000000
|
||||
PARAMETER C_CLKOUT0_FREQ = 125000000
|
||||
PARAMETER C_CLKOUT0_PHASE = 90
|
||||
PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
|
||||
PARAMETER C_CLKOUT0_BUF = TRUE
|
||||
PARAMETER C_CLKOUT1_FREQ = 125000000
|
||||
PARAMETER C_CLKOUT1_PHASE = 0
|
||||
PARAMETER C_CLKOUT1_GROUP = PLL0
|
||||
PARAMETER C_CLKOUT1_BUF = TRUE
|
||||
PARAMETER C_CLKOUT2_FREQ = 125000000
|
||||
PARAMETER C_CLKOUT2_PHASE = 0
|
||||
PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
|
||||
PARAMETER C_CLKOUT2_BUF = TRUE
|
||||
PARAMETER C_CLKOUT3_FREQ = 200000000
|
||||
PARAMETER C_CLKOUT3_PHASE = 0
|
||||
PARAMETER C_CLKOUT3_GROUP = NONE
|
||||
PARAMETER C_CLKOUT3_BUF = TRUE
|
||||
PARAMETER C_CLKOUT4_FREQ = 62500000
|
||||
PARAMETER C_CLKOUT4_PHASE = 0
|
||||
PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
|
||||
PARAMETER C_CLKOUT4_BUF = TRUE
|
||||
PARAMETER C_CLKFBOUT_FREQ = 125000000
|
||||
PARAMETER C_CLKFBOUT_BUF = TRUE
|
||||
PARAMETER HW_VER = 3.00.a
|
||||
PORT CLKIN = dcm_clk_s
|
||||
PORT CLKFBIN = SRAM_CLK_FB_s
|
||||
PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
|
||||
PORT CLKOUT1 = clk_125_0000MHzPLL0
|
||||
PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT CLKOUT3 = clk_200_0000MHz
|
||||
PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST
|
||||
PORT CLKFBOUT = SRAM_CLK_OUT_s
|
||||
PORT RST = net_gnd
|
||||
PORT LOCKED = Dcm_all_locked
|
||||
END
|
||||
|
||||
BEGIN jtagppc_cntlr
|
||||
PARAMETER INSTANCE = jtagppc_cntlr_inst
|
||||
PARAMETER HW_VER = 2.01.c
|
||||
BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
|
||||
END
|
||||
|
||||
BEGIN proc_sys_reset
|
||||
PARAMETER INSTANCE = proc_sys_reset_0
|
||||
PARAMETER C_EXT_RESET_HIGH = 0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
BUS_INTERFACE RESETPPC0 = ppc_reset_bus
|
||||
PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
|
||||
PORT Ext_Reset_In = sys_rst_s
|
||||
PORT Dcm_locked = Dcm_all_locked
|
||||
PORT Bus_Struct_Reset = sys_bus_reset
|
||||
PORT Peripheral_Reset = sys_periph_reset
|
||||
END
|
||||
|
||||
BEGIN xps_intc
|
||||
PARAMETER INSTANCE = xps_intc_0
|
||||
PARAMETER HW_VER = 2.00.a
|
||||
PARAMETER C_BASEADDR = 0x81800000
|
||||
PARAMETER C_HIGHADDR = 0x8180ffff
|
||||
BUS_INTERFACE SPLB = plb_v46_0
|
||||
PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt
|
||||
PORT Irq = ppc440_0_EICC440EXTIRQ
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
|
||||
PARAMETER VERSION = 2.2.0
|
||||
|
||||
|
||||
BEGIN OS
|
||||
PARAMETER OS_NAME = standalone
|
||||
PARAMETER OS_VER = 2.00.a
|
||||
PARAMETER PROC_INSTANCE = ppc440_0
|
||||
PARAMETER STDIN = RS232_Uart_1
|
||||
PARAMETER STDOUT = RS232_Uart_1
|
||||
END
|
||||
|
||||
|
||||
BEGIN PROCESSOR
|
||||
PARAMETER DRIVER_NAME = cpu_ppc440
|
||||
PARAMETER DRIVER_VER = 1.00.b
|
||||
PARAMETER HW_INSTANCE = ppc440_0
|
||||
PARAMETER COMPILER = powerpc-eabi-gcc
|
||||
PARAMETER ARCHIVER = powerpc-eabi-ar
|
||||
END
|
||||
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = bram
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = uartlite
|
||||
PARAMETER DRIVER_VER = 1.14.a
|
||||
PARAMETER HW_INSTANCE = RS232_Uart_1
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = gpio
|
||||
PARAMETER DRIVER_VER = 2.13.a
|
||||
PARAMETER HW_INSTANCE = LEDs_8Bit
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = gpio
|
||||
PARAMETER DRIVER_VER = 2.13.a
|
||||
PARAMETER HW_INSTANCE = LEDs_Positions
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = gpio
|
||||
PARAMETER DRIVER_VER = 2.13.a
|
||||
PARAMETER HW_INSTANCE = Push_Buttons_5Bit
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = gpio
|
||||
PARAMETER DRIVER_VER = 2.13.a
|
||||
PARAMETER HW_INSTANCE = DIP_Switches_8Bit
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = iic
|
||||
PARAMETER DRIVER_VER = 1.14.a
|
||||
PARAMETER HW_INSTANCE = IIC_EEPROM
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = emc
|
||||
PARAMETER DRIVER_VER = 2.00.a
|
||||
PARAMETER HW_INSTANCE = SRAM
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = pcie
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = PCIe_Bridge
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = emaclite
|
||||
PARAMETER DRIVER_VER = 1.14.a
|
||||
PARAMETER HW_INSTANCE = Ethernet_MAC
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = memcon
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = DDR2_SDRAM
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = sysace
|
||||
PARAMETER DRIVER_VER = 1.12.a
|
||||
PARAMETER HW_INSTANCE = SysACE_CompactFlash
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = apu_fpu_virtex5
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = ppc440_0_apu_fpu_virtex5
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = clock_generator_0
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = jtagppc_cntlr_inst
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 1.00.a
|
||||
PARAMETER HW_INSTANCE = proc_sys_reset_0
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = intc
|
||||
PARAMETER DRIVER_VER = 1.11.a
|
||||
PARAMETER HW_INSTANCE = xps_intc_0
|
||||
END
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#Please do not modify this file by hand
|
||||
XmpVersion: 11.1
|
||||
VerMgmt: 11.1
|
||||
IntStyle: default
|
||||
MHS File: system.mhs
|
||||
MSS File: system.mss
|
||||
Architecture: virtex5
|
||||
Device: xc5vfx70t
|
||||
Package: ff1136
|
||||
SpeedGrade: -1
|
||||
UserCmd1:
|
||||
UserCmd1Type: 0
|
||||
UserCmd2:
|
||||
UserCmd2Type: 0
|
||||
GenSimTB: 0
|
||||
SdkExportBmmBit: 1
|
||||
SdkExportDir: SDK/SDK_Export
|
||||
InsertNoPads: 0
|
||||
WarnForEAArch: 1
|
||||
HdlLang: VHDL
|
||||
SimModel: BEHAVIORAL
|
||||
UcfFile: data/system.ucf
|
||||
EnableParTimingError: 1
|
||||
ShowLicenseDialog: 1
|
||||
Processor: ppc440_0
|
||||
BootLoop: 1
|
||||
XmdStub: 0
|
||||
SwProj: RTOSDemo
|
||||
Processor: ppc440_0
|
||||
Executable: RTOSDemo/executable.elf
|
||||
Source: RTOSDemo/../../Common/Minimal/BlockQ.c
|
||||
Source: RTOSDemo/../../Common/Minimal/blocktim.c
|
||||
Source: RTOSDemo/../../Common/Minimal/comtest.c
|
||||
Source: RTOSDemo/../../Common/Minimal/countsem.c
|
||||
Source: RTOSDemo/../../Common/Minimal/death.c
|
||||
Source: RTOSDemo/../../Common/Minimal/dynamic.c
|
||||
Source: RTOSDemo/../../Common/Minimal/flash.c
|
||||
Source: RTOSDemo/../../Common/Minimal/GenQTest.c
|
||||
Source: RTOSDemo/../../Common/Minimal/integer.c
|
||||
Source: RTOSDemo/../../Common/Minimal/QPeek.c
|
||||
Source: RTOSDemo/../../Common/Minimal/recmutex.c
|
||||
Source: RTOSDemo/../../Common/Minimal/semtest.c
|
||||
Source: RTOSDemo/../../../Source/tasks.c
|
||||
Source: RTOSDemo/../../../Source/list.c
|
||||
Source: RTOSDemo/../../../Source/queue.c
|
||||
Source: RTOSDemo/../../../Source/croutine.c
|
||||
Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S
|
||||
Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c
|
||||
Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c
|
||||
Source: RTOSDemo/flop/flop-reg-test.c
|
||||
Source: RTOSDemo/flop/flop.c
|
||||
Source: RTOSDemo/partest/partest.c
|
||||
Source: RTOSDemo/serial/serial.c
|
||||
Source: RTOSDemo/main.c
|
||||
DefaultInit: EXECUTABLE
|
||||
InitBram: 0
|
||||
Active: 1
|
||||
CompilerOptLevel: 0
|
||||
GlobPtrOpt: 0
|
||||
DebugSym: 1
|
||||
ProfileFlag: 0
|
||||
SearchIncl: ../../Source/include ../../Source/portable/GCC/PPC440_Xilinx ../Common/include ./RTOSDemo ./RTOSDemo/flop
|
||||
ProgStart:
|
||||
StackSize:
|
||||
HeapSize:
|
||||
LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld
|
||||
ProgCCFlags: -D GCC_PPC440 -mregnames
|
||||
CompileInXps: 1
|
||||
NonXpsApp: 0
|
||||
Loading…
Add table
Add a link
Reference in a new issue