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* Revert "Remove coroutines (#874)"
This reverts commit 569c78fd8c
.
* Update freertos Kernel submodule to latest head
* Remove temporary files
* Fix MingW demos and spell check
* Fix manifest version; fix headers
* Add ignore files and paths to core-checker.py
* Fix copyright in remaining files
* Fix PR check build failure
1. Remove defining `inline` in Makefile. This was causing build
warnings.
2. Ensure that the linker removed unused functions from various
compilation units.
3. Update the linker script so that all the functions are correctly
placed in FLASH section.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---------
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
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605 changed files with 11240 additions and 3628 deletions
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@ -47,26 +47,26 @@
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* signal which triggers a single interrupt with a fixed priority for all
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* interrupt levels. Alternatively the signals can be disaggregated into unique
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* interrupt events which can be vectored via a dispatch table to unique
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* handlers for each interrupt source. This mechanism allows, for instance, a
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* single interrupt handler for a large number of IO pins yet unique handlers
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* handlers for each interrupt source. This mechanism allows, for instance, a
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* single interrupt handler for a large number of IO pins yet unique handlers
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* for timers and other signals.
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*
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*
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* When operating in disaggregated mode certain restrictions apply. The
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* interrupt event and status registers are shared between timers due to their
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* proximity in the memory map. Similarly the software interrupt control
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* registers are shared with other interrupt sources. The JTVIC maps interrupt
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* levels into MIPs core interrupt levels consequently JTVIC priorities of 0, 1,
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* 3, and 4 map to the MIPs core values of 1, 3, 5, and 7. The parameter
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* configTIMERS_DISAGGREGATED_ISRS is used to control if the timers in register
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* GIRQ23 are operating in disaggregated mode. Similarly
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* levels into MIPs core interrupt levels consequently JTVIC priorities of 0, 1,
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* 3, and 4 map to the MIPs core values of 1, 3, 5, and 7. The parameter
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* configTIMERS_DISAGGREGATED_ISRS is used to control if the timers in register
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* GIRQ23 are operating in disaggregated mode. Similarly
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* configCPU_DISAGGREGATED_ISRS controls the mode for GIRQ24.
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*
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*
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* Note:
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* Disaggregated mode is the more natural manner in which to operate the ISRs
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* and currently only this mode has been tested with the demo application. If
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* you wish to use aggregated mode then an alternative interrupt handler scheme
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* will need to be used that marshals all interrupts from a single GIRQ through
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* a common handler function that tests which interrupt occurred and dispatches
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* will need to be used that marshals all interrupts from a single GIRQ through
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* a common handler function that tests which interrupt occurred and dispatches
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* to the relevant handlers.
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*/
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#define configTIMERS_DISAGGREGATED_ISRS 1
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@ -99,6 +99,9 @@
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configGENERATE_RUN_TIME_STATS 0
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Software timer definitions. */
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#define configUSE_TIMERS 1
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