Revert "Remove coroutines (#874)" (#1019)

* Revert "Remove coroutines (#874)"

This reverts commit 569c78fd8c.

* Update freertos Kernel submodule to latest head

* Remove temporary files

* Fix MingW demos and spell check

* Fix manifest version; fix headers

* Add ignore files and paths to core-checker.py

* Fix copyright in remaining files

* Fix PR check build failure

1. Remove defining `inline` in Makefile. This was causing build
   warnings.
2. Ensure that the linker removed unused functions from various
   compilation units.
3. Update the linker script so that all the functions are correctly
   placed in FLASH section.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Aniruddha Kanhere 2023-06-09 15:25:48 -07:00 committed by GitHub
parent 9ccae851e7
commit 1277ba1661
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
605 changed files with 11240 additions and 3628 deletions

View file

@ -112,6 +112,9 @@ readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1

View file

@ -32,8 +32,8 @@
* containing an unexpected value is indicative of an error in the context
* switching mechanism.
*/
__asm void vRegTest1Implementation( void )
{
PRESERVE8
@ -76,7 +76,7 @@ reg1_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
@ -157,10 +157,10 @@ reg1_loop
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
@ -197,7 +197,7 @@ reg1_loopf_pass
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, =ulRegTest1LoopCounter
@ -205,7 +205,7 @@ reg1_loopf_pass
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg1_loop
@ -256,11 +256,11 @@ __asm void vRegTest2Implementation( void )
vmov d15, r6, r7
reg2_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
@ -341,10 +341,10 @@ reg2_loop
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
@ -381,7 +381,7 @@ reg2_loopf_pass
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
/* Increment the loop counter to indicate this test is still functioning
correctly. */
push { r0-r1 }
@ -389,16 +389,16 @@ reg2_loopf_pass
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
lsl r0, r0, #28 /* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
/* Start again. */
b reg2_loop

View file

@ -74,7 +74,7 @@ timers must still be above the tick interrupt priority. */
#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )
#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
/* Hardware register locations and bit definitions to enable the btimer
/* Hardware register locations and bit definitions to enable the btimer
interrupts. */
#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )
#define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )