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synced 2025-10-26 23:36:32 -04:00
Fix formatting in kernel demo application files (#1148)
* Fix formatting in kernel demo application files * Fix header check fail in the demo files * Add ignored patterns in core header check file * Fix formatting * Update vApplicationStackOverflowHook for AVR_ATMega4809_MPLAB.X/main.c Co-authored-by: Soren Ptak <ptaksoren@gmail.com> * Update vApplicationStackOverflowHook for AVR_ATMega4809_MPLAB.X/main.c Co-authored-by: Soren Ptak <ptaksoren@gmail.com> * Update vApplicationStackOverflowHook for AVR_Dx_IAR/main.c Co-authored-by: Soren Ptak <ptaksoren@gmail.com> * Update vApplicationStackOverflowHook for AVR_Dx_IAR/main.c Co-authored-by: Soren Ptak <ptaksoren@gmail.com> * Update vApplicationStackOverflowHook for AVR_Dx_MPLAB.X/main.c Co-authored-by: Soren Ptak <ptaksoren@gmail.com> * Update vApplicationMallocFailedHook for AVR_Dx_MPLAB.X/main.c Co-authored-by: Soren Ptak <ptaksoren@gmail.com> * Fix formatting AVR32_UC3 --------- Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
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169 changed files with 22211 additions and 21557 deletions
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@ -1,4 +1,5 @@
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS and lwIP example for AVR32 UC3.
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@ -58,88 +59,88 @@
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#include "flash.h"
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/* Priority definitions for most of the tasks in the demo application. */
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#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
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#define mainETH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
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#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
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#define mainETH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
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/* Baud rate used by the serial port tasks. */
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#define mainCOM_BAUD_RATE ( ( unsigned long ) 57600 )
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#define mainCOM_BUFFER_LEN ( ( unsigned long ) 70 )
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#define mainCOM_BAUD_RATE ( ( unsigned long ) 57600 )
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#define mainCOM_BUFFER_LEN ( ( unsigned long ) 70 )
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/* An address in the internal Flash used to count resets. This is used to check that
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the demo application is not unexpectedly resetting. */
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#define mainRESET_COUNT_ADDRESS ( ( void * ) 0xC0000000 )
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* the demo application is not unexpectedly resetting. */
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#define mainRESET_COUNT_ADDRESS ( ( void * ) 0xC0000000 )
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//!
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//! \fn main
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//! \brief start the software here
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//! 1) Initialize the microcontroller and the shared hardware resources
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//! of the board.
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//! 2) Launch the IP modules.
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//! 3) Start FreeRTOS.
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//! \return 42, which should never occur.
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//! \note
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//!
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/*! */
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/*! \fn main */
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/*! \brief start the software here */
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/*! 1) Initialize the microcontroller and the shared hardware resources */
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/*! of the board. */
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/*! 2) Launch the IP modules. */
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/*! 3) Start FreeRTOS. */
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/*! \return 42, which should never occur. */
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/*! \note */
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/*! */
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int main( void )
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{
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volatile avr32_pm_t* pm = &AVR32_PM;
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volatile avr32_pm_t * pm = &AVR32_PM;
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/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
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/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
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/* Switch to external oscillator 0 */
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pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
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/* Switch to external oscillator 0 */
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pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
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/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
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Extra div by 2 => 96MHz */
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pm_pll_setup(pm, /* volatile avr32_pm_t* pm */
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0, /* unsigned int pll */
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15, /* unsigned int mul */
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1, /* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
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0, /* unsigned int osc */
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16); /* unsigned int lockcount */
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/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
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* Extra div by 2 => 96MHz */
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pm_pll_setup( pm, /* volatile avr32_pm_t* pm */
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0, /* unsigned int pll */
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15, /* unsigned int mul */
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1, /* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
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0, /* unsigned int osc */
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16 ); /* unsigned int lockcount */
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pm_pll_set_option( pm, 0, // pll0
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0, // Choose the range 160-240MHz.
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1, // div2
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0 ); // wbwdisable
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pm_pll_set_option( pm, 0, /* pll0 */
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0, /* Choose the range 160-240MHz. */
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1, /* div2 */
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0 ); /* wbwdisable */
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/* Enable PLL0 */
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pm_pll_enable(pm,0);
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/* Enable PLL0 */
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pm_pll_enable( pm, 0 );
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/* Wait for PLL0 locked */
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pm_wait_for_pll0_locked(pm) ;
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/* Wait for PLL0 locked */
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pm_wait_for_pll0_locked( pm );
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/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
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pm_gc_setup(pm,
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0,
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1, /* Use Osc (=0) or PLL (=1) */
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0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
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0,
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1);
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/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
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pm_gc_setup( pm,
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0,
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1, /* Use Osc (=0) or PLL (=1) */
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0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
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0,
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1 );
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/* Enable Generic clock 0*/
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pm_gc_enable(pm, 0);
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/* Enable Generic clock 0*/
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pm_gc_enable( pm, 0 );
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/* switch to clock */
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pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
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flashc_set_wait_state( 1 );
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pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
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/* switch to clock */
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pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
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flashc_set_wait_state( 1 );
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pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
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/* Setup the LED's for output. */
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vParTestInitialise();
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/* Setup the LED's for output. */
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vParTestInitialise();
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/* Start the flash tasks just to provide visual feedback that the demo is
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executing. */
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vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
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/* Start the flash tasks just to provide visual feedback that the demo is
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* executing. */
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vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
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/* 2) Start ethernet task. */
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vStartEthernetTask( mainETH_TASK_PRIORITY );
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/* 2) Start ethernet task. */
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vStartEthernetTask( mainETH_TASK_PRIORITY );
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/* 3) Start FreeRTOS. */
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vTaskStartScheduler();
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/* 3) Start FreeRTOS. */
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vTaskStartScheduler();
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/* Will only reach here if there was insufficient memory to create the idle task. */
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/* Will only reach here if there was insufficient memory to create the idle task. */
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return 0;
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return 0;
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}
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/*-----------------------------------------------------------*/
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