mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-12-06 13:15:19 -05:00
armv8.1-m: Add PACBTI support to kernel non-secure implementation
In this commit, Pointer Authentication, and Branch Target Identification Extension (PACBTI) support is added for Non-Secure and Non-TrustZone variants of Cortex-M85 FreeRTOS-Kernel Port. The PACBTI support is added for Arm Compiler For Embedded, and IAR toolchains only. The support in the kernel is not yet enabled for GNU toolchain due to known issues. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
This commit is contained in:
Ahmed Ismail
Ahmed Ismail
parent
4d0a28d269
commit
11fe156c08
58 changed files with 2212 additions and 42 deletions
5
.github/.cSpellWords.txt
vendored
5
.github/.cSpellWords.txt
vendored
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@ -448,6 +448,7 @@ MAINRDY
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MAIR
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Mang
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Mbits
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mbranch
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mcause
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MCFR
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MCKA
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@ -586,6 +587,8 @@ OWATCOM
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OWDR
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OWER
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OWSR
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pacbti
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PACBTI
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PAGEN
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PCDR
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PCER
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@ -900,6 +903,7 @@ TXTEN
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TXUBR
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TXVC
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TXVDIS
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UBTI
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UDCP
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UNACKED
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uncrustify
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@ -915,6 +919,7 @@ UNSUB
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UNSUBACK
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unsubscriptions
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unsuspended
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UPAC
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URAD
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URAT
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URSTEN
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@ -3032,6 +3032,18 @@
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#define configCONTROL_INFINITE_LOOP()
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#endif
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/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
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* support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
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#if ( portHAS_PACBTI_FEATURE == 1 )
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#ifndef configENABLE_PAC
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#define configENABLE_PAC 0
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#endif
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#ifndef configENABLE_BTI
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#define configENABLE_BTI 0
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#endif
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#endif
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/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
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* dynamically allocated RAM, in which case when any task is deleted it is known
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* that both the task's stack and TCB need to be freed. Sometimes the
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
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#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
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#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
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#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
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#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
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/*-----------------------------------------------------------*/
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/**
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@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
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* any secure calls.
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*/
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#define portNO_SECURE_CONTEXT 0
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/**
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* @brief Constants required to check and configure PACBTI security feature implementation.
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*/
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#if ( portHAS_PACBTI_FEATURE == 1 )
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#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
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#define portCONTROL_UPAC_EN ( 1UL << 7UL )
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#define portCONTROL_PAC_EN ( 1UL << 6UL )
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#define portCONTROL_UBTI_EN ( 1UL << 5UL )
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#define portCONTROL_BTI_EN ( 1UL << 4UL )
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#endif /* portHAS_PACBTI_FEATURE */
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/*-----------------------------------------------------------*/
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/**
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@ -410,6 +427,26 @@ static void prvTaskExitError( void );
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static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
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#endif /* configENABLE_FPU */
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#if ( portHAS_PACBTI_FEATURE == 1 )
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/**
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* @brief Configures PACBTI features.
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*
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* This function configures the Pointer Authentication, and Branch Target
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* Identification security features as per the user configuration. It returns
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* the value of the special purpose CONTROL register accordingly, and optionally
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* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
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* architecture based) target supports PACBTI security feature.
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*
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* @param xWriteControlRegister Used to control whether the special purpose
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* CONTROL register should be updated or not.
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*
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* @return CONTROL register value according to the configured PACBTI option.
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*/
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static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
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#endif /* portHAS_PACBTI_FEATURE */
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/**
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* @brief Setup the timer to generate the tick interrupts.
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*
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@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
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{
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uint32_t ulIndex = 0;
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uint32_t ulControl = 0x0;
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xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
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ulIndex++;
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@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
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ulIndex++;
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#if ( portHAS_PACBTI_FEATURE == 1 )
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{
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/* Check PACBTI security feature configuration before pushing the
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* CONTROL register's value on task's TCB. */
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ulControl = prvConfigurePACBTI( pdFALSE );
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}
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#endif /* portHAS_PACBTI_FEATURE */
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if( xRunPrivileged == pdTRUE )
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{
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xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
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xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
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ulIndex++;
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}
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else
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{
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xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
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xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
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ulIndex++;
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}
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@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
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portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
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portNVIC_SHPR2_REG = 0;
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#if ( portHAS_PACBTI_FEATURE == 1 )
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{
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/* Set the CONTROL register value based on PACBTI security feature
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* configuration before starting the first task. */
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( void) prvConfigurePACBTI( pdTRUE );
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}
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#endif /* portHAS_PACBTI_FEATURE */
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#if ( configENABLE_MPU == 1 )
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{
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/* Setup the Memory Protection Unit (MPU). */
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@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
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#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
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/*-----------------------------------------------------------*/
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#if ( portHAS_PACBTI_FEATURE == 1 )
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static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
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{
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uint32_t ulControl = 0x0;
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/* Ensure that PACBTI is implemented. */
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configASSERT( portID_ISAR5_REG != 0x0 );
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/* Enable UsageFault exception if PAC or BTI is enabled. */
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#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
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{
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portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
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}
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#endif
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#if( configENABLE_PAC == 1 )
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{
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ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
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}
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#endif
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#if( configENABLE_BTI == 1 )
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{
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ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
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}
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#endif
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if( xWriteControlRegister == pdTRUE )
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{
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__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
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}
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return ulControl;
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}
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#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -56,6 +58,7 @@
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#define portARCH_NAME "Cortex-M55"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 1
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -56,6 +58,7 @@
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#define portARCH_NAME "Cortex-M85"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 1
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#define portHAS_PACBTI_FEATURE 1
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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|
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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|
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
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*
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* SPDX-License-Identifier: MIT
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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|
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
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* SPDX-License-Identifier: MIT
|
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*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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|
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
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||||
* SPDX-License-Identifier: MIT
|
||||
*
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|
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -781,6 +781,104 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
|
|||
Common/mpu_wrappers_v2.c
|
||||
)
|
||||
endif()
|
||||
|
||||
if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
|
||||
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "GNU")
|
||||
message(FATAL_ERROR "ARMv8.1-M PACBTI support in the kernel is not yet enabled for GNU toolchain due to known issues.")
|
||||
endif()
|
||||
|
||||
if(FREERTOS_PORT MATCHES ".*ARM_CM85")
|
||||
if(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_STANDARD")
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=standard>)
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti+pac-ret>>)
|
||||
target_compile_definitions(freertos_config
|
||||
INTERFACE
|
||||
configENABLE_PAC=1
|
||||
configENABLE_BTI=1
|
||||
)
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI")
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
|
||||
target_compile_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
-mbranch-protection=bti+pac-ret+leaf
|
||||
)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=1
|
||||
configENABLE_BTI=1
|
||||
)
|
||||
elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
|
||||
message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI PACBTI option is not supported on IAR Compiler.")
|
||||
endif()
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET")
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=pac-ret>)
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=pac-ret>>)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=1
|
||||
)
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF")
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
|
||||
target_compile_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
-mbranch-protection=pac-ret+leaf
|
||||
)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=1
|
||||
)
|
||||
elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
|
||||
message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF PACBTI option is not supported on IAR Compiler.")
|
||||
endif()
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_BTI")
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=bti>)
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti>>)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_BTI=1
|
||||
)
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
|
||||
target_compile_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
-mbranch-protection=none
|
||||
)
|
||||
endif()
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=0
|
||||
configENABLE_BTI=0
|
||||
)
|
||||
else()
|
||||
message(FATAL_ERROR "Invalid FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG configuration, the supported configurations are
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_STANDARD,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_PACRET,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_BTI,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_NONE
|
||||
")
|
||||
endif()
|
||||
if(NOT FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
|
||||
# The reason why `--library_security=pacbti-m` link option is defined for both `freertos_kernel_port`, and
|
||||
# `freertos_kernel` targets even though `freertos_kernel_port` gets linked to `freertos_kernel` is that the
|
||||
# `freertos_kernel_port` is an object library where its linker options don't propagate to the targets that
|
||||
# link against it.
|
||||
target_link_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
--library_security=pacbti-m
|
||||
)
|
||||
target_link_options(freertos_kernel
|
||||
PUBLIC
|
||||
--library_security=pacbti-m
|
||||
)
|
||||
endif()
|
||||
else()
|
||||
message(FATAL_ERROR "FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option is currently only supported on ARM Cortex-M85 FreeRTOS port.")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
add_library(freertos_kernel_port_headers INTERFACE)
|
||||
|
||||
target_include_directories(freertos_kernel_port_headers INTERFACE
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue