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Rename directories with XMC4500 in their name that now contain XMC4200 and XMC4000 build configurations to instead say XMC4000.

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Richard Barry 2013-09-04 16:03:31 +00:00
parent d8963209c2
commit 117235c08a
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200
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Ensure stdint is only used by the compiler, and not the assembler. */
#ifdef __ICCARM__
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif /* __ICCARM__ */
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_QUEUE_SETS 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 6 /* 63 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
/* Demo application specific settings. */
#ifdef __ICCARM__
#if defined( PART_XMC4500 )
/* Hardware includes. */
#include "XMC4500.h"
#include "System_XMC4500.h"
/* Configure pin P3.9 for the LED. */
#define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
#elif defined( PART_XMC4400 )
/* Hardware includes. */
#include "XMC4400.h"
#include "System_XMC4200.h"
/* Configure pin P5.2 for the LED. */
#define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )
#elif defined( PART_XMC4200 )
/* Hardware includes. */
#include "XMC4200.h"
#include "System_XMC4200.h"
/* Configure pin P2.1 for the LED. */
#define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL
/* To toggle the single LED */
#define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )
#else
#error Part number not specified in project options
#endif
#endif
#endif /* FREERTOS_CONFIG_H */

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo.ewp</path>
</project>
<batchBuild/>
</workspace>

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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RegTest.s Normal file
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN ulRegTest1LoopCounter
EXTERN ulRegTest2LoopCounter
PUBLIC vRegTest1Task
PUBLIC vRegTest2Task
PUBLIC vRegTestClearFlopRegistersToParameterValue
PUBLIC ulRegTestCheckFlopRegistersContainParameterValue
/*-----------------------------------------------------------*/
vRegTest1Task
/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
/* Fill the VFP registers with known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg1_loop:
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
reg1_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg1_error_loopf
reg1_loopf_pass
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, =ulRegTest1LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg1_loop
reg1_error_loop:
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
/*-----------------------------------------------------------*/
vRegTest2Task
/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
/* Set all the VFP to known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg2_loop:
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
reg2_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
/* Increment the loop counter to indicate this test is still functioning
correctly. */
push { r0-r1 }
ldr r0, =ulRegTest2LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
lsl r0, r0, #28 /* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
/* Start again. */
b reg2_loop
reg2_error_loop:
/* If this line is hit then there was an error in a core register value.
This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
/*-----------------------------------------------------------*/
vRegTestClearFlopRegistersToParameterValue
/* Clobber the auto saved registers. */
vmov d0, r0, r0
vmov d1, r0, r0
vmov d2, r0, r0
vmov d3, r0, r0
vmov d4, r0, r0
vmov d5, r0, r0
vmov d6, r0, r0
vmov d7, r0, r0
bx lr
/*-----------------------------------------------------------*/
ulRegTestCheckFlopRegistersContainParameterValue
vmov r1, s0
cmp r0, r1
bne return_error
vmov r1, s1
cmp r0, r1
bne return_error
vmov r1, s2
cmp r0, r1
bne return_error
vmov r1, s3
cmp r0, r1
bne return_error
vmov r1, s4
cmp r0, r1
bne return_error
vmov r1, s5
cmp r0, r1
bne return_error
vmov r1, s6
cmp r0, r1
bne return_error
vmov r1, s7
cmp r0, r1
bne return_error
vmov r1, s8
cmp r0, r1
bne return_error
vmov r1, s9
cmp r0, r1
bne return_error
vmov r1, s10
cmp r0, r1
bne return_error
vmov r1, s11
cmp r0, r1
bne return_error
vmov r1, s12
cmp r0, r1
bne return_error
vmov r1, s13
cmp r0, r1
bne return_error
vmov r1, s14
cmp r0, r1
bne return_error
vmov r1, s15
cmp r0, r1
bne return_error
return_pass
mov r0, #1
bx lr
return_error
mov r0, #0
bx lr
END

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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/XMC4500_Flash.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define symbol __DRAM1_start__ = 0x20000000;
define symbol __DRAM1_end__ = 0x20007FFF;
define symbol __DRAM2_start__ = 0x30000000;
define symbol __DRAM2_end__ = 0x30007FFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region DRAM1_region = mem:[from __DRAM1_start__ to __DRAM1_end__];
define region DRAM2_region = mem:[from __DRAM2_start__ to __DRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region {readonly};
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in DRAM1_region{ section .dram1};
place in DRAM2_region{ section .dram2};

239
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c Normal file
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*
*
* Additional code:
*
* This demo does not contain a non-kernel interrupt service routine that
* can be used as an example for application writers to use as a reference.
* Therefore, the framework of a dummy (not installed) handler is provided
* in this file. The dummy function is called Dummy_IRQHandler(). Please
* ensure to read the comments in the function itself, but more importantly,
* the notes on the function contained on the documentation page for this demo
* that is found on the FreeRTOS.org web site.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Standard demo includes. */
#include "QueueSet.h"
#include "QueueOverwrite.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* Set up the hardware ready to run this demo.
*/
static void prvSetupHardware( void );
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
extern void main_blinky( void );
extern void main_full( void );
/*-----------------------------------------------------------*/
int main( void )
{
/* Prepare the hardware to run this demo. */
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
of this file. */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
{
main_blinky();
}
#else
{
main_full();
}
#endif
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
configCONFIGURE_LED();
/* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
{
/* Write to a queue that is in use as part of the queue set demo to
demonstrate using queue sets from an ISR. */
vQueueSetAccessQueueSetFromISR();
/* Test the ISR safe queue overwrite functions. */
vQueueOverwritePeriodicISRDemo();
}
#endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */
}
/*-----------------------------------------------------------*/
#ifdef JUST_AN_EXAMPLE_ISR
void Dummy_IRQHandler(void)
{
long lHigherPriorityTaskWoken = pdFALSE;
/* Clear the interrupt if necessary. */
Dummy_ClearITPendingBit();
/* This interrupt does nothing more than demonstrate how to synchronise a
task with an interrupt. A semaphore is used for this purpose. Note
lHigherPriorityTaskWoken is initialised to zero. */
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
/* If there was a task that was blocked on the semaphore, and giving the
semaphore caused the task to unblock, and the unblocked task has a priority
higher than the current Running state task (the task that this interrupt
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the
portEND_SWITCHING_ISR() macro will result in a context switch being pended to
ensure this interrupt returns directly to the unblocked, higher priority,
task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
}
#endif /* JUST_AN_EXAMPLE_ISR */

232
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@ -0,0 +1,232 @@
/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles the LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* Values passed to the two tasks just to check the task parameter
functionality. */
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* Called by main() to create the simply blinky style application if
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
*/
void main_blinky( void );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static xQueueHandle xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
configTOGGLE_LED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

297
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c Normal file
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@ -0,0 +1,297 @@
/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the comprehensive test and demo version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_full() creates all the demo application tasks and a software timer, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" timer - The check software timer period is initially set to three
* seconds. The callback function associated with the check software timer
* checks that all the standard demo tasks, and the register check tasks, are
* not only still executing, but are executing without reporting any errors. If
* the check software timer discovers that a task has either stalled, or
* reported an error, then it changes its own execution period from the initial
* three seconds, to just 200ms. The check software timer callback function
* also toggles the single LED each time it is called. This provides a visual
* indication of the system status: If the LED toggles every three seconds,
* then no issues have been discovered. If the LED toggles every 200ms, then
* an issue has been discovered with at least one task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "semtest.h"
#include "dynamic.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "QueueSet.h"
#include "QueueOverwrite.h"
/* Priorities for the demo application tasks. */
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_RATE_MS constant. */
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_RATE_MS constant. */
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* The check timer callback function, as described at the top of this file.
*/
static void prvCheckTimerCallback( xTimerHandle xTimer );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file.
*/
extern void vRegTest1Task( void *pvParameters );
extern void vRegTest2Task( void *pvParameters );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check software timer. If the variables keep
incrementing, then the register check tasks has not discovered any errors. If
a variable stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
void main_full( void )
{
xTimerHandle xCheckTimer = NULL;
/* Start all the other standard demo/test tasks. The have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartQueueSetTasks();
vStartQueueOverwriteTask( tskIDLE_PRIORITY );
vStartDynamicPriorityTasks();
vCreateBlockTimeTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartMathTasks( mainFLOP_TASK_PRIORITY );
/* Create the register check tasks, as described at the top of this
file */
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
/* Create the software timer that performs the 'check' functionality,
as described at the top of this file. */
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
);
if( xCheckTimer != NULL )
{
xTimerStart( xCheckTimer, mainDONT_BLOCK );
}
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTimerCallback( xTimerHandle xTimer )
{
static long lChangedTimerPeriodAlready = pdFALSE;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xAreQueueSetTasksStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
if( xIsQueueOverwriteTaskStillRunning() != pdTRUE )
{
ulErrorFound = pdTRUE;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound = pdTRUE;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
everything is ok. A faster toggle indicates an error. */
configTOGGLE_LED();
/* Have any errors been latch in ulErrorFound? If so, shorten the
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
This will result in an increase in the rate at which mainCHECK_LED
toggles. */
if( ulErrorFound != pdFALSE )
{
if( lChangedTimerPeriodAlready == pdFALSE )
{
lChangedTimerPeriodAlready = pdTRUE;
/* This call to xTimerChangePeriod() uses a zero block time.
Functions called from inside of a timer callback function must
*never* attempt to block. */
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
}
}
}
/*-----------------------------------------------------------*/

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/**************************************************************************//**
* @file system_XMC4200.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4000 Device Series
* @version V3.0.1 Alpha
* @date 26. September 2012
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <system_XMC4200.h>
#include <XMC4200.h>
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock;
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
#define SCU_CLOCK_BACK_UP_FACTORY 2
#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
#define HIB_CLOCK_FOSI 1
#define HIB_CLOCK_OSCULP 2
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/* not avalible in config wizzard*/
/*
* mandatory clock parameters **************************************************
*
* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
// Selection of imput lock for PLL
/*************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
/*************************************************************************************/
// Standby clock selection for Backup clock source trimming
/*************************************************************************************/
#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
/*************************************************************************************/
// Global clock parameters
/*************************************************************************************/
#define CLOCK_FSYS 80000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define CLOCK_BACK_UP 24000000
/*************************************************************************************/
/* OSC_HP setup parameters */
/*************************************************************************************/
#define SCU_OSC_HP_MODE 0xF0
#define SCU_OSCHPWDGDIV 2
/*************************************************************************************/
/* MAIN PLL setup parameters */
/*************************************************************************************/
//Divider settings for external crystal @ 12 MHz
/*************************************************************************************/
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 5
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
/*************************************************************************************/
//Divider settings for use of backup clock source trimmed
/*************************************************************************************/
//#define SCU_PLL_K1DIV 1
//#define SCU_PLL_K2DIV 5
//#define SCU_PLL_PDIV 3
//#define SCU_PLL_NDIV 79
/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/* not avalible in config wizzard*/
#define SCU_USBPLL_PDIV 0
#define SCU_USBPLL_NDIV 31
#define SCU_USBDIV 3
/*--------------------- Flash Wait State Configuration -------------------------------
//
// <e> Flash Wait State Configuration
// <o1.0..3> Flash Wait State
// <0=> 3 WS
// <1=> 4 WS
// <2=> 5 WS
// <3=> 6 WS
// </e>
//
*/
#define PMU_FLASH 1
#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
// <o2.0..4> Clockout divider <1-10><#-1>
// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0
#define SCU_CLOCKOUT_SOURCE 0x00000000
#define SCU_CLOCKOUT_DIV 0x00000009
#define SCU_CLOCKOUT_PIN 0x00000001
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
#if SCU_CLOCK_SETUP
uint32_t SystemCoreClock = CLOCK_FSYS;
#else
uint32_t SystemCoreClock = CLOCK_BACK_UP;
#endif
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the WDT */
#if WDT_SETUP
WDT->CTR &= ~WDTENB_nVal;
#endif
/* Setup the Flash Wait State */
#if PMU_FLASH
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS+3;
FLASH0->FCON = temp;
#endif
/* Setup the clockout */
#if SCU_CLOCKOUT_SETUP
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
/*set PLL div for clkout */
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
}
else {
PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
}
#endif
/* Setup the System clock */
#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
/* Setup the USB PL */
#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
unsigned int PDIV;
unsigned int NDIV;
unsigned int K2DIV;
unsigned int long VCO;
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
if (SCU_CLK->SYSCLKCR == 0x00010000)
{
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
/* check if PLL is locked */
/* read back divider settings */
PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
/* the selected clock is the Backup clock fofi */
VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
else
{
/* the selected clock is the PLL external oscillator */
VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
}
}
else
{
SystemCoreClock = CLOCK_BACK_UP;
}
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
int temp;
unsigned int long VCO;
int stepping_K2DIV;
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
/* Enable OSC_HP if not already on*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/********************************************************************************************************************/
/* Use external crystal for PLL clock input */
/********************************************************************************************************************/
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
{
/********************************************************************************************************************/
/* Use factory trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
{
/********************************************************************************************************************/
/* Use automatic trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* check for HIB Domain enabled */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
/* check for HIB Domain is not in reset state */
if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
{
/****************************************************************************************************************/
/* Use fOSI as source of the standby clock */
/****************************************************************************************************************/
SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
}
else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
{
/****************************************************************************************************************/
/* Use fULP as source of the standby clock */
/****************************************************************************************************************/
/*check OSCUL if running correct*/
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
/* select OSCUL clock for RTC*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*enable OSCULP WDG Alarm Enable*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*wait now for clock is stable */
do
{
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
for(temp=0;temp<=0xFFFF;temp++);
}
while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
}
// now OSCULP is running and can be used
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
}
}
/********************************************************************************************************************/
/* Setup and look the main PLL */
/********************************************************************************************************************/
if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
/* Systen is still running from internal clock */
/* select FOFI as system clock */
if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/24000000)-1;
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
/* setup time out loop */
/* Timeout for wait loo ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
}
else return(0);
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/* we may have to reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/*********************************************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 60MHz
*********************************************************/
if (CLOCK_FSYS > 60000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/60000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 90MHz
*********************************************************/
if (CLOCK_FSYS > 90000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/90000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
}
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void)
{
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
}
/* check and if not already running enable OSC_HP */
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
/* check if Main PLL is switched on for OSC WD*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
/* Setup USBDIV settings USB clock */
SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif

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FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4400.c Normal file
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/**************************************************************************//**
* @file system_XMC4400.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4500 Device Series
* @version V3.0.1 Alpha
* @date 17. September 2012
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <system_XMC4400.h>
#include <XMC4400.h>
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock;
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
#define SCU_CLOCK_BACK_UP_FACTORY 2
#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
#define HIB_CLOCK_FOSI 1
#define HIB_CLOCK_OSCULP 2
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/* not avalible in config wizzard*/
/*
* mandatory clock parameters **************************************************
*
* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
// Selection of imput lock for PLL
/*************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
/*************************************************************************************/
// Standby clock selection for Backup clock source trimming
/*************************************************************************************/
#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
/*************************************************************************************/
// Global clock parameters
/*************************************************************************************/
#define CLOCK_FSYS 120000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define CLOCK_BACK_UP 24000000
/*************************************************************************************/
/* OSC_HP setup parameters */
/*************************************************************************************/
#define SCU_OSC_HP_MODE 0xF0
#define SCU_OSCHPWDGDIV 2
/*************************************************************************************/
/* MAIN PLL setup parameters */
/*************************************************************************************/
//Divider settings for external crystal @ 12 MHz
/*************************************************************************************/
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 3
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
/*************************************************************************************/
//Divider settings for use of backup clock source trimmed
/*************************************************************************************/
//#define SCU_PLL_K1DIV 1
//#define SCU_PLL_K2DIV 3
//#define SCU_PLL_PDIV 3
//#define SCU_PLL_NDIV 79
/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/* not avalible in config wizzard*/
#define SCU_USBPLL_PDIV 0
#define SCU_USBPLL_NDIV 31
#define SCU_USBDIV 3
/*--------------------- Flash Wait State Configuration -------------------------------
//
// <e> Flash Wait State Configuration
// <o1.0..3> Flash Wait State
// <0=> 3 WS
// <1=> 4 WS
// <2=> 5 WS
// <3=> 6 WS
// </e>
//
*/
#define PMU_FLASH 1
#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
// <o2.0..4> Clockout divider <1-10><#-1>
// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0
#define SCU_CLOCKOUT_SOURCE 0x00000000
#define SCU_CLOCKOUT_DIV 0x00000009
#define SCU_CLOCKOUT_PIN 0x00000001
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
#if SCU_CLOCK_SETUP
uint32_t SystemCoreClock = CLOCK_FSYS;
#else
uint32_t SystemCoreClock = CLOCK_BACK_UP;
#endif
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the WDT */
#if WDT_SETUP
WDT->CTR &= ~WDTENB_nVal;
#endif
/* Setup the Flash Wait State */
#if PMU_FLASH
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS+3;
FLASH0->FCON = temp;
#endif
/* Setup the clockout */
#if SCU_CLOCKOUT_SETUP
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
/*set PLL div for clkout */
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
}
else {
PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
}
#endif
/* Setup the System clock */
#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
/* Setup the USB PL */
#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
unsigned int PDIV;
unsigned int NDIV;
unsigned int K2DIV;
unsigned int long VCO;
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
if (SCU_CLK->SYSCLKCR == 0x00010000)
{
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
/* check if PLL is locked */
/* read back divider settings */
PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
/* the selected clock is the Backup clock fofi */
VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
else
{
/* the selected clock is the PLL external oscillator */
VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
}
}
else
{
SystemCoreClock = CLOCK_BACK_UP;
}
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
int temp;
unsigned int long VCO;
int stepping_K2DIV;
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
/* Enable OSC_HP if not already on*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/********************************************************************************************************************/
/* Use external crystal for PLL clock input */
/********************************************************************************************************************/
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
{
/********************************************************************************************************************/
/* Use factory trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
{
/********************************************************************************************************************/
/* Use automatic trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* check for HIB Domain enabled */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
/* check for HIB Domain is not in reset state */
if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
{
/****************************************************************************************************************/
/* Use fOSI as source of the standby clock */
/****************************************************************************************************************/
SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
}
else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
{
/****************************************************************************************************************/
/* Use fULP as source of the standby clock */
/****************************************************************************************************************/
/*check OSCUL if running correct*/
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
/* select OSCUL clock for RTC*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*enable OSCULP WDG Alarm Enable*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*wait now for clock is stable */
do
{
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
for(temp=0;temp<=0xFFFF;temp++);
}
while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
}
// now OSCULP is running and can be used
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
}
}
/********************************************************************************************************************/
/* Setup and look the main PLL */
/********************************************************************************************************************/
if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
/* Systen is still running from internal clock */
/* select FOFI as system clock */
if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/24000000)-1;
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
/* setup time out loop */
/* Timeout for wait loo ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
}
else return(0);
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/* we may have to reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/*********************************************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 60MHz
*********************************************************/
if (CLOCK_FSYS > 60000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/60000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 90MHz
*********************************************************/
if (CLOCK_FSYS > 90000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/90000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
}
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void)
{
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
}
/* check and if not already running enable OSC_HP */
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
/* check if Main PLL is switched on for OSC WD*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
/* Setup USBDIV settings USB clock */
SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif

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/*****************************************************************************/
/* Startup_XMC4200.s: Startup file for XMC4200 device series for EWARM */
/*****************************************************************************/
/*
* @file Startup_XMC4200.s
* XMC4000 Device Series
* @version V1.0
* @date Jan 2013
*
* Copyright (C) 2012 IAR Systems. All rights reserved.
* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* ********************* Version History *********************************** */
/* ***************************************************************************
V1.0 January, 30 2013: In ths version a workoraound for the erratum PMU_CM.001
is implmented (patch for the Exception and interrupt handlers)
**************************************************************************** */
MODULE ?vector_table
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
;/*
; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
; * A veneer defined below will first be executed which in turn branches to the final
; * exception handler.
; *
; * In addition to defining the veneers, the vector table must for these buggy
; * devices contain the veneers.
; */
;set WORKAROUND_PMU_CM001 under Options for target
;Initialize varaible WORKAROUND_PMU_CM001 as FALSE
WORKAROUND_PMU_CM001 SET 1
;/* A macro to setup a vector table entry based on STEP ID */
#ifdef WORKAROUND_PMU_CM001
ExcpVector macro
DCD \1_Veneer
endm
#else
ExcpVector macro
DCD \1
endm
#endif
;/* A macro to ease definition of the various handlers based on STEP ID */
#ifdef WORKAROUND_PMU_CM001
;/* First define the final exception handler */
ProxyHandler macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(1)
\1
B \1
endm
;/* And then define a veneer that will branch to the final excp handler */
ProxyHandler_Veneer macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(2)
\1
LDR R0, =ProxyHandler
PUSH {LR}
BLX R0
POP {PC}
endm
;/* No prefetch bug, hence define only the final exception handler */
#else
ProxyHandler macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(1)
\1
B \1
endm
#endif
;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
ExcpVector NMI_Handler ; NMI Handler
ExcpVector HardFault_Handler ; Hard Fault Handler
ExcpVector MemManage_Handler ; MPU Fault Handler
ExcpVector BusFault_Handler ; Bus Fault Handler
ExcpVector UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
ExcpVector PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals
ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
DCD 0 ; Not Available
ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
DCD 0 ; Not Available
ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
DCD 0 ; Not Available
ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =SystemInit_DAVE3
BLX R0
LDR R0, =__iar_program_start
BX R0
ProxyHandler NMI_Handler
ProxyHandler HardFault_Handler
ProxyHandler MemManage_Handler
ProxyHandler BusFault_Handler
ProxyHandler UsageFault_Handler
ProxyHandler SVC_Handler
ProxyHandler DebugMon_Handler
ProxyHandler PendSV_Handler
ProxyHandler SysTick_Handler
ProxyHandler SCU_0_IRQHandler
ProxyHandler ERU0_0_IRQHandler
ProxyHandler ERU0_1_IRQHandler
ProxyHandler ERU0_2_IRQHandler
ProxyHandler ERU0_3_IRQHandler
ProxyHandler ERU1_0_IRQHandler
ProxyHandler ERU1_1_IRQHandler
ProxyHandler ERU1_2_IRQHandler
ProxyHandler ERU1_3_IRQHandler
ProxyHandler PMU0_0_IRQHandler
ProxyHandler VADC0_C0_0_IRQHandler
ProxyHandler VADC0_C0_1_IRQHandler
ProxyHandler VADC0_C0_2_IRQHandler
ProxyHandler VADC0_C0_3_IRQHandler
ProxyHandler VADC0_G0_0_IRQHandler
ProxyHandler VADC0_G0_1_IRQHandler
ProxyHandler VADC0_G0_2_IRQHandler
ProxyHandler VADC0_G0_3_IRQHandler
ProxyHandler VADC0_G1_0_IRQHandler
ProxyHandler VADC0_G1_1_IRQHandler
ProxyHandler VADC0_G1_2_IRQHandler
ProxyHandler VADC0_G1_3_IRQHandler
ProxyHandler DAC0_0_IRQHandler
ProxyHandler DAC0_1_IRQHandler
ProxyHandler CCU40_0_IRQHandler
ProxyHandler CCU40_1_IRQHandler
ProxyHandler CCU40_2_IRQHandler
ProxyHandler CCU40_3_IRQHandler
ProxyHandler CCU41_0_IRQHandler
ProxyHandler CCU41_1_IRQHandler
ProxyHandler CCU41_2_IRQHandler
ProxyHandler CCU41_3_IRQHandler
ProxyHandler CCU80_0_IRQHandler
ProxyHandler CCU80_1_IRQHandler
ProxyHandler CCU80_2_IRQHandler
ProxyHandler CCU80_3_IRQHandler
ProxyHandler POSIF0_0_IRQHandler
ProxyHandler POSIF0_1_IRQHandler
ProxyHandler HRPWM_0_IRQHandler
ProxyHandler HRPWM_1_IRQHandler
ProxyHandler HRPWM_2_IRQHandler
ProxyHandler HRPWM_3_IRQHandler
ProxyHandler CAN0_0_IRQHandler
ProxyHandler CAN0_1_IRQHandler
ProxyHandler CAN0_2_IRQHandler
ProxyHandler CAN0_3_IRQHandler
ProxyHandler CAN0_4_IRQHandler
ProxyHandler CAN0_5_IRQHandler
ProxyHandler CAN0_6_IRQHandler
ProxyHandler CAN0_7_IRQHandler
ProxyHandler USIC0_0_IRQHandler
ProxyHandler USIC0_1_IRQHandler
ProxyHandler USIC0_2_IRQHandler
ProxyHandler USIC0_3_IRQHandler
ProxyHandler USIC0_4_IRQHandler
ProxyHandler USIC0_5_IRQHandler
ProxyHandler USIC1_0_IRQHandler
ProxyHandler USIC1_1_IRQHandler
ProxyHandler USIC1_2_IRQHandler
ProxyHandler USIC1_3_IRQHandler
ProxyHandler USIC1_4_IRQHandler
ProxyHandler USIC1_5_IRQHandler
ProxyHandler LEDTS0_0_IRQHandler
ProxyHandler FCE0_0_IRQHandler
ProxyHandler GPDMA0_0_IRQHandler
ProxyHandler USB0_0_IRQHandler
; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.
PUBWEAK SystemInit_DAVE3
SECTION .text:CODE:REORDER:NOROOT(2)
SystemInit_DAVE3
NOP
BX LR
; Definition of the default weak DAVE3 function for clock App usage.
; AllowPLLInitByStartup Handler
PUBWEAK AllowPLLInitByStartup
SECTION .text:CODE:REORDER:NOROOT(2)
AllowPLLInitByStartup
MOV R0,#1
BX LR
PREF_PCON EQU 0x58004000
SCU_GCU_PEEN EQU 0x5000413C
SCU_GCU_PEFLAG EQU 0x50004150
END

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/*****************************************************************************/
/* Startup_XMC4400.s: Startup file for XMC4400 device series for EWARM */
/*****************************************************************************/
/**
* @file Startup_XMC4400.s
* XMC4000 Device Series
* @version V1.0
* @date Jan 2013
*
* Copyright (C) 2012 IAR Systems. All rights reserved.
* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* ********************* Version History *********************************** */
/* ***************************************************************************
V1.0 January, 30 2013: In ths version a workoraound for the erratum PMU_CM.001
is implmented (patch for the Exception and interrupt handlers)
**************************************************************************** */
MODULE ?vector_table
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
;/*
; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
; * A veneer defined below will first be executed which in turn branches to the final
; * exception handler.
; *
; * In addition to defining the veneers, the vector table must for these buggy
; * devices contain the veneers.
; */
;set WORKAROUND_PMU_CM001 under Options for target
;Initialize varaible WORKAROUND_PMU_CM001 as FALSE
WORKAROUND_PMU_CM001 SET 1
;/* A macro to setup a vector table entry based on STEP ID */
#ifdef WORKAROUND_PMU_CM001
ExcpVector macro
DCD \1_Veneer
endm
#else
ExcpVector macro
DCD \1
endm
#endif
;/* A macro to ease definition of the various handlers based on STEP ID */
#ifdef WORKAROUND_PMU_CM001
;/* First define the final exception handler */
ProxyHandler macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(1)
\1
B \1
endm
;/* And then define a veneer that will branch to the final excp handler */
ProxyHandler_Veneer macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(2)
\1
LDR R0, =ProxyHandler
PUSH {LR}
BLX R0
POP {PC}
endm
;/* No prefetch bug, hence define only the final exception handler */
#else
ProxyHandler macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(1)
\1
B \1
endm
#endif
;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
ExcpVector NMI_Handler ; NMI Handler
ExcpVector HardFault_Handler ; Hard Fault Handler
ExcpVector MemManage_Handler ; MPU Fault Handler
ExcpVector BusFault_Handler ; Bus Fault Handler
ExcpVector UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
ExcpVector DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
DCD 0 ; Not Available
ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD_SRM_0
ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD_SRM_1
ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD_SRM_2
ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD_SRM_3
ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD_SRA_0
ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD_SRA_1
ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD_SRA_2
ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD_SRA_3
ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
DCD 0 ; Not Available
ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
DCD 0 ; Not Available
ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =SystemInit_DAVE3
BLX R0
LDR R0, =__iar_program_start
BX R0
ProxyHandler NMI_Handler
ProxyHandler HardFault_Handler
ProxyHandler MemManage_Handler
ProxyHandler BusFault_Handler
ProxyHandler UsageFault_Handler
ProxyHandler SVC_Handler
ProxyHandler DebugMon_Handler
ProxyHandler PendSV_Handler
ProxyHandler SysTick_Handler
ProxyHandler SCU_0_IRQHandler
ProxyHandler ERU0_0_IRQHandler
ProxyHandler ERU0_1_IRQHandler
ProxyHandler ERU0_2_IRQHandler
ProxyHandler ERU0_3_IRQHandler
ProxyHandler ERU1_0_IRQHandler
ProxyHandler ERU1_1_IRQHandler
ProxyHandler ERU1_2_IRQHandler
ProxyHandler ERU1_3_IRQHandler
ProxyHandler PMU0_0_IRQHandler
ProxyHandler VADC0_C0_0_IRQHandler
ProxyHandler VADC0_C0_1_IRQHandler
ProxyHandler VADC0_C0_2_IRQHandler
ProxyHandler VADC0_C0_3_IRQHandler
ProxyHandler VADC0_G0_0_IRQHandler
ProxyHandler VADC0_G0_1_IRQHandler
ProxyHandler VADC0_G0_2_IRQHandler
ProxyHandler VADC0_G0_3_IRQHandler
ProxyHandler VADC0_G1_0_IRQHandler
ProxyHandler VADC0_G1_1_IRQHandler
ProxyHandler VADC0_G1_2_IRQHandler
ProxyHandler VADC0_G1_3_IRQHandler
ProxyHandler VADC0_G2_0_IRQHandler
ProxyHandler VADC0_G2_1_IRQHandler
ProxyHandler VADC0_G2_2_IRQHandler
ProxyHandler VADC0_G2_3_IRQHandler
ProxyHandler VADC0_G3_0_IRQHandler
ProxyHandler VADC0_G3_1_IRQHandler
ProxyHandler VADC0_G3_2_IRQHandler
ProxyHandler VADC0_G3_3_IRQHandler
ProxyHandler DSD0_0_IRQHandler
ProxyHandler DSD0_1_IRQHandler
ProxyHandler DSD0_2_IRQHandler
ProxyHandler DSD0_3_IRQHandler
ProxyHandler DSD0_4_IRQHandler
ProxyHandler DSD0_5_IRQHandler
ProxyHandler DSD0_6_IRQHandler
ProxyHandler DSD0_7_IRQHandler
ProxyHandler DAC0_0_IRQHandler
ProxyHandler DAC0_1_IRQHandler
ProxyHandler CCU40_0_IRQHandler
ProxyHandler CCU40_1_IRQHandler
ProxyHandler CCU40_2_IRQHandler
ProxyHandler CCU40_3_IRQHandler
ProxyHandler CCU41_0_IRQHandler
ProxyHandler CCU41_1_IRQHandler
ProxyHandler CCU41_2_IRQHandler
ProxyHandler CCU41_3_IRQHandler
ProxyHandler CCU42_0_IRQHandler
ProxyHandler CCU42_1_IRQHandler
ProxyHandler CCU42_2_IRQHandler
ProxyHandler CCU42_3_IRQHandler
ProxyHandler CCU43_0_IRQHandler
ProxyHandler CCU43_1_IRQHandler
ProxyHandler CCU43_2_IRQHandler
ProxyHandler CCU43_3_IRQHandler
ProxyHandler CCU80_0_IRQHandler
ProxyHandler CCU80_1_IRQHandler
ProxyHandler CCU80_2_IRQHandler
ProxyHandler CCU80_3_IRQHandler
ProxyHandler CCU81_0_IRQHandler
ProxyHandler CCU81_1_IRQHandler
ProxyHandler CCU81_2_IRQHandler
ProxyHandler CCU81_3_IRQHandler
ProxyHandler POSIF0_0_IRQHandler
ProxyHandler POSIF0_1_IRQHandler
ProxyHandler POSIF1_0_IRQHandler
ProxyHandler POSIF1_1_IRQHandler
ProxyHandler HRPWM_0_IRQHandler
ProxyHandler HRPWM_1_IRQHandler
ProxyHandler HRPWM_2_IRQHandler
ProxyHandler HRPWM_3_IRQHandler
ProxyHandler CAN0_0_IRQHandler
ProxyHandler CAN0_1_IRQHandler
ProxyHandler CAN0_2_IRQHandler
ProxyHandler CAN0_3_IRQHandler
ProxyHandler CAN0_4_IRQHandler
ProxyHandler CAN0_5_IRQHandler
ProxyHandler CAN0_6_IRQHandler
ProxyHandler CAN0_7_IRQHandler
ProxyHandler USIC0_0_IRQHandler
ProxyHandler USIC0_1_IRQHandler
ProxyHandler USIC0_2_IRQHandler
ProxyHandler USIC0_3_IRQHandler
ProxyHandler USIC0_4_IRQHandler
ProxyHandler USIC0_5_IRQHandler
ProxyHandler USIC1_0_IRQHandler
ProxyHandler USIC1_1_IRQHandler
ProxyHandler USIC1_2_IRQHandler
ProxyHandler USIC1_3_IRQHandler
ProxyHandler USIC1_4_IRQHandler
ProxyHandler USIC1_5_IRQHandler
ProxyHandler LEDTS0_0_IRQHandler
ProxyHandler FCE0_0_IRQHandler
ProxyHandler GPDMA0_0_IRQHandler
ProxyHandler USB0_0_IRQHandler
ProxyHandler ETH0_0_IRQHandler
; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.
PUBWEAK SystemInit_DAVE3
SECTION .text:CODE:REORDER:NOROOT(2)
SystemInit_DAVE3
NOP
BX LR
; Definition of the default weak DAVE3 function for clock App usage.
; AllowPLLInitByStartup Handler
PUBWEAK AllowPLLInitByStartup
SECTION .text:CODE:REORDER:NOROOT(2)
AllowPLLInitByStartup
MOV R0,#1
BX LR
PREF_PCON EQU 0x58004000
SCU_GCU_PEEN EQU 0x5000413C
SCU_GCU_PEFLAG EQU 0x50004150
END

397
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/startup_XMC4500.s Normal file
View file

@ -0,0 +1,397 @@
/*****************************************************************************/
/* Startup_XMC4500.s: Startup file for XMC4500 device series for EWARM */
/*****************************************************************************/
/**
* @file Startup_XMC4500.s
* XMC4000 Device Series
* @version V1.0
* @date Jan 2013
*
* Copyright (C) 2012 IAR Systems. All rights reserved.
* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* ********************* Version History *********************************** */
/* ***************************************************************************
V1.0 January, 30 2013: In ths version a workoraound for the erratum PMU_CM.001
is implmented (patch for the Exception and interrupt handlers)
**************************************************************************** */
MODULE ?vector_table
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
;/*
; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
; * A veneer defined below will first be executed which in turn branches to the final
; * exception handler.
; *
; * In addition to defining the veneers, the vector table must for these buggy
; * devices contain the veneers.
; */
;set WORKAROUND_PMU_CM001 under Options for target
;Initialize varaible WORKAROUND_PMU_CM001 as TRUE
WORKAROUND_PMU_CM001 SET 1
;/* A macro to setup a vector table entry based on STEP ID */
#ifdef WORKAROUND_PMU_CM001
ExcpVector macro
DCD \1_Veneer
endm
#else
ExcpVector macro
DCD \1
endm
#endif
;/* A macro to ease definition of the various handlers based on STEP ID */
#ifdef WORKAROUND_PMU_CM001
;/* First define the final exception handler */
ProxyHandler macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(1)
\1
B \1
endm
;/* And then define a veneer that will branch to the final excp handler */
ProxyHandler_Veneer macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(2)
\1
LDR R0, =ProxyHandler
PUSH {LR}
BLX R0
POP {PC}
endm
;/* No prefetch bug, hence define only the final exception handler */
#else
ProxyHandler macro
PUBWEAK \1
SECTION .text:CODE:REORDER:NOROOT(1)
\1
B \1
endm
#endif
;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
ExcpVector NMI_Handler
ExcpVector HardFault_Handler
ExcpVector MemManage_Handler
ExcpVector BusFault_Handler
ExcpVector UsageFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
ExcpVector DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
DCD 0 ; Handler name for SR PMU0_1
ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0
ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1
ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2
ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3
ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4
ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5
ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6
ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7
ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_0
ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
ExcpVector USIC2_0_IRQHandler ; Handler name for SR USIC2_0
ExcpVector USIC2_1_IRQHandler ; Handler name for SR USIC2_1
ExcpVector USIC2_2_IRQHandler ; Handler name for SR USIC2_2
ExcpVector USIC2_3_IRQHandler ; Handler name for SR USIC2_3
ExcpVector USIC2_4_IRQHandler ; Handler name for SR USIC2_4
ExcpVector USIC2_5_IRQHandler ; Handler name for SR USIC2_5
ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
DCD 0 ; Not Available
ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
ExcpVector SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
DCD 0 ; Not Available
ExcpVector GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0
DCD 0 ; Not Available
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =SystemInit_DAVE3
BLX R0
LDR R0, =__iar_program_start
BX R0
ProxyHandler NMI_Handler
ProxyHandler HardFault_Handler
ProxyHandler MemManage_Handler
ProxyHandler BusFault_Handler
ProxyHandler UsageFault_Handler
ProxyHandler SVC_Handler
ProxyHandler DebugMon_Handler
ProxyHandler PendSV_Handler
ProxyHandler SysTick_Handler
ProxyHandler SCU_0_IRQHandler
ProxyHandler ERU0_0_IRQHandler
ProxyHandler ERU0_1_IRQHandler
ProxyHandler ERU0_2_IRQHandler
ProxyHandler ERU0_3_IRQHandler
ProxyHandler ERU1_0_IRQHandler
ProxyHandler ERU1_1_IRQHandler
ProxyHandler ERU1_2_IRQHandler
ProxyHandler ERU1_3_IRQHandler
ProxyHandler PMU0_0_IRQHandler
ProxyHandler PMU0_1_IRQHandler
ProxyHandler VADC0_C0_0_IRQHandler
ProxyHandler VADC0_C0_1_IRQHandler
ProxyHandler VADC0_C0_2_IRQHandler
ProxyHandler VADC0_C0_3_IRQHandler
ProxyHandler VADC0_G0_0_IRQHandler
ProxyHandler VADC0_G0_1_IRQHandler
ProxyHandler VADC0_G0_2_IRQHandler
ProxyHandler VADC0_G0_3_IRQHandler
ProxyHandler VADC0_G1_0_IRQHandler
ProxyHandler VADC0_G1_1_IRQHandler
ProxyHandler VADC0_G1_2_IRQHandler
ProxyHandler VADC0_G1_3_IRQHandler
ProxyHandler VADC0_G2_0_IRQHandler
ProxyHandler VADC0_G2_1_IRQHandler
ProxyHandler VADC0_G2_2_IRQHandler
ProxyHandler VADC0_G2_3_IRQHandler
ProxyHandler VADC0_G3_0_IRQHandler
ProxyHandler VADC0_G3_1_IRQHandler
ProxyHandler VADC0_G3_2_IRQHandler
ProxyHandler VADC0_G3_3_IRQHandler
ProxyHandler DSD0_0_IRQHandler
ProxyHandler DSD0_1_IRQHandler
ProxyHandler DSD0_2_IRQHandler
ProxyHandler DSD0_3_IRQHandler
ProxyHandler DSD0_4_IRQHandler
ProxyHandler DSD0_5_IRQHandler
ProxyHandler DSD0_6_IRQHandler
ProxyHandler DSD0_7_IRQHandler
ProxyHandler DAC0_0_IRQHandler
ProxyHandler DAC0_1_IRQHandler
ProxyHandler CCU40_0_IRQHandler
ProxyHandler CCU40_1_IRQHandler
ProxyHandler CCU40_2_IRQHandler
ProxyHandler CCU40_3_IRQHandler
ProxyHandler CCU41_0_IRQHandler
ProxyHandler CCU41_1_IRQHandler
ProxyHandler CCU41_2_IRQHandler
ProxyHandler CCU41_3_IRQHandler
ProxyHandler CCU42_0_IRQHandler
ProxyHandler CCU42_1_IRQHandler
ProxyHandler CCU42_2_IRQHandler
ProxyHandler CCU42_3_IRQHandler
ProxyHandler CCU43_0_IRQHandler
ProxyHandler CCU43_1_IRQHandler
ProxyHandler CCU43_2_IRQHandler
ProxyHandler CCU43_3_IRQHandler
ProxyHandler CCU80_0_IRQHandler
ProxyHandler CCU80_1_IRQHandler
ProxyHandler CCU80_2_IRQHandler
ProxyHandler CCU80_3_IRQHandler
ProxyHandler CCU81_0_IRQHandler
ProxyHandler CCU81_1_IRQHandler
ProxyHandler CCU81_2_IRQHandler
ProxyHandler CCU81_3_IRQHandler
ProxyHandler POSIF0_0_IRQHandler
ProxyHandler POSIF0_1_IRQHandler
ProxyHandler POSIF1_0_IRQHandler
ProxyHandler POSIF1_1_IRQHandler
ProxyHandler CAN0_0_IRQHandler
ProxyHandler CAN0_1_IRQHandler
ProxyHandler CAN0_2_IRQHandler
ProxyHandler CAN0_3_IRQHandler
ProxyHandler CAN0_4_IRQHandler
ProxyHandler CAN0_5_IRQHandler
ProxyHandler CAN0_6_IRQHandler
ProxyHandler CAN0_7_IRQHandler
ProxyHandler USIC0_0_IRQHandler
ProxyHandler USIC0_1_IRQHandler
ProxyHandler USIC0_2_IRQHandler
ProxyHandler USIC0_3_IRQHandler
ProxyHandler USIC0_4_IRQHandler
ProxyHandler USIC0_5_IRQHandler
ProxyHandler USIC1_0_IRQHandler
ProxyHandler USIC1_1_IRQHandler
ProxyHandler USIC1_2_IRQHandler
ProxyHandler USIC1_3_IRQHandler
ProxyHandler USIC1_4_IRQHandler
ProxyHandler USIC1_5_IRQHandler
ProxyHandler USIC2_0_IRQHandler
ProxyHandler USIC2_1_IRQHandler
ProxyHandler USIC2_2_IRQHandler
ProxyHandler USIC2_3_IRQHandler
ProxyHandler USIC2_4_IRQHandler
ProxyHandler USIC2_5_IRQHandler
ProxyHandler LEDTS0_0_IRQHandler
ProxyHandler FCE0_0_IRQHandler
ProxyHandler GPDMA0_0_IRQHandler
ProxyHandler SDMMC0_0_IRQHandler
ProxyHandler USB0_0_IRQHandler
ProxyHandler ETH0_0_IRQHandler
ProxyHandler GPDMA1_0_IRQHandler
; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.
PUBWEAK SystemInit_DAVE3
SECTION .text:CODE:REORDER:NOROOT(2)
SystemInit_DAVE3
NOP
BX LR
; Definition of the default weak DAVE3 function for clock App usage.
; AllowPLLInitByStartup Handler
PUBWEAK AllowPLLInitByStartup
SECTION .text:CODE:REORDER:NOROOT(2)
AllowPLLInitByStartup
MOV R0,#1
BX LR
PREF_PCON EQU 0x58004000
SCU_GCU_PEEN EQU 0x5000413C
SCU_GCU_PEFLAG EQU 0x50004150
END

72
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/**************************************************************************//**
* @file system_XMC4200.h
* @brief Header file for the XMC4400-Series systeminit
*
* @version V1.0
* @date 17. September 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4200_H
#define __SYSTEM_XMC4200_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* this weak function enables DAVE3 clock App usage */
extern uint32_t AllowPLLInitByStartup(void);
#ifdef __cplusplus
}
#endif
#endif

72
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/**************************************************************************//**
* @file system_XMC4400.h
* @brief Header file for the XMC4400-Series systeminit
*
* @version V1.0
* @date 17. August 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4400_H
#define __SYSTEM_XMC4400_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* this weak function enables DAVE3 clock App usage */
extern uint32_t AllowPLLInitByStartup(void);
#ifdef __cplusplus
}
#endif
#endif

705
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/**************************************************************************//**
* @file system_XMC4500.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4500 Device Series
* @version V3.0.1 Alpha
* @date 17. September 2012
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include "system_XMC4500.h"
#include <XMC4500.h>
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock;
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
#define SCU_CLOCK_BACK_UP_FACTORY 2
#define SCU_CLOCK_BACK_UP_AUTOMATIC 3
#define HIB_CLOCK_FOSI 1
#define HIB_CLOCK_OSCULP 2
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/* not avalible in config wizzard*/
/*
* mandatory clock parameters **************************************************
*
* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
// Selection of imput lock for PLL
/*************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
/*************************************************************************************/
// Standby clock selection for Backup clock source trimming
/*************************************************************************************/
#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
/*************************************************************************************/
// Global clock parameters
/*************************************************************************************/
#define CLOCK_FSYS 120000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define CLOCK_BACK_UP 24000000
/*************************************************************************************/
/* OSC_HP setup parameters */
/*************************************************************************************/
#define SCU_OSC_HP_MODE 0xF0
#define SCU_OSCHPWDGDIV 2
/*************************************************************************************/
/* MAIN PLL setup parameters */
/*************************************************************************************/
//Divider settings for external crystal @ 12 MHz
/*************************************************************************************/
#define SCU_PLL_K1DIV 1
#define SCU_PLL_K2DIV 3
#define SCU_PLL_PDIV 1
#define SCU_PLL_NDIV 79
/*************************************************************************************/
//Divider settings for use of backup clock source trimmed
/*************************************************************************************/
//#define SCU_PLL_K1DIV 1
//#define SCU_PLL_K2DIV 3
//#define SCU_PLL_PDIV 3
//#define SCU_PLL_NDIV 79
/*************************************************************************************/
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/* not avalible in config wizzard*/
#define SCU_USBPLL_PDIV 0
#define SCU_USBPLL_NDIV 31
#define SCU_USBDIV 3
/*--------------------- Flash Wait State Configuration -------------------------------
//
// <e> Flash Wait State Configuration
// <o1.0..3> Flash Wait State
// <0=> 3 WS
// <1=> 4 WS
// <2=> 5 WS
// <3=> 6 WS
// </e>
//
*/
#define PMU_FLASH 1
#define PMU_FLASH_WS 0x00000000
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> Divided value of USB PLL output
// <3=> Divided value of PLL Clock
// <o2.0..4> Clockout divider <1-10><#-1>
// <o3.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0
#define SCU_CLOCKOUT_SOURCE 0x00000003
#define SCU_CLOCKOUT_DIV 0x00000009
#define SCU_CLOCKOUT_PIN 0x00000001
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
#if SCU_CLOCK_SETUP
uint32_t SystemCoreClock = CLOCK_FSYS;
#else
uint32_t SystemCoreClock = CLOCK_BACK_UP;
#endif
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
int temp;
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the WDT */
#if WDT_SETUP
WDT->CTR &= ~WDTENB_nVal;
#endif
/* Setup the Flash Wait State */
#if PMU_FLASH
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS+3;
FLASH0->FCON = temp;
#endif
/* Setup the clockout */
#if SCU_CLOCKOUT_SETUP
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
/*set PLL div for clkout */
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
//PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
}
else {
PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
//PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
}
#endif
/* Setup the System clock */
#if SCU_CLOCK_SETUP
SystemClockSetup();
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
/* Setup the USB PL */
#if SCU_USB_CLOCK_SETUP
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
unsigned int PDIV;
unsigned int NDIV;
unsigned int K2DIV;
unsigned int long VCO;
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
if (SCU_CLK->SYSCLKCR == 0x00010000)
{
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
/* check if PLL is locked */
/* read back divider settings */
PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
/* the selected clock is the Backup clock fofi */
VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
else
{
/* the selected clock is the PLL external oscillator */
VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
SystemCoreClock = VCO/K2DIV;
/* in case the sysclock div is used */
SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
}
}
}
else
{
SystemCoreClock = CLOCK_BACK_UP;
}
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
int temp;
unsigned int long VCO;
int stepping_K2DIV;
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
/* Enable OSC_HP if not already on*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/********************************************************************************************************************/
/* Use external crystal for PLL clock input */
/********************************************************************************************************************/
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
{
/********************************************************************************************************************/
/* Use factory trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
}
else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
{
/********************************************************************************************************************/
/* Use automatic trimming Back-up clock for PLL clock input */
/********************************************************************************************************************/
/* check for HIB Domain enabled */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
/* check for HIB Domain is not in reset state */
if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
/* PLL Back up clock selected */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
{
/****************************************************************************************************************/
/* Use fOSI as source of the standby clock */
/****************************************************************************************************************/
SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
}
else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
{
/****************************************************************************************************************/
/* Use fULP as source of the standby clock */
/****************************************************************************************************************/
/*check OSCUL if running correct*/
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
/*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
/* select OSCUL clock for RTC*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*enable OSCULP WDG Alarm Enable*/
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
/*wait now for clock is stable */
do
{
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
for(temp=0;temp<=0xFFFF;temp++);
}
while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
}
// now OSCULP is running and can be used
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
/*TRIAL for delay loop*/
for(temp=0;temp<=0xFFFF;temp++);
}
}
/********************************************************************************************************************/
/* Setup and look the main PLL */
/********************************************************************************************************************/
if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
/* Systen is still running from internal clock */
/* select FOFI as system clock */
if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/24000000)-1;
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
/* setup time out loop */
/* Timeout for wait loo ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
}
else return(0);
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/* we may have to reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/*********************************************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 60MHz
*********************************************************/
if (CLOCK_FSYS > 60000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/60000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/*********************************************************
here the ramp up of the system clock starts FSys < 90MHz
*********************************************************/
if (CLOCK_FSYS > 90000000){
/*calulation for stepping*/
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
stepping_K2DIV = (VCO/90000000)-1;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
}
else
{
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
return(1);
}
/*********************************************************/
/* Delay for next K2 step ~50µs */
/*********************************************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
while (SysTick->VAL >= 100); /* wait for ~50µs */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
}
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_USB_CLOCK_SETUP == 1)
static int USBClockSetup(void)
{
/* this weak function enables DAVE3 clock App usage */
if(AllowPLLInitByStartup()){
/* check if PLL is switched on */
if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
}
/* check and if not already running enable OSC_HP */
if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
/* check if Main PLL is switched on for OSC WD*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
/* Timeout for wait loop ~150ms */
/********************************/
SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
do
{
;/* wait for ~150ms */
}while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
return(0);/* Return Error */
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
/* Setup USBDIV settings USB clock */
SCU_CLK->USBCLKCR = SCU_USBDIV;
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}/* end this weak function enables DAVE3 clock App usage */
return(1);
}
#endif

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/**************************************************************************//**
* @file system_XMC4500.h
* @brief Header file for the XMC4500-Series systeminit
*
* @version V1.6
* @date 23. October 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4500_H
#define __SYSTEM_XMC4500_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* this weak function enables DAVE3 clock App usage */
extern uint32_t AllowPLLInitByStartup(void);
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
/*
* mandatory clock parameters **************************************************
*/
/* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
* mandatory for old system_xmc4500.c files - please do not remove!!!
**************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
#define CLOCK_OSC_HP 24000000
#define CLOCK_BACK_UP 24000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define SYSTEM_FREQUENCY 120000000
/* OSC_HP setup parameters */
#define OSC_HP_MODE 0
#define OSCHPWDGDIV 2
/* MAIN PLL setup parameters */
#define PLL_K1DIV 1
#define PLL_K2DIV 3
#define PLL_PDIV 1
#define PLL_NDIV 79
#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
#define USBPLL_PDIV 1
#define USBPLL_NDIV 15
#ifdef __cplusplus
}
#endif
#endif