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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Support FPU - RISC-V architecture (GCC)
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
This commit is contained in:
Emmanuel Puerto
parent
2167df2446
commit
102df3fa08
1 changed files with 187 additions and 2 deletions
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@ -82,8 +82,29 @@
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#define portWORD_SIZE (__riscv_xlen / 8)
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/* Number of FPU register */
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/* FPU is not yet supported so PORT_FPU_REGISTER = 0 */
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#define portasmFPU_CONTEXT_SIZE 0
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#ifdef __riscv_fdiv
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#define MSTATUS_FS 0x00006000 /* Floating-point Status */
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#define MSTATUS_FS_OFF 0x00000000
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#define MSTATUS_FS_INITIAL 0x00002000
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#define MSTATUS_FS_CLEAN 0x00004000
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#define MSTATUS_FS_DIRTY 0x00006000
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#if __riscv_flen == 32
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#define store_fpu fsw
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#define load_fpu flw
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#endif /* __riscv_flen == 32 */
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#if __riscv_flen == 64
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#define store_fpu fsd
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#define load_fpu fld
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#endif /* __riscv_flen == 64 */
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#define portasmFPU_CONTEXT_SIZE (32)
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#define portFPUWORD_SIZE (__riscv_flen / 8)
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#else
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#define portasmFPU_CONTEXT_SIZE (0)
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#define portFPUWORD_SIZE (0)
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#endif /* __riscv_fdiv */
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#include "freertos_risc_v_chip_specific_extensions.h"
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@ -138,10 +159,12 @@ definitions. */
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#define PORT_CONTEXT_mepcOFFSET (PORT_CONTEXT_mepcIDX * portWORD_SIZE)
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#define PORT_CONTEXT_mstatusOFFSET (PORT_CONTEXT_mstatusIDX * portWORD_SIZE)
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#define PORT_CONTEXT_rufOFFSET (PORT_CONTEXT_rufIDX * portWORD_SIZE)
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#define PORT_CONTEXT_fpuOFFSET(X) ((X) * portFPUWORD_SIZE)
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/* total size of the structure usable in ASM. */
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#define portasmREGISTER_CONTEXT_WORDSIZE ((portasmLAST_BASE_REGS) * (portWORD_SIZE))
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#define portasmADDITIONAL_CONTEXT_WORDSIZE ((portasmADDITIONAL_CONTEXT_SIZE) * (portWORD_SIZE))
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#define portasmFPU_CONTEXT_WORDSIZE ((portasmFPU_CONTEXT_SIZE) * (portFPUWORD_SIZE))
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.global xPortStartFirstTask
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.global freertos_risc_v_trap_handler
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@ -158,6 +181,131 @@ definitions. */
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.extern portHANDLE_INTERRUPT
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.extern portHANDLE_EXCEPTION
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/*-----------------------------------------------------------*/
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#ifdef __riscv_fdiv
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.macro portSAVE_FpuReg
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/* get FS field from mstatus */
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li t0, MSTATUS_FS
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csrr t1, mstatus
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and t0, t1, t0
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li t2, MSTATUS_FS_DIRTY
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bne t2, t0, 1f
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/* FS == dirty */
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/* Make room for the additional FPU registers. */
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addi sp, sp, -portasmFPU_CONTEXT_WORDSIZE
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store_fpu f0, PORT_CONTEXT_fpuOFFSET(0)(sp) /* f0(ft0) FP temporary register */
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store_fpu f1, PORT_CONTEXT_fpuOFFSET(1)(sp) /* f1(ft1) FP temporary register */
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store_fpu f2, PORT_CONTEXT_fpuOFFSET(2)(sp) /* f2(ft2) FP temporary register */
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store_fpu f3, PORT_CONTEXT_fpuOFFSET(3)(sp) /* f3(ft3) FP temporary register */
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store_fpu f4, PORT_CONTEXT_fpuOFFSET(4)(sp) /* f4(ft4) FP temporary register */
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store_fpu f5, PORT_CONTEXT_fpuOFFSET(5)(sp) /* f5(ft5) FP temporary register */
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store_fpu f6, PORT_CONTEXT_fpuOFFSET(6)(sp) /* f6(ft6) FP temporary register */
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store_fpu f7, PORT_CONTEXT_fpuOFFSET(7)(sp) /* f7(ft7) FP temporary register */
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store_fpu f8, PORT_CONTEXT_fpuOFFSET(8)(sp) /* f8(fs0) FP Saved register */
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store_fpu f9, PORT_CONTEXT_fpuOFFSET(9)(sp) /* f9(fs0) FP Saved register */
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store_fpu f10, PORT_CONTEXT_fpuOFFSET(10)(sp) /* f10(fa0) FP arguments/return values register */
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store_fpu f11, PORT_CONTEXT_fpuOFFSET(11)(sp) /* f11(fa1) FP arguments/return values register */
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store_fpu f12, PORT_CONTEXT_fpuOFFSET(12)(sp) /* f12(fa2) FP arguments register */
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store_fpu f13, PORT_CONTEXT_fpuOFFSET(13)(sp) /* f13(fa3) FP arguments register */
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store_fpu f14, PORT_CONTEXT_fpuOFFSET(14)(sp) /* f14(fa4) FP arguments register */
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store_fpu f15, PORT_CONTEXT_fpuOFFSET(15)(sp) /* f15(fa5) FP arguments register */
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store_fpu f16, PORT_CONTEXT_fpuOFFSET(16)(sp) /* f16(fa6) FP arguments register */
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store_fpu f17, PORT_CONTEXT_fpuOFFSET(17)(sp) /* f17(fa7) FP arguments register */
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store_fpu f18, PORT_CONTEXT_fpuOFFSET(18)(sp) /* f18(fs2) FP Saved register */
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store_fpu f19, PORT_CONTEXT_fpuOFFSET(19)(sp) /* f19(fs3) FP Saved register */
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store_fpu f20, PORT_CONTEXT_fpuOFFSET(20)(sp) /* f20(fs4) FP Saved register */
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store_fpu f21, PORT_CONTEXT_fpuOFFSET(21)(sp) /* f21(fs5) FP Saved register */
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store_fpu f22, PORT_CONTEXT_fpuOFFSET(22)(sp) /* f22(fs6) FP Saved register */
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store_fpu f23, PORT_CONTEXT_fpuOFFSET(23)(sp) /* f23(fs7) FP Saved register */
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store_fpu f24, PORT_CONTEXT_fpuOFFSET(24)(sp) /* f24(fs8) FP Saved register */
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store_fpu f25, PORT_CONTEXT_fpuOFFSET(25)(sp) /* f25(fs9) FP Saved register */
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store_fpu f26, PORT_CONTEXT_fpuOFFSET(26)(sp) /* f26(fs10) FP Saved register */
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store_fpu f27, PORT_CONTEXT_fpuOFFSET(27)(sp) /* f27(fs11) FP Saved register */
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store_fpu f28, PORT_CONTEXT_fpuOFFSET(28)(sp) /* f28(ft8) FP temporary register */
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store_fpu f29, PORT_CONTEXT_fpuOFFSET(29)(sp) /* f29(ft9) FP temporary register */
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store_fpu f30, PORT_CONTEXT_fpuOFFSET(30)(sp) /* f30(ft10) FP temporary register */
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store_fpu f31, PORT_CONTEXT_fpuOFFSET(31)(sp) /* f31(ft11) FP temporary register */
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/* must set FS to clean */
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csrc mstatus, t0
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li t1, MSTATUS_FS_CLEAN
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csrs mstatus, t1
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1:
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.endm
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#else
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.macro portSAVE_FpuReg
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/* No fpu registers to save, so this macro does nothing. */
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.endm
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#endif /* __riscv_fdiv */
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/*-----------------------------------------------------------*/
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#ifdef __riscv_fdiv
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.macro portRESTORE_FpuReg
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/* get FS field from mstatus */
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li t0, MSTATUS_FS
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csrr t1, mstatus
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and t0, t1, t0
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li t2, MSTATUS_FS_OFF
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beq t2, t0, 1f
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/* FS != off */
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csrs mstatus, t0
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/* Remove space added for additional fpu registers. */
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addi sp, sp, portasmFPU_CONTEXT_WORDSIZE
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load_fpu f0, PORT_CONTEXT_fpuOFFSET(0)(sp) /* f0(ft0) FP temporary register */
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load_fpu f1, PORT_CONTEXT_fpuOFFSET(1)(sp) /* f1(ft1) FP temporary register */
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load_fpu f2, PORT_CONTEXT_fpuOFFSET(2)(sp) /* f2(ft2) FP temporary register */
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load_fpu f3, PORT_CONTEXT_fpuOFFSET(3)(sp) /* f3(ft3) FP temporary register */
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load_fpu f4, PORT_CONTEXT_fpuOFFSET(4)(sp) /* f4(ft4) FP temporary register */
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load_fpu f5, PORT_CONTEXT_fpuOFFSET(5)(sp) /* f5(ft5) FP temporary register */
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load_fpu f6, PORT_CONTEXT_fpuOFFSET(6)(sp) /* f6(ft6) FP temporary register */
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load_fpu f7, PORT_CONTEXT_fpuOFFSET(7)(sp) /* f7(ft7) FP temporary register */
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load_fpu f8, PORT_CONTEXT_fpuOFFSET(8)(sp) /* f8(fs0) FP Saved register */
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load_fpu f9, PORT_CONTEXT_fpuOFFSET(9)(sp) /* f9(fs0) FP Saved register */
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load_fpu f10, PORT_CONTEXT_fpuOFFSET(10)(sp) /* f10(fa0) FP arguments/return values register */
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load_fpu f11, PORT_CONTEXT_fpuOFFSET(11)(sp) /* f11(fa1) FP arguments/return values register */
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load_fpu f12, PORT_CONTEXT_fpuOFFSET(12)(sp) /* f12(fa2) FP arguments register */
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load_fpu f13, PORT_CONTEXT_fpuOFFSET(13)(sp) /* f13(fa3) FP arguments register */
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load_fpu f14, PORT_CONTEXT_fpuOFFSET(14)(sp) /* f14(fa4) FP arguments register */
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load_fpu f15, PORT_CONTEXT_fpuOFFSET(15)(sp) /* f15(fa5) FP arguments register */
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load_fpu f16, PORT_CONTEXT_fpuOFFSET(16)(sp) /* f16(fa6) FP arguments register */
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load_fpu f17, PORT_CONTEXT_fpuOFFSET(17)(sp) /* f17(fa7) FP arguments register */
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load_fpu f18, PORT_CONTEXT_fpuOFFSET(18)(sp) /* f18(fs2) FP Saved register */
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load_fpu f19, PORT_CONTEXT_fpuOFFSET(19)(sp) /* f19(fs3) FP Saved register */
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load_fpu f20, PORT_CONTEXT_fpuOFFSET(20)(sp) /* f20(fs4) FP Saved register */
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load_fpu f21, PORT_CONTEXT_fpuOFFSET(21)(sp) /* f21(fs5) FP Saved register */
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load_fpu f22, PORT_CONTEXT_fpuOFFSET(22)(sp) /* f22(fs6) FP Saved register */
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load_fpu f23, PORT_CONTEXT_fpuOFFSET(23)(sp) /* f23(fs7) FP Saved register */
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load_fpu f24, PORT_CONTEXT_fpuOFFSET(24)(sp) /* f24(fs8) FP Saved register */
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load_fpu f25, PORT_CONTEXT_fpuOFFSET(25)(sp) /* f25(fs9) FP Saved register */
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load_fpu f26, PORT_CONTEXT_fpuOFFSET(26)(sp) /* f26(fs10) FP Saved register */
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load_fpu f27, PORT_CONTEXT_fpuOFFSET(27)(sp) /* f27(fs11) FP Saved register */
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load_fpu f28, PORT_CONTEXT_fpuOFFSET(28)(sp) /* f28(ft8) FP temporary register */
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load_fpu f29, PORT_CONTEXT_fpuOFFSET(29)(sp) /* f29(ft9) FP temporary register */
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load_fpu f30, PORT_CONTEXT_fpuOFFSET(30)(sp) /* f30(ft10) FP temporary register */
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load_fpu f31, PORT_CONTEXT_fpuOFFSET(31)(sp) /* f31(ft11) FP temporary register */
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/* must set FS to clean */
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csrc mstatus, t0
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li t1, MSTATUS_FS_CLEAN
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csrs mstatus, t1
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1:
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.endm
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#else
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.macro portRESTORE_FpuReg
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/* No fpu registers to restore, so this macro does nothing. */
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.endm
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#endif /* __riscv_fdiv */
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/*-----------------------------------------------------------*/
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.macro portSAVE_BaseReg
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/* Make room for the registers. */
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@ -302,9 +450,12 @@ is_exception:
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store_x t0, PORT_CONTEXT_xOFFSET(2)(sp)
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/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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portasmSAVE_ADDITIONAL_REGISTERS
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/* Save any fpu registers */
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portSAVE_FpuReg
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/* Execption is treated by external function */
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jal portHANDLE_EXCEPTION
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/* in case that the go back from exception, restore registers */
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portRESTORE_FpuReg
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portasmRESTORE_ADDITIONAL_REGISTERS
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portRESTORE_BaseReg
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load_x x2, PORT_CONTEXT_xOFFSET(2)(sp)
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@ -326,6 +477,8 @@ ecall_yield:
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/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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portasmSAVE_ADDITIONAL_REGISTERS
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/* Save any fpu registers */
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portSAVE_FpuReg
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/* Load pxCurrentTCB and update first TCB member(pxTopOfStack) with sp. */
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load_x s0, pxCurrentTCB
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@ -351,6 +504,8 @@ handle_interrupt:
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/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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portasmSAVE_ADDITIONAL_REGISTERS
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/* Save any fpu registers */
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portSAVE_FpuReg
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/* Load pxCurrentTCB and update first TCB member(pxTopOfStack) with sp. */
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load_x s0, pxCurrentTCB
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@ -435,6 +590,7 @@ end_trap_handler:
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store_x t1, 0( s0 ) /* Write sp saved value to first TCB member. */
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/* restore registers */
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portRESTORE_FpuReg
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portasmRESTORE_ADDITIONAL_REGISTERS
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portRESTORE_BaseReg
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load_x x2, PORT_CONTEXT_xOFFSET(2)(sp)
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@ -454,6 +610,20 @@ xPortStartFirstTask:
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csrw mtvec, t0
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#endif /* ( portasmHAS_SIFIVE_CLINT != 0 ) */
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#ifdef __riscv_fdiv
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/* we put the FPU in initial state */
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csrr t0, misa /* Get misa */
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li t1, 0x10028 /* 0x10028 = Q,F,D Quad, Single or Double precission floating point */
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and t0, t0, t1
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beqz t0, 1f /* check if Q,F or D is present into misa */
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csrr t0, mstatus /* Floating point unit is present so need to put it into initial state */
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lui t1, 0x1 /* t1 = 0x1 << 12 */
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or t0, t0, t1
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csrw mstatus, t0 /* Set FS to initial state */
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csrwi fcsr, 0 /* Clear Floating-point Control and Status Register */
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1:
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#endif /* __riscv_fdiv */
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/** Set all register to the FirstTask context */
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load_x t2, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( t2 ) /* Read sp from first TCB member. */
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@ -471,6 +641,7 @@ xPortStartFirstTask:
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csrs mie, t0
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#endif /* ( portasmHAS_MTIME != 0 ) */
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portRESTORE_FpuReg
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portasmRESTORE_ADDITIONAL_REGISTERS
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portRESTORE_BaseReg
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@ -627,6 +798,20 @@ chip_specific_stack_frame: /* First add any chip specific registers to the st
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j chip_specific_stack_frame /* Until no more chip specific registers. */
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1:
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#ifdef __riscv_fdiv
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/* Make room for the fpu registers. */
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/* Here we use the memory space needed for all fpu registers instead of using the number of fpu registers */
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/* Thanks to it we usually manage any xxbits core with yybits fpu */
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addi t0, x0, portasmFPU_CONTEXT_WORDSIZE
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fpu_specific_stack_frame:
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beq t0, x0, 1f /* No more space is needed. */
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addi t2, t2, -portWORD_SIZE
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store_x x0, 0(t2) /* Give an initial value of zero. */
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addi t0, t0, -portWORD_SIZE /* Decrement the count space remaining. */
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j fpu_specific_stack_frame /* Until no more space is needed. */
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1:
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#endif /* __riscv_fdiv */
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mv a0, t2
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ret
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.endfunc
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