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Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
This commit is contained in:
Richard Barry
parent
7cc42b2ab6
commit
101806906d
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@ -0,0 +1,74 @@
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/*
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* FreeRTOS Kernel V10.1.1
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* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and t
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o permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_port_specific_extensions.h. There
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* is one freertos_risc_v_port_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_port_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips
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* that include a standard CLINT and do not add to the base set of RISC-V
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* registers.
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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.macro portSAVE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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.macro portRESTORE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -27,6 +27,38 @@
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* 1 tab == 4 spaces!
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* 1 tab == 4 spaces!
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*/
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_port_specific_extensions.h. There
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* is one freertos_risc_v_port_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_port_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips
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* that include a standard CLINT and do not add to the base set of RISC-V
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* registers.
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*
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*/
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#include "freertos_risc_v_port_specific_extensions.h"
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#if __riscv_xlen == 64
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define WORD_SIZE 8
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#define WORD_SIZE 8
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@ -86,6 +118,8 @@ vPortTrapHandler:
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sw x30, 27 * WORD_SIZE( sp )
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sw x30, 27 * WORD_SIZE( sp )
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sw x31, 28 * WORD_SIZE( sp )
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sw x31, 28 * WORD_SIZE( sp )
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portSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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csrr t0, mstatus /* Required for MPIE bit. */
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * WORD_SIZE( sp )
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sw t0, 29 * WORD_SIZE( sp )
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@ -95,25 +129,19 @@ vPortTrapHandler:
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csrr a0, mcause
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csrr a0, mcause
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csrr a1, mepc
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csrr a1, mepc
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test_if_environment_call:
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test_if_asynchronous:
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li t0, 11 /* 11 == environment call when using qemu. */
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srli a2, a0, 0x1f /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
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bne a0, t0, test_if_timer
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beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
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addi a1, a1, 4 /* Synchronous so return to the instruction after the environment call. */
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sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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sw a1, 0( sp ) /* Save updated exception return address. */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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j processed_source
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test_if_timer:
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sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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handle_asynchronous:
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test_if_mtimer:
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lui t0, 0x80000
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lui t0, 0x80000
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addi t1,t0, 7 /* 0x80000007 == machine timer interrupt. */
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addi t1, t0, 7 /* 0x80000007 == machine timer interrupt. */
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bne a0, t1, test_if_external_interrupt
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bne a0, t1, test_if_external_interrupt
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lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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lw t1, pullNextTime /* Load the address of ullNextTime into t1. */
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lw t1, pullNextTime /* Load the address of ullNextTime into t1. */
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lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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j processed_source
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j processed_source
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test_if_external_interrupt:
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test_if_external_interrupt:
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addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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bne a0, t1, is_exception /* Only thing left it can be. */
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bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
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jal vPortHandleInterrupt
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jal vPortHandleInterrupt
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j processed_source
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j processed_source
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handle_synchronous:
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addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
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sw a1, 0( sp ) /* Save updated exception return address. */
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test_if_environment_call:
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li t0, 11 /* 11 == environment call. */
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bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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j processed_source
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is_exception:
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is_exception:
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ebreak
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ebreak
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j is_exception
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j is_exception
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as_yet_unhandled:
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ebreak
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j as_yet_unhandled
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processed_source:
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processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw t0, 29 * WORD_SIZE( sp )
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lw t0, 29 * WORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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csrw mstatus, t0 /* Required for MPIE bit. */
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portRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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lw x1, 1 * WORD_SIZE( sp )
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lw x1, 1 * WORD_SIZE( sp )
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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addi sp, sp, CONTEXT_SIZE
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mret
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mret
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@ -195,35 +240,35 @@ xPortStartFirstTask:
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
|
||||||
lw x29, 26 * WORD_SIZE( sp ) /* t4 */
|
lw x29, 26 * WORD_SIZE( sp ) /* t4 */
|
||||||
lw x30, 27 * WORD_SIZE( sp ) /* t5 */
|
lw x30, 27 * WORD_SIZE( sp ) /* t5 */
|
||||||
lw x31, 28 * WORD_SIZE( sp ) /* t6 */
|
lw x31, 28 * WORD_SIZE( sp ) /* t6 */
|
||||||
addi sp, sp, CONTEXT_SIZE
|
addi sp, sp, CONTEXT_SIZE
|
||||||
csrs mstatus, 8 /* Enable machine interrupts. */
|
csrs mstatus, 8 /* Enable machine interrupts. */
|
||||||
ret
|
ret
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue