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Enhance heap_4.c to prevent blocks accidentally being freed twice, or blocks that don't have a valid block link descriptor being freed.
Update the Cortex-A9 port to include asserts if an ISR safe FreeRTOS function is called from an interrupt that has a higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY (or whatever the CA9 equivalent is called), and also assert if the binary point is not set correctly.
This commit is contained in:
Richard Barry
parent
4894955a08
commit
0f6b0d3a59
5 changed files with 371 additions and 200 deletions
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@ -123,14 +123,19 @@
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number of bits implemented by the interrupt controller. */
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#if configUNIQUE_INTERRUPT_PRIORITIES == 16
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#define portPRIORITY_SHIFT 4
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#define portMAX_BINARY_POINT_VALUE 3
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#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
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#define portPRIORITY_SHIFT 3
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#define portMAX_BINARY_POINT_VALUE 2
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#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
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#define portPRIORITY_SHIFT 2
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#define portMAX_BINARY_POINT_VALUE 1
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#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
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#define portPRIORITY_SHIFT 1
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#define portMAX_BINARY_POINT_VALUE 0
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#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
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#define portPRIORITY_SHIFT 0
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#define portMAX_BINARY_POINT_VALUE 0
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#else
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#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
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#endif
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@ -151,14 +156,22 @@ context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( portSTACK_TYPE ) 0 )
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/* Interrupt controller access addresses. */
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#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
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#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
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#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
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#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
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#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
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#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile unsigned long * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
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#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
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#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
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#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
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#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
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#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
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#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
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#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
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#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile unsigned long * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
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#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
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#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
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#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
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#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile unsigned long * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
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#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile unsigned char * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
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/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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point is zero. */
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#define portBINARY_POINT_BITS ( ( unsigned char ) 0x03 )
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/* Constants required to setup the initial task context. */
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#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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@ -200,11 +213,6 @@ the scheduler starts. As it is stored as part of the task context it will
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automatically be set to 0 when the first task is started. */
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volatile unsigned long ulCriticalNesting = 9999UL;
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/* The value to be written to the interrupt controllers priority mask register
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to mask interrupts that can use the FreeRTOS API without masking higher priority
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interrupts. */
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const unsigned long ulPortAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/* Used to pass constants into the ASM code. The address at which variables are
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placed is the constant value so indirect loads in the asm code are not
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required. */
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@ -313,15 +321,24 @@ unsigned long ulAPSR;
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if( ulAPSR != portAPSR_USER_MODE )
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{
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/* Start the timer that generates the tick ISR. */
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configSETUP_TICK_INTERRUPT();
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/* Only continue if the binary point value is set to its lowest possible
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setting. See the comments in vPortValidateInterruptPriority() below for
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more information. */
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configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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{
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/* Start the timer that generates the tick ISR. */
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configSETUP_TICK_INTERRUPT();
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__enable_irq();
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vPortRestoreTaskContext();
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__enable_irq();
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vPortRestoreTaskContext();
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}
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}
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/* Will only get here if xTaskStartScheduler() was called with the CPU in
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a non-privileged mode. */
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a non-privileged mode or the binary point register was not set to its lowest
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possible value. */
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return 0;
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}
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/*-----------------------------------------------------------*/
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@ -371,7 +388,7 @@ void FreeRTOS_Tick_Handler( void )
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handler runs at the lowest priority, so interrupts cannot already be masked,
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so there is no need to save and restore the current mask value. */
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__disable_irq();
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portICCPMR_PRIORITY_MASK_REGISTER = ulPortAPIPriorityMask;
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portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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__asm( "DSB \n"
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"ISB \n" );
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__enable_irq();
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@ -414,7 +431,7 @@ unsigned long ulPortSetInterruptMask( void )
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unsigned long ulReturn;
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__disable_irq();
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if( portICCPMR_PRIORITY_MASK_REGISTER == ulPortAPIPriorityMask )
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if( portICCPMR_PRIORITY_MASK_REGISTER == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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{
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/* Interrupts were already masked. */
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ulReturn = pdTRUE;
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@ -422,7 +439,7 @@ unsigned long ulReturn;
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else
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{
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ulReturn = pdFALSE;
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portICCPMR_PRIORITY_MASK_REGISTER = ulPortAPIPriorityMask;
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portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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__asm( "DSB \n"
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"ISB \n" );
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}
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@ -430,5 +447,47 @@ unsigned long ulReturn;
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return ulReturn;
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}
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/*-----------------------------------------------------------*/
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#if( configASSERT_DEFINED == 1 )
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void vPortValidateInterruptPriority( void )
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{
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/* The following assertion will fail if a service routine (ISR) for
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an interrupt that has been assigned a priority above
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configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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function. ISR safe FreeRTOS API functions must *only* be called
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from interrupts that have been assigned a priority at or below
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configMAX_SYSCALL_INTERRUPT_PRIORITY.
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Numerically low interrupt priority numbers represent logically high
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interrupt priorities, therefore the priority of the interrupt must
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be set to a value equal to or numerically *higher* than
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configMAX_SYSCALL_INTERRUPT_PRIORITY.
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FreeRTOS maintains separate thread and ISR API functions to ensure
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interrupt entry is as fast and simple as possible.
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The following links provide detailed information:
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http://www.freertos.org/RTOS-Cortex-M3-M4.html
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http://www.freertos.org/FAQHelp.html */
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configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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/* Priority grouping: The interrupt controller (GIC) allows the bits
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that define each interrupt's priority to be split between bits that
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define the interrupt's pre-emption priority bits and bits that define
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the interrupt's sub-priority. For simplicity all bits must be defined
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to be pre-emption priority bits. The following assertion will fail if
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this is not the case (if some bits represent a sub-priority).
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The priority grouping is configured by the GIC's binary point register
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(ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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possible value (which may be above 0). */
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configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
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}
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#endif /* configASSERT_DEFINED */
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