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RX GCC port - Introduce macros that perform the interrupt entry and exit manually, then move the asm code back as naked functions within the port.c file.
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Richard Barry
parent
c788ecec17
commit
0ef04cd7bd
3 changed files with 169 additions and 219 deletions
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@ -86,20 +86,19 @@ which would require the old IPL to be read first and stored in a local variable.
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* Function to start the first task executing - written in asm code as direct
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* access to registers is required.
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*/
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extern void prvStartFirstTask( void );
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static void prvStartFirstTask( void ) __attribute__((naked));
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/*
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* Software interrupt handler. Performs the actual context switch (saving and
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* restoring of registers). Written in asm code as direct register access is
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* required.
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*/
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static void prvYieldHandler( void );
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void vSoftwareInterruptISR( void ) __attribute__((naked));
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/*
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* The tick ISR handler. The peripheral used is configured by the application
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* via a hook/callback function.
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* The tick interrupt handler.
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*/
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void vTickISR( void ) __attribute__((interrupt));
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void vTickISR( void ) __attribute__((naked));
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/*-----------------------------------------------------------*/
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@ -203,10 +202,143 @@ extern void vApplicationSetupTimerInterrupt( void );
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented as there is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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static void prvStartFirstTask( void )
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{
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__asm volatile
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(
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/* When starting the scheduler there is nothing that needs moving to the
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interrupt stack because the function is not called from an interrupt.
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Just ensure the current stack is the user stack. */
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"SETPSW U \n" \
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/* Obtain the location of the stack associated with which ever task
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pxCurrentTCB is currently pointing to. */
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"MOV.L #_pxCurrentTCB, R15 \n" \
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"MOV.L [R15], R15 \n" \
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"MOV.L [R15], R0 \n" \
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/* Restore the registers from the stack of the task pointed to by
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pxCurrentTCB. */
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"POP R15 \n" \
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/* Accumulator low 32 bits. */
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"MVTACLO R15 \n" \
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"POP R15 \n" \
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/* Accumulator high 32 bits. */
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"MVTACHI R15 \n" \
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"POP R15 \n" \
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/* Floating point status word. */
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"MVTC R15, FPSW \n" \
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/* R1 to R15 - R0 is not included as it is the SP. */
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"POPM R1-R15 \n" \
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/* This pops the remaining registers. */
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"RTE \n" \
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"NOP \n" \
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"NOP \n"
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);
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}
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/*-----------------------------------------------------------*/
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void vSoftwareInterruptISR( void )
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{
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__asm volatile
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(
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/* Re-enable interrupts. */
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"SETPSW I \n" \
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/* Move the data that was automatically pushed onto the interrupt stack when
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the interrupt occurred from the interrupt stack to the user stack.
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R15 is saved before it is clobbered. */
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"PUSH.L R15 \n" \
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/* Read the user stack pointer. */
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"MVFC USP, R15 \n" \
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/* Move the address down to the data being moved. */
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"SUB #12, R15 \n" \
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"MVTC R15, USP \n" \
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/* Copy the data across, R15, then PC, then PSW. */
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"MOV.L [ R0 ], [ R15 ] \n" \
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"MOV.L 4[ R0 ], 4[ R15 ] \n" \
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"MOV.L 8[ R0 ], 8[ R15 ] \n" \
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/* Move the interrupt stack pointer to its new correct position. */
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"ADD #12, R0 \n" \
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/* All the rest of the registers are saved directly to the user stack. */
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"SETPSW U \n" \
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/* Save the rest of the general registers (R15 has been saved already). */
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"PUSHM R1-R14 \n" \
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/* Save the FPSW and accumulator. */
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"MVFC FPSW, R15 \n" \
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"PUSH.L R15 \n" \
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"MVFACHI R15 \n" \
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"PUSH.L R15 \n" \
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/* Middle word. */
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"MVFACMI R15 \n" \
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/* Shifted left as it is restored to the low order word. */
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"SHLL #16, R15 \n" \
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"PUSH.L R15 \n" \
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/* Save the stack pointer to the TCB. */
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"MOV.L #_pxCurrentTCB, R15 \n" \
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"MOV.L [ R15 ], R15 \n" \
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"MOV.L R0, [ R15 ] \n" \
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/* Ensure the interrupt mask is set to the syscall priority while the kernel
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structures are being accessed. */
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"MVTIPL %0 \n" \
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/* Select the next task to run. */
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"BSR.A _vTaskSwitchContext \n" \
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/* Reset the interrupt mask as no more data structure access is required. */
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"MVTIPL %1 \n" \
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/* Load the stack pointer of the task that is now selected as the Running
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state task from its TCB. */
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"MOV.L #_pxCurrentTCB,R15 \n" \
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"MOV.L [ R15 ], R15 \n" \
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"MOV.L [ R15 ], R0 \n" \
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/* Restore the context of the new task. The PSW (Program Status Word) and
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PC will be popped by the RTE instruction. */
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"POP R15 \n" \
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"MVTACLO R15 \n" \
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"POP R15 \n" \
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"MVTACHI R15 \n" \
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"POP R15 \n" \
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"MVTC R15, FPSW \n" \
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"POPM R1-R15 \n" \
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"RTE \n" \
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"NOP \n" \
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"NOP "
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:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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);
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}
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/*-----------------------------------------------------------*/
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void vTickISR( void )
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{
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/* Re-enable interrupts. */
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__asm volatile( "SETPSW I" );
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/* This is a naked function. This macro saves registers then re-enables
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interrupts. */
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portENTER_INTERRUPT();
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/* Increment the tick, and perform any processing the new tick value
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necessitates. Ensure IPL is at the max syscall value first. */
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@ -220,14 +352,34 @@ void vTickISR( void )
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#if( configUSE_PREEMPTION == 1 )
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taskYIELD();
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#endif
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/* Retore registers, then return. */
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portEXIT_INTERRUPT();
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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unsigned long ulPortGetIPL( void )
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{
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/* Not implemented as there is nothing to return to. */
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__asm volatile
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(
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"MVFC PSW, R1 \n" \
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"SHLR #24, R1 \n" \
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"RTS "
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);
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}
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/*-----------------------------------------------------------*/
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void vPortSetIPL( unsigned long ulNewIPL )
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{
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__asm volatile
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(
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"PUSH R5 \n" \
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"MVFC PSW, R5 \n" \
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"SHLL #24, R1 \n" \
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"AND #-0F000001H, R5 \n" \
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"OR R1, R5 \n" \
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"MVTC R5, PSW \n" \
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"POP R5 \n" \
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"RTS "
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);
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}
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