From de276eb02397ced5c55f40eea8b8602af3c98a34 Mon Sep 17 00:00:00 2001 From: ActoryOu Date: Sat, 2 Nov 2024 01:09:49 +0800 Subject: [PATCH 1/4] Fix spelling typos (#1168) * Fix spelling --------- Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> --- History.txt | 8 ++++---- examples/coverity/README.md | 2 +- examples/template_configuration/FreeRTOSConfig.h | 2 +- include/task.h | 2 +- portable/ARMv8M/non_secure/port.c | 2 +- .../non_secure/portable/GCC/ARM_CM33/portasm.c | 6 +++--- .../portable/GCC/ARM_CM33_NTZ/portasm.c | 6 +++--- .../non_secure/portable/IAR/ARM_CM33/portasm.s | 6 +++--- .../portable/IAR/ARM_CM33_NTZ/portasm.s | 6 +++--- portable/ARMv8M/non_secure/portasm.h | 2 +- portable/ARMv8M/non_secure/portmacrocommon.h | 2 +- portable/ARMv8M/secure/context/secure_context.c | 2 +- portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h | 8 ++++---- portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h | 14 +++++++------- portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h | 8 ++++---- portable/GCC/ARM_AARCH64/port.c | 2 +- portable/GCC/ARM_CA9/port.c | 2 +- portable/GCC/ARM_CM0/portasm.h | 2 +- portable/GCC/ARM_CM23/non_secure/port.c | 2 +- portable/GCC/ARM_CM23/non_secure/portasm.h | 2 +- .../GCC/ARM_CM23/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM23/secure/secure_context.c | 2 +- portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 2 +- portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h | 2 +- .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM33/non_secure/port.c | 2 +- portable/GCC/ARM_CM33/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM33/non_secure/portasm.h | 2 +- .../GCC/ARM_CM33/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM33/secure/secure_context.c | 2 +- portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 2 +- portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h | 2 +- .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM35P/non_secure/port.c | 2 +- portable/GCC/ARM_CM35P/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM35P/non_secure/portasm.h | 2 +- .../GCC/ARM_CM35P/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM35P/secure/secure_context.c | 2 +- portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 2 +- portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h | 2 +- .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM4_MPU/portmacro.h | 2 +- portable/GCC/ARM_CM55/non_secure/port.c | 2 +- portable/GCC/ARM_CM55/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM55/non_secure/portasm.h | 2 +- .../GCC/ARM_CM55/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM55/secure/secure_context.c | 2 +- portable/GCC/ARM_CM55_NTZ/non_secure/port.c | 2 +- portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h | 2 +- .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM85/non_secure/port.c | 2 +- portable/GCC/ARM_CM85/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM85/non_secure/portasm.h | 2 +- .../GCC/ARM_CM85/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CM85/secure/secure_context.c | 2 +- portable/GCC/ARM_CM85_NTZ/non_secure/port.c | 2 +- portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c | 6 +++--- portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h | 2 +- .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 2 +- portable/GCC/ARM_CRx_MPU/port.c | 2 +- portable/GCC/ARM_CRx_MPU/portmacro.h | 4 ++-- portable/GCC/ARM_CRx_MPU/portmacro_asm.h | 2 +- portable/GCC/AVR32_UC3/port.c | 2 +- portable/IAR/ARM_CA9/port.c | 2 +- portable/IAR/ARM_CM23/non_secure/port.c | 2 +- portable/IAR/ARM_CM23/non_secure/portasm.h | 2 +- .../IAR/ARM_CM23/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM23/secure/secure_context.c | 2 +- portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 2 +- portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h | 2 +- .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM33/non_secure/port.c | 2 +- portable/IAR/ARM_CM33/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM33/non_secure/portasm.s | 6 +++--- .../IAR/ARM_CM33/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM33/secure/secure_context.c | 2 +- portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 2 +- portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s | 6 +++--- .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM35P/non_secure/port.c | 2 +- portable/IAR/ARM_CM35P/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM35P/non_secure/portasm.s | 6 +++--- .../IAR/ARM_CM35P/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM35P/secure/secure_context.c | 2 +- portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 2 +- portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s | 6 +++--- .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM4F_MPU/portmacro.h | 2 +- portable/IAR/ARM_CM55/non_secure/port.c | 2 +- portable/IAR/ARM_CM55/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM55/non_secure/portasm.s | 6 +++--- .../IAR/ARM_CM55/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM55/secure/secure_context.c | 2 +- portable/IAR/ARM_CM55_NTZ/non_secure/port.c | 2 +- portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s | 6 +++--- .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM85/non_secure/port.c | 2 +- portable/IAR/ARM_CM85/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM85/non_secure/portasm.s | 6 +++--- .../IAR/ARM_CM85/non_secure/portmacrocommon.h | 2 +- portable/IAR/ARM_CM85/secure/secure_context.c | 2 +- portable/IAR/ARM_CM85_NTZ/non_secure/port.c | 2 +- portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h | 2 +- portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s | 6 +++--- .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 2 +- portable/IAR/AVR32_UC3/port.c | 2 +- portable/IAR/AtmelSAM7S64/AT91SAM7S64.h | 4 ++-- portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h | 4 ++-- portable/IAR/AtmelSAM7S64/AT91SAM7X128.h | 8 ++++---- portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h | 8 ++++---- portable/IAR/AtmelSAM7S64/AT91SAM7X256.h | 8 ++++---- portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h | 8 ++++---- portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h | 16 ++++++++-------- portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h | 10 +++++----- portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h | 10 +++++----- portable/MPLAB/PIC24_dsPIC/port.c | 2 +- portable/RVDS/ARM_CA9/port.c | 2 +- portable/RVDS/ARM_CM4_MPU/portmacro.h | 2 +- portable/ThirdParty/GCC/ARC_EM_HS/port.c | 2 +- portable/ThirdParty/GCC/ARC_v1/port.c | 2 +- portable/ThirdParty/GCC/Posix/port.c | 2 +- portable/ThirdParty/GCC/Posix/portmacro.h | 2 +- .../ThirdParty/GCC/RP2040/include/portmacro.h | 2 +- .../Xtensa_ESP32/include/FreeRTOSConfig_arch.h | 2 +- portable/WizC/PIC18/portmacro.h | 2 +- portable/oWatcom/16BitDOS/common/portasm.h | 2 +- queue.c | 2 +- 133 files changed, 218 insertions(+), 218 deletions(-) diff --git a/History.txt b/History.txt index d5293b90b..ae29ae9c9 100644 --- a/History.txt +++ b/History.txt @@ -528,7 +528,7 @@ Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021 in more files. + Other minor updates include adding additional configASSERT() checks and correcting and improving code comments. - + Go look at the smp branch to see the progress towards the Symetric + + Go look at the smp branch to see the progress towards the Symmetric Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020 @@ -2015,7 +2015,7 @@ Changes between V6.1.0 and V6.1.1 released January 14 2011 Embedded Workbench. + Added a new port for the MSP430X core using the IAR Embedded Workbench. + Updated all the RX62N demo projects that target the Renesas Demonstration - Kit (RDK) to take into account the revered LED wiring on later hardware + Kit (RDK) to take into account the reversed LED wiring on later hardware revisions, and the new J-Link debug interface DLL. + Updated all the RX62N demo projects so the IO page served by the example embedded web server works with all web browsers. @@ -3174,7 +3174,7 @@ Changes between V1.2.3 and V1.2.4 xSerialPortInitMinimal() and the function xPortInit() has been renamed to xSerialPortInit(). + The function sSerialPutChar() has been renamed cSerialPutChar() and - the function return type chaned to portCHAR. + the function return type changed to portCHAR. + The integer and flop tasks now include calls to tskYIELD(), allowing them to be used with the cooperative scheduler. + All the demo applications now use the integer and comtest tasks when the @@ -3308,7 +3308,7 @@ Changes between V1.01 and V1.2.0 ports to allocate a different maximum number of priorities. + By default the trace facility is off, previously USE_TRACE_FACILITY was defined. - + comtest.c now uses a psuedo random delay between sends. This allows for + + comtest.c now uses a pseudo random delay between sends. This allows for better testing as the interrupts do not arrive at regular intervals. + Minor change to the Flashlite serial port driver. The driver is written to demonstrate the scheduler and is not written to be efficient. diff --git a/examples/coverity/README.md b/examples/coverity/README.md index 688577d37..60df69343 100644 --- a/examples/coverity/README.md +++ b/examples/coverity/README.md @@ -35,7 +35,7 @@ commands in a terminal: ~~~ 2. Create the build files using CMake in a `build` directory: -Singe core FreeRTOS: +Single core FreeRTOS: ~~~ cmake -B build -S examples/coverity ~~~ diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h index fe21f1108..8c5e53066 100644 --- a/examples/template_configuration/FreeRTOSConfig.h +++ b/examples/template_configuration/FreeRTOSConfig.h @@ -643,7 +643,7 @@ * contain the most recent error for that task. */ #define configUSE_POSIX_ERRNO 0 -/* Set the following INCLUDE_* constants to 1 to incldue the named API function, +/* Set the following INCLUDE_* constants to 1 to include the named API function, * or 0 to exclude the named API function. Most linkers will remove unused * functions even when the constant is 1. */ #define INCLUDE_vTaskPrioritySet 1 diff --git a/include/task.h b/include/task.h index 60535254c..0414eb9e2 100644 --- a/include/task.h +++ b/include/task.h @@ -2372,7 +2372,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; * * WARN: This function assumes that the pcWriteBuffer is of length * configSTATS_BUFFER_MAX_LENGTH. This function is there only for - * backward compatiblity. New applications are recommended to use + * backward compatibility. New applications are recommended to use * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer * explicitly. * diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c index f09840a46..aaeccaa35 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c @@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c index 47996cd9e..7cdff7005 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c @@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s index f4b7ab20f..212688d61 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s @@ -216,7 +216,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -275,7 +275,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -409,7 +409,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s index be06f67ad..9d6c6a7ef 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s @@ -202,7 +202,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -246,7 +246,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -340,7 +340,7 @@ PendSV_Handler: str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/ARMv8M/non_secure/portasm.h b/portable/ARMv8M/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/ARMv8M/non_secure/portasm.h +++ b/portable/ARMv8M/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/ARMv8M/non_secure/portmacrocommon.h +++ b/portable/ARMv8M/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/ARMv8M/secure/context/secure_context.c b/portable/ARMv8M/secure/context/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/ARMv8M/secure/context/secure_context.c +++ b/portable/ARMv8M/secure/context/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h index a335e4ad2..e5aa862e0 100644 --- a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h +++ b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h @@ -627,8 +627,8 @@ typedef struct _AT91S_MC /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ @@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC AT91_REG EMAC_ECOL; /* Excessive Collision Register */ AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ @@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES #define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ #define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ #define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ -#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ #define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ /* ========== Register definition for PDC_ADC peripheral ========== */ #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ diff --git a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h index a680c4861..a148b18a6 100644 --- a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h +++ b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h @@ -627,8 +627,8 @@ typedef struct _AT91S_MC /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ @@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC AT91_REG EMAC_ECOL; /* Excessive Collision Register */ AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ @@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES #define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ #define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ #define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ -#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ #define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ /* ========== Register definition for PDC_ADC peripheral ========== */ #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ @@ -3125,9 +3125,9 @@ AT91C_MC_RCB EQU( 0x1 << 0 ); -( MC ) Remap Command Bit /* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ AT91C_MC_UNDADD EQU( 0x1 << 0 ); --( MC ) Undefined Addess Abort Status +-( MC ) Undefined Address Abort Status AT91C_MC_MISADD EQU( 0x1 << 1 ); --( MC ) Misaligned Addess Abort Status +-( MC ) Misaligned Address Abort Status AT91C_MC_ABTSZ EQU( 0x3 << 8 ); -( MC ) Abort Size Status AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 ); @@ -5698,7 +5698,7 @@ AT91C_US_CLKS EQU( 0x3 << 4 ); AT91C_EMAC_SA3H EQU( 0xFFFDC0AC ); -( EMAC ) Specific Address 3 Top, Last 2 bytes AT91C_EMAC_RRE EQU( 0xFFFDC06C ); - -( EMAC ) Receive Ressource Error Register + -( EMAC ) Receive Resource Error Register AT91C_EMAC_STE EQU( 0xFFFDC084 ); -( EMAC ) SQE Test Error Register /* - ========== Register definition for PDC_ADC peripheral ========== */ diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h index 0d9a70884..5de1aee3b 100644 --- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h +++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h @@ -210,7 +210,7 @@ /** \brief Set the next receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RNPR = ( unsigned int ) address; @@ -222,7 +222,7 @@ /** \brief Set the next transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TNPR = ( unsigned int ) address; @@ -234,7 +234,7 @@ /** \brief Set the receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RPR = ( unsigned int ) address; @@ -246,7 +246,7 @@ /** \brief Set the transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TPR = ( unsigned int ) address; diff --git a/portable/GCC/ARM_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c index 238874edc..7f080db74 100644 --- a/portable/GCC/ARM_AARCH64/port.c +++ b/portable/GCC/ARM_AARCH64/port.c @@ -547,7 +547,7 @@ UBaseType_t uxPortSetInterruptMask( void ) * this is not the case (if some bits represent a sub-priority). * * The priority grouping is configured by the GIC's binary point register - * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); } diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c index 79b60a933..0fd9dd471 100644 --- a/portable/GCC/ARM_CA9/port.c +++ b/portable/GCC/ARM_CA9/port.c @@ -562,7 +562,7 @@ uint32_t ulPortSetInterruptMask( void ) * this is not the case (if some bits represent a sub-priority). * * The priority grouping is configured by the GIC's binary point register - * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); } diff --git a/portable/GCC/ARM_CM0/portasm.h b/portable/GCC/ARM_CM0/portasm.h index 77e87b132..346507531 100644 --- a/portable/GCC/ARM_CM0/portasm.h +++ b/portable/GCC/ARM_CM0/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.h b/portable/GCC/ARM_CM23/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM23/non_secure/portasm.h +++ b/portable/GCC/ARM_CM23/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/GCC/ARM_CM23/secure/secure_context.c +++ b/portable/GCC/ARM_CM23/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c index f09840a46..aaeccaa35 100644 --- a/portable/GCC/ARM_CM33/non_secure/portasm.c +++ b/portable/GCC/ARM_CM33/non_secure/portasm.c @@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.h b/portable/GCC/ARM_CM33/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM33/non_secure/portasm.h +++ b/portable/GCC/ARM_CM33/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/GCC/ARM_CM33/secure/secure_context.c +++ b/portable/GCC/ARM_CM33/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c index 47996cd9e..7cdff7005 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c @@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM35P/non_secure/port.c +++ b/portable/GCC/ARM_CM35P/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c index f09840a46..aaeccaa35 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portasm.c +++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c @@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.h b/portable/GCC/ARM_CM35P/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portasm.h +++ b/portable/GCC/ARM_CM35P/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.c b/portable/GCC/ARM_CM35P/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_context.c +++ b/portable/GCC/ARM_CM35P/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c index 47996cd9e..7cdff7005 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c @@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h index d9677a72b..264887e8e 100644 --- a/portable/GCC/ARM_CM4_MPU/portmacro.h +++ b/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -98,7 +98,7 @@ typedef unsigned long UBaseType_t; #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM55/non_secure/port.c +++ b/portable/GCC/ARM_CM55/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c index f09840a46..aaeccaa35 100644 --- a/portable/GCC/ARM_CM55/non_secure/portasm.c +++ b/portable/GCC/ARM_CM55/non_secure/portasm.c @@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.h b/portable/GCC/ARM_CM55/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM55/non_secure/portasm.h +++ b/portable/GCC/ARM_CM55/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM55/secure/secure_context.c b/portable/GCC/ARM_CM55/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/GCC/ARM_CM55/secure/secure_context.c +++ b/portable/GCC/ARM_CM55/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c index 47996cd9e..7cdff7005 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c @@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM85/non_secure/port.c +++ b/portable/GCC/ARM_CM85/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c index f09840a46..aaeccaa35 100644 --- a/portable/GCC/ARM_CM85/non_secure/portasm.c +++ b/portable/GCC/ARM_CM85/non_secure/portasm.c @@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.h b/portable/GCC/ARM_CM85/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM85/non_secure/portasm.h +++ b/portable/GCC/ARM_CM85/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/GCC/ARM_CM85/secure/secure_context.c +++ b/portable/GCC/ARM_CM85/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c index 47996cd9e..7cdff7005 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c @@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT " \n" " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bx lr \n" /* Return. */ @@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " \n" " select_next_task: \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" @@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ - " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" " bl vTaskSwitchContext \n" diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/GCC/ARM_CRx_MPU/port.c b/portable/GCC/ARM_CRx_MPU/port.c index e4904e58d..6b8d77cd6 100644 --- a/portable/GCC/ARM_CRx_MPU/port.c +++ b/portable/GCC/ARM_CRx_MPU/port.c @@ -100,7 +100,7 @@ PRIVILEGED_DATA static BaseType_t prvPortSchedulerRunning = pdFALSE; * @param ulBufferLength Length of the given buffer. * @param ulAccessRequested Access requested. * - * @return pdTRUE if MPU region settins authorizes the requested access to the + * @return pdTRUE if MPU region settings authorizes the requested access to the * given buffer, pdFALSE otherwise. */ PRIVILEGED_FUNCTION static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion, diff --git a/portable/GCC/ARM_CRx_MPU/portmacro.h b/portable/GCC/ARM_CRx_MPU/portmacro.h index 7e80f093e..1eb8f0162 100644 --- a/portable/GCC/ARM_CRx_MPU/portmacro.h +++ b/portable/GCC/ARM_CRx_MPU/portmacro.h @@ -236,7 +236,7 @@ typedef uint32_t TickType_t; #define portTICK_TYPE_IS_ATOMIC 1 /** - * @brief The number of miliseconds between system ticks. + * @brief The number of milliseconds between system ticks. * * @ingroup System Clock */ @@ -380,7 +380,7 @@ void vPortExitCritical( void ); * @note The processor privilege level is determined by checking the * mode bits [4:0] of the Current Program Status Register (CPSR). * - * @return pdTRUE, if the processer is privileged, pdFALSE otherwise. + * @return pdTRUE, if the processor is privileged, pdFALSE otherwise. */ BaseType_t xPortIsPrivileged( void ); diff --git a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h index a113ac02d..c9573e419 100644 --- a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h +++ b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h @@ -36,7 +36,7 @@ extern "C" { #include "FreeRTOSConfig.h" #ifndef configTOTAL_MPU_REGIONS - #error "Set configTOTAL_MPU_REGIONS to the humber of MPU regions in FreeRTOSConfig.h" + #error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h" #elif( configTOTAL_MPU_REGIONS == 12 ) #define portMPU_TOTAL_REGIONS ( 12UL ) #elif( configTOTAL_MPU_REGIONS == 16 ) diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c index bd8b0bd2b..984ef56a0 100644 --- a/portable/GCC/AVR32_UC3/port.c +++ b/portable/GCC/AVR32_UC3/port.c @@ -401,7 +401,7 @@ static void prvSetupTimerInterrupt( void ) #if ( configTICK_USE_TC == 1 ) volatile avr32_tc_t * tc = &AVR32_TC; - /* Options for waveform genration. */ + /* Options for waveform generation. */ tc_waveform_opt_t waveform_opt = { .channel = configTICK_TC_CHANNEL, /* Channel selection. */ diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c index f26ae3790..66852f9a7 100644 --- a/portable/IAR/ARM_CA9/port.c +++ b/portable/IAR/ARM_CA9/port.c @@ -438,7 +438,7 @@ uint32_t ulPortSetInterruptMask( void ) * this is not the case (if some bits represent a sub-priority). * * The priority grouping is configured by the GIC's binary point register - * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); } diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.h b/portable/IAR/ARM_CM23/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM23/non_secure/portasm.h +++ b/portable/IAR/ARM_CM23/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM23/secure/secure_context.c b/portable/IAR/ARM_CM23/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/IAR/ARM_CM23/secure/secure_context.c +++ b/portable/IAR/ARM_CM23/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.h b/portable/IAR/ARM_CM33/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM33/non_secure/portasm.h +++ b/portable/IAR/ARM_CM33/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s index f4b7ab20f..212688d61 100644 --- a/portable/IAR/ARM_CM33/non_secure/portasm.s +++ b/portable/IAR/ARM_CM33/non_secure/portasm.s @@ -216,7 +216,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -275,7 +275,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -409,7 +409,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM33/secure/secure_context.c b/portable/IAR/ARM_CM33/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/IAR/ARM_CM33/secure/secure_context.c +++ b/portable/IAR/ARM_CM33/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s index be06f67ad..9d6c6a7ef 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s @@ -202,7 +202,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -246,7 +246,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -340,7 +340,7 @@ PendSV_Handler: str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM35P/non_secure/port.c +++ b/portable/IAR/ARM_CM35P/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.h b/portable/IAR/ARM_CM35P/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portasm.h +++ b/portable/IAR/ARM_CM35P/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s index f4b7ab20f..212688d61 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portasm.s +++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s @@ -216,7 +216,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -275,7 +275,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -409,7 +409,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.c b/portable/IAR/ARM_CM35P/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_context.c +++ b/portable/IAR/ARM_CM35P/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s index be06f67ad..9d6c6a7ef 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s @@ -202,7 +202,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -246,7 +246,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -340,7 +340,7 @@ PendSV_Handler: str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h index f7f8b51f1..246b82dde 100644 --- a/portable/IAR/ARM_CM4F_MPU/portmacro.h +++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h @@ -100,7 +100,7 @@ typedef unsigned long UBaseType_t; #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM55/non_secure/port.c +++ b/portable/IAR/ARM_CM55/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.h b/portable/IAR/ARM_CM55/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM55/non_secure/portasm.h +++ b/portable/IAR/ARM_CM55/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s index f4b7ab20f..212688d61 100644 --- a/portable/IAR/ARM_CM55/non_secure/portasm.s +++ b/portable/IAR/ARM_CM55/non_secure/portasm.s @@ -216,7 +216,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -275,7 +275,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -409,7 +409,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM55/secure/secure_context.c b/portable/IAR/ARM_CM55/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/IAR/ARM_CM55/secure/secure_context.c +++ b/portable/IAR/ARM_CM55/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s index be06f67ad..9d6c6a7ef 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s @@ -202,7 +202,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -246,7 +246,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -340,7 +340,7 @@ PendSV_Handler: str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM85/non_secure/port.c +++ b/portable/IAR/ARM_CM85/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.h b/portable/IAR/ARM_CM85/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM85/non_secure/portasm.h +++ b/portable/IAR/ARM_CM85/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s index f4b7ab20f..212688d61 100644 --- a/portable/IAR/ARM_CM85/non_secure/portasm.s +++ b/portable/IAR/ARM_CM85/non_secure/portasm.s @@ -216,7 +216,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -275,7 +275,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -409,7 +409,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/ARM_CM85/secure/secure_context.c b/portable/IAR/ARM_CM85/secure/secure_context.c index 72fb3862c..3aa335e63 100644 --- a/portable/IAR/ARM_CM85/secure/secure_context.c +++ b/portable/IAR/ARM_CM85/secure/secure_context.c @@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 5b399358e..a33dfa43c 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -56,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h index bd5a2bfca..b7021b024 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h @@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s index be06f67ad..9d6c6a7ef 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s @@ -202,7 +202,7 @@ vStartFirstTask: ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -246,7 +246,7 @@ PendSV_Handler: select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -340,7 +340,7 @@ PendSV_Handler: str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 3cf65761f..cd83bee57 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c index 7a1cc640b..dbe121cca 100644 --- a/portable/IAR/AVR32_UC3/port.c +++ b/portable/IAR/AVR32_UC3/port.c @@ -374,7 +374,7 @@ static void prvSetupTimerInterrupt( void ) #if ( configTICK_USE_TC == 1 ) volatile avr32_tc_t * tc = &AVR32_TC; - /* Options for waveform genration. */ + /* Options for waveform generation. */ tc_waveform_opt_t waveform_opt = { .channel = configTICK_TC_CHANNEL, /* Channel selection. */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h index 2dbceba43..6df767884 100644 --- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h @@ -562,8 +562,8 @@ typedef struct _AT91S_MC /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h index 9d95f3eb7..a39150071 100644 --- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h @@ -487,8 +487,8 @@ /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h index b8a7652f4..a143430db 100644 --- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h @@ -627,8 +627,8 @@ typedef struct _AT91S_MC /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ @@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC AT91_REG EMAC_ECOL; /* Excessive Collision Register */ AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ @@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES #define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ #define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ #define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ -#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ #define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ /* ========== Register definition for PDC_ADC peripheral ========== */ #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h index fe701970e..78ea37595 100644 --- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h @@ -411,8 +411,8 @@ /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ @@ -1234,7 +1234,7 @@ #define EMAC_ECOL ( 96 ) /* Excessive Collision Register */ #define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */ #define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */ -#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */ +#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */ #define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */ #define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */ #define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */ @@ -2096,7 +2096,7 @@ #define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ #define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ #define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ -#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ #define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ /* ========== Register definition for PDC_ADC peripheral ========== */ #define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h index 98e1babc2..f51209974 100644 --- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h @@ -627,8 +627,8 @@ typedef struct _AT91S_MC /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ @@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC AT91_REG EMAC_ECOL; /* Excessive Collision Register */ AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_RRE; /* Receive Ressource Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ @@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES #define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ #define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ #define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ -#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ #define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ /* ========== Register definition for PDC_ADC peripheral ========== */ #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h index 5c0be5efc..8471ca44d 100644 --- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h @@ -411,8 +411,8 @@ /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ #define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ -#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */ -#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ #define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ #define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ #define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ @@ -1234,7 +1234,7 @@ #define EMAC_ECOL ( 96 ) /* Excessive Collision Register */ #define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */ #define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */ -#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */ +#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */ #define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */ #define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */ #define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */ @@ -2096,7 +2096,7 @@ #define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ #define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ #define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ -#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */ +#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ #define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ /* ========== Register definition for PDC_ADC peripheral ========== */ #define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h index a392be1a7..c53e6c8af 100644 --- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h +++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h @@ -60,7 +60,7 @@ __inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC co /**---------------------------------------------------------------------------- */ /** \fn AT91F_MC_EFC_GetModeReg */ -/** \brief Return MC EFC Mode Regsiter */ +/** \brief Return MC EFC Mode Register */ /**---------------------------------------------------------------------------- */ __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */ { @@ -69,7 +69,7 @@ __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a M /**---------------------------------------------------------------------------- */ /** \fn AT91F_MC_EFC_ComputeFMCN */ -/** \brief Return MC EFC Mode Regsiter */ +/** \brief Return MC EFC Mode Register */ /**---------------------------------------------------------------------------- */ __inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */ { @@ -123,7 +123,7 @@ __inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg /** \brief Set the next receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RNPR = ( unsigned int ) address; @@ -135,7 +135,7 @@ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC /** \brief Set the next transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TNPR = ( unsigned int ) address; @@ -147,7 +147,7 @@ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC /** \brief Set the receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RPR = ( unsigned int ) address; @@ -159,7 +159,7 @@ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC con /** \brief Set the transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TPR = ( unsigned int ) address; @@ -742,7 +742,7 @@ __inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI, /**---------------------------------------------------------------------------- */ /** \fn AT91F_SPI_Close */ -/** \brief Close SPI: disable IT disable transfert, close PDC */ +/** \brief Close SPI: disable IT disable transfer, close PDC */ /**---------------------------------------------------------------------------- */ __inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */ { @@ -1063,7 +1063,7 @@ __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg poin /**---------------------------------------------------------------------------- */ /** \fn AT91F_CKGR_CfgMainOscStartUpTime */ -/** \brief Cfg MOR Register according to the main osc startup time */ +/** \brief Cfg MORE Register according to the main osc startup time */ /**---------------------------------------------------------------------------- */ __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h index 61fbb1f79..4fc975894 100644 --- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h +++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h @@ -210,7 +210,7 @@ /** \brief Set the next receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RNPR = ( unsigned int ) address; @@ -222,7 +222,7 @@ /** \brief Set the next transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TNPR = ( unsigned int ) address; @@ -234,7 +234,7 @@ /** \brief Set the receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RPR = ( unsigned int ) address; @@ -246,7 +246,7 @@ /** \brief Set the transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TPR = ( unsigned int ) address; @@ -1054,7 +1054,7 @@ /**---------------------------------------------------------------------------- */ /** \fn AT91F_CKGR_CfgMainOscStartUpTime */ -/** \brief Cfg MOR Register according to the main osc startup time */ +/** \brief Cfg MORE Register according to the main osc startup time */ /**---------------------------------------------------------------------------- */ __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h index 0d9a70884..4ac85fb96 100644 --- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h +++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h @@ -210,7 +210,7 @@ /** \brief Set the next receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RNPR = ( unsigned int ) address; @@ -222,7 +222,7 @@ /** \brief Set the next transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TNPR = ( unsigned int ) address; @@ -234,7 +234,7 @@ /** \brief Set the receive transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be received */ + char * address, /* \arg address to the next block to be received */ unsigned int bytes ) /* \arg number of bytes to be received */ { pPDC->PDC_RPR = ( unsigned int ) address; @@ -246,7 +246,7 @@ /** \brief Set the transmit transfer descriptor */ /**---------------------------------------------------------------------------- */ __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ - char * address, /* \arg address to the next bloc to be transmitted */ + char * address, /* \arg address to the next block to be transmitted */ unsigned int bytes ) /* \arg number of bytes to be transmitted */ { pPDC->PDC_TPR = ( unsigned int ) address; @@ -1054,7 +1054,7 @@ /**---------------------------------------------------------------------------- */ /** \fn AT91F_CKGR_CfgMainOscStartUpTime */ -/** \brief Cfg MOR Register according to the main osc startup time */ +/** \brief Cfg MORE Register according to the main osc startup time */ /**---------------------------------------------------------------------------- */ __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c index 0299ec0ee..f309128e5 100644 --- a/portable/MPLAB/PIC24_dsPIC/port.c +++ b/portable/MPLAB/PIC24_dsPIC/port.c @@ -45,7 +45,7 @@ #define portTIMER_PRESCALE 8 #define portINITIAL_SR 0 -/* Defined for backward compatability with project created prior to +/* Defined for backward compatibility with project created prior to FreeRTOS.org V4.3.0. */ #ifndef configKERNEL_INTERRUPT_PRIORITY #define configKERNEL_INTERRUPT_PRIORITY 1 diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c index c89232644..7ef38f399 100644 --- a/portable/RVDS/ARM_CA9/port.c +++ b/portable/RVDS/ARM_CA9/port.c @@ -476,7 +476,7 @@ uint32_t ulPortSetInterruptMask( void ) * this is not the case (if some bits represent a sub-priority). * * The priority grouping is configured by the GIC's binary point register - * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest * possible value (which may be above 0). */ configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE ); } diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h index 1faeffd27..005e00503 100644 --- a/portable/RVDS/ARM_CM4_MPU/portmacro.h +++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -97,7 +97,7 @@ typedef unsigned long UBaseType_t; #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c index 0e023088e..7837f8f73 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/port.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -204,7 +204,7 @@ void vPortEndTask( void ) /* * !!! Note !!! * This a trick!!! - * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware + * It's a copy from task.c. We need to know the definition of TCB for the purpose of hardware * stack check. Pls don't forget to update it when FreeRTOS is updated. */ typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ diff --git a/portable/ThirdParty/GCC/ARC_v1/port.c b/portable/ThirdParty/GCC/ARC_v1/port.c index 728cd6fac..39e8b771b 100644 --- a/portable/ThirdParty/GCC/ARC_v1/port.c +++ b/portable/ThirdParty/GCC/ARC_v1/port.c @@ -204,7 +204,7 @@ void vPortEndTask( void ) /* * !!! Note !!! * This a trick!!! - * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware + * It's a copy from task.c. We need to know the definition of TCB for the purpose of hardware * stack check. Pls don't forget to update it when FreeRTOS is updated. */ typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c index b11e9017f..1bec7afd8 100644 --- a/portable/ThirdParty/GCC/Posix/port.c +++ b/portable/ThirdParty/GCC/Posix/port.c @@ -242,7 +242,7 @@ BaseType_t xPortStartScheduler( void ) xSchedulerEnd = pdFALSE; /* Reset pthread_once_t, needed to restart the scheduler again. - * memset the internal struct members for MacOS/Linux Compatability */ + * memset the internal struct members for MacOS/Linux Compatibility */ #if __APPLE__ hSigSetupThread.__sig = _PTHREAD_ONCE_SIG_init; memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof(hSigSetupThread.__opaque)); diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h index d1e35d125..e117749fe 100644 --- a/portable/ThirdParty/GCC/Posix/portmacro.h +++ b/portable/ThirdParty/GCC/Posix/portmacro.h @@ -135,7 +135,7 @@ extern void vPortCancelThread( void * pxTaskToDelete ); * are always a full memory barrier. ISRs are emulated as signals * which also imply a full memory barrier. * - * Thus, only a compilier barrier is needed to prevent the compiler + * Thus, only a compiler barrier is needed to prevent the compiler * reordering. */ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h index bf91eda36..023250884 100644 --- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h +++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h @@ -83,7 +83,7 @@ typedef uint32_t UBaseType_t; #define portBYTE_ALIGNMENT 8 #define portDONT_DISCARD __attribute__( ( used ) ) -/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config, +/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rather than our config, * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */ #define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS #if portUSE_DIVIDER_SAVE_RESTORE diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h index fa942add3..b7e42aa94 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h @@ -114,7 +114,7 @@ * interrupts. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL -/* Stack alignment, architecture specifc. Must be a power of two. */ +/* Stack alignment, architecture specific. Must be a power of two. */ #define configSTACK_ALIGNMENT 16 diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h index a976bbd99..abeb955d0 100644 --- a/portable/WizC/PIC18/portmacro.h +++ b/portable/WizC/PIC18/portmacro.h @@ -154,7 +154,7 @@ extern uint8_t ucCriticalNesting; /* * The minimal stacksize is calculated on the first reference of * portMINIMAL_STACK_SIZE. Some input to this calculation is - * compiletime determined, other input is port-defined (see port.c) + * compile time determined, other input is port-defined (see port.c) */ extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void ); extern uint16_t usCalcMinStackSize; diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h index dac4dc864..b9cb0e697 100644 --- a/portable/oWatcom/16BitDOS/common/portasm.h +++ b/portable/oWatcom/16BitDOS/common/portasm.h @@ -63,7 +63,7 @@ debugger). The true stack pointer is then stored in the bp register. We add "les bx, dword ptr pxCurrentTCB" \ "mov ss, es:[ bx + 2 ]" \ "mov sp, es:[ bx ]" \ - "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ + "mov bp, sp" /* Prepare the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ "add bp, 0x0002" diff --git a/queue.c b/queue.c index fd62489f5..4759b439b 100644 --- a/queue.c +++ b/queue.c @@ -418,7 +418,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { - /* Queues can be allocated wither statically or dynamically, so + /* Queues can be allocated either statically or dynamically, so * note this queue was allocated statically in case the queue is * later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; From a081ba8b9c0e18b466a6e03ee0052d00f5f23304 Mon Sep 17 00:00:00 2001 From: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com> Date: Fri, 1 Nov 2024 10:56:18 -0700 Subject: [PATCH 2/4] Fix variable name mismatch, mpu_wrappers type mismatch. (#1181) Fix variable name mismatch introduced by #1166. Fix MPU v2 wrappers incorrectly using UBaseType_t instead of BaseType. --- include/mpu_prototypes.h | 4 ++-- portable/Common/mpu_wrappers.c | 4 ++-- portable/Common/mpu_wrappers_v2.c | 14 +++++++------- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h index ea2dd9f75..1efd13440 100644 --- a/include/mpu_prototypes.h +++ b/include/mpu_prototypes.h @@ -346,12 +346,12 @@ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; * with all the APIs. */ TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, - const UBaseType_t uxAutoReload, + const BaseType_t xAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, - const UBaseType_t uxAutoReload, + const BaseType_t xAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c index ab2a74bd2..4c5731665 100644 --- a/portable/Common/mpu_wrappers.c +++ b/portable/Common/mpu_wrappers.c @@ -1806,7 +1806,7 @@ portRAISE_PRIVILEGE(); portMEMORY_BARRIER(); - vTimerSetReloadMode( xTimer, uxAutoReload ); + vTimerSetReloadMode( xTimer, xAutoReload ); portMEMORY_BARRIER(); portRESET_PRIVILEGE(); @@ -1814,7 +1814,7 @@ } else { - vTimerSetReloadMode( xTimer, uxAutoReload ); + vTimerSetReloadMode( xTimer, xAutoReload ); } } #endif /* if ( configUSE_TIMERS == 1 ) */ diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c index c5bbdc318..eb9e6f056 100644 --- a/portable/Common/mpu_wrappers_v2.c +++ b/portable/Common/mpu_wrappers_v2.c @@ -3558,10 +3558,10 @@ #if ( configUSE_TIMERS == 1 ) void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer, - const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION; + const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION; void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer, - const UBaseType_t uxAutoReload ) /* PRIVILEGED_FUNCTION */ + const BaseType_t xAutoReload ) /* PRIVILEGED_FUNCTION */ { TimerHandle_t xInternalTimerHandle = NULL; int32_t lIndex; @@ -3579,7 +3579,7 @@ if( xInternalTimerHandle != NULL ) { - vTimerSetReloadMode( xInternalTimerHandle, uxAutoReload ); + vTimerSetReloadMode( xInternalTimerHandle, xAutoReload ); } } } @@ -3733,7 +3733,7 @@ TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, - const UBaseType_t uxAutoReload, + const BaseType_t xAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* PRIVILEGED_FUNCTION */ { @@ -3745,7 +3745,7 @@ if( lIndex != -1 ) { - xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, MPU_TimerCallback ); + xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback ); if( xInternalTimerHandle != NULL ) { @@ -3768,7 +3768,7 @@ TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, - const UBaseType_t uxAutoReload, + const BaseType_t xAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t * pxTimerBuffer ) /* PRIVILEGED_FUNCTION */ @@ -3781,7 +3781,7 @@ if( lIndex != -1 ) { - xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer ); + xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer ); if( xInternalTimerHandle != NULL ) { From 7d76dceaadd22bfdd6a77973f8c0b7b46cb326c5 Mon Sep 17 00:00:00 2001 From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Date: Sat, 2 Nov 2024 08:13:53 +0530 Subject: [PATCH 3/4] Add assert check for NULL TCB handle (#1177) Co-authored-by: ActoryOu --- tasks.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/tasks.c b/tasks.c index 6d86326c5..147b1aade 100644 --- a/tasks.c +++ b/tasks.c @@ -2203,6 +2203,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the calling task that is * being deleted. */ pxTCB = prvGetTCBFromHandle( xTaskToDelete ); + configASSERT( pxTCB != NULL ); /* Remove task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) @@ -2495,7 +2496,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, traceENTER_eTaskGetState( xTask ); - configASSERT( pxTCB ); + configASSERT( pxTCB != NULL ); #if ( configNUMBER_OF_CORES == 1 ) if( pxTCB == pxCurrentTCB ) @@ -2628,6 +2629,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the priority of the task * that called uxTaskPriorityGet() that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + uxReturn = pxTCB->uxPriority; } portBASE_TYPE_EXIT_CRITICAL(); @@ -2676,6 +2679,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the priority of the calling * task that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + uxReturn = pxTCB->uxPriority; } taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); @@ -2702,6 +2707,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the base priority of the task * that called uxTaskBasePriorityGet() that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + uxReturn = pxTCB->uxBasePriority; } portBASE_TYPE_EXIT_CRITICAL(); @@ -2750,6 +2757,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the base priority of the calling * task that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + uxReturn = pxTCB->uxBasePriority; } taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); @@ -2794,6 +2803,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the priority of the calling * task that is being changed. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); traceTASK_PRIORITY_SET( pxTCB, uxNewPriority ); @@ -2988,6 +2998,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, taskENTER_CRITICAL(); { pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); pxTCB->uxCoreAffinityMask = uxCoreAffinityMask; @@ -3043,6 +3054,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, portBASE_TYPE_ENTER_CRITICAL(); { pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + uxCoreAffinityMask = pxTCB->uxCoreAffinityMask; } portBASE_TYPE_EXIT_CRITICAL(); @@ -3066,6 +3079,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, taskENTER_CRITICAL(); { pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); pxTCB->xPreemptionDisable = pdTRUE; } @@ -3089,6 +3103,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, taskENTER_CRITICAL(); { pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); pxTCB->xPreemptionDisable = pdFALSE; @@ -3122,6 +3137,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, /* If null is passed in here then it is the running task that is * being suspended. */ pxTCB = prvGetTCBFromHandle( xTaskToSuspend ); + configASSERT( pxTCB != NULL ); traceTASK_SUSPEND( pxTCB ); @@ -4194,7 +4210,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /* If null is passed in here then the name of the calling task is being * queried. */ pxTCB = prvGetTCBFromHandle( xTaskToQuery ); - configASSERT( pxTCB ); + configASSERT( pxTCB != NULL ); traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) ); @@ -4357,6 +4373,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) configASSERT( ppxTaskBuffer != NULL ); pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 ) { @@ -4596,7 +4613,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) traceENTER_xTaskAbortDelay( xTask ); - configASSERT( pxTCB ); + configASSERT( pxTCB != NULL ); vTaskSuspendAll(); { @@ -4978,6 +4995,7 @@ BaseType_t xTaskIncrementTick( void ) /* If xTask is NULL then set the calling task's hook. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); /* Save the hook function in the TCB. A critical section is required as * the value can be accessed from an interrupt. */ @@ -5007,6 +5025,7 @@ BaseType_t xTaskIncrementTick( void ) /* If xTask is NULL then set the calling task's hook. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); /* Save the hook function in the TCB. A critical section is required as * the value can be accessed from an interrupt. */ @@ -5984,6 +6003,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) { pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + configASSERT( pxTCB != NULL ); + pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; } else @@ -6011,6 +6032,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) /* If null is passed in here then we are modifying the MPU settings of * the calling task. */ pxTCB = prvGetTCBFromHandle( xTaskToModify ); + configASSERT( pxTCB != NULL ); vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 ); @@ -6141,6 +6163,7 @@ static void prvCheckTasksWaitingTermination( void ) /* xTask is NULL then get the state of the calling task. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); pxTaskStatus->xHandle = pxTCB; pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] ); @@ -6357,6 +6380,7 @@ static void prvCheckTasksWaitingTermination( void ) * type. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); #if portSTACK_GROWTH < 0 { @@ -6389,6 +6413,7 @@ static void prvCheckTasksWaitingTermination( void ) traceENTER_uxTaskGetStackHighWaterMark( xTask ); pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); #if portSTACK_GROWTH < 0 { @@ -8288,6 +8313,7 @@ TickType_t uxTaskResetEventItemValue( void ) /* If null is passed in here then it is the calling task that is having * its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); taskENTER_CRITICAL(); { @@ -8327,6 +8353,7 @@ TickType_t uxTaskResetEventItemValue( void ) /* If null is passed in here then it is the calling task that is having * its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); taskENTER_CRITICAL(); { @@ -8354,6 +8381,7 @@ TickType_t uxTaskResetEventItemValue( void ) traceENTER_ulTaskGetRunTimeCounter( xTask ); pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter ); @@ -8381,6 +8409,8 @@ TickType_t uxTaskResetEventItemValue( void ) if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) { pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime; } else @@ -8584,6 +8614,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, traceENTER_xTaskGetMPUSettings( xTask ); pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) ); From 445336aad9a72dc4a3de6cf2e7ad212517f94558 Mon Sep 17 00:00:00 2001 From: ActoryOu Date: Mon, 4 Nov 2024 17:23:28 +0800 Subject: [PATCH 4/4] Follow GitHub recommendation to update release.yml (#1178) GitHub recommends to store user inputs in environments variables and then use them in scripts. This PR updates the code as per the GitHub recommendation. Details here - https://docs.github.com/en/actions/security-for-github-actions/security-guides/security-hardening-for-github-actions#understanding-the-risk-of-script-injections. --- .github/workflows/auto-release.yml | 46 +++++++++++++++++++++--------- tasks.c | 2 +- 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml index bad7a9bce..3477f6591 100644 --- a/.github/workflows/auto-release.yml +++ b/.github/workflows/auto-release.yml @@ -44,37 +44,49 @@ jobs: fetch-depth: 0 - name: Configure git identity + env: + ACTOR: ${{ github.actor }} run: | - git config --global user.name ${{ github.actor }} - git config --global user.email ${{ github.actor }}@users.noreply.github.com + git config --global user.name "$ACTOR" + git config --global user.email "$ACTOR"@users.noreply.github.com - name: create a new branch that references commit id + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + COMMIT_ID: ${{ github.event.inputs.commit_id }} working-directory: ./local_kernel run: | - git checkout -b ${{ github.event.inputs.version_number }} ${{ github.event.inputs.commit_id }} + git checkout -b "$VERSION_NUMBER" "$COMMIT_ID" echo "COMMIT_SHA_1=$(git rev-parse HEAD)" >> $GITHUB_ENV - name: Update source files with version info + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }} + COMMIT_SHA_1: ${{ env.COMMIT_SHA_1 }} + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | # Install deps and run pip install -r ./tools/.github/scripts/release-requirements.txt - ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_1 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }} + ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_1" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER" exit $? - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - name : Update version number in manifest.yml + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} working-directory: ./local_kernel run: | - ./.github/scripts/manifest_updater.py -v ${{ github.event.inputs.version_number }} + ./.github/scripts/manifest_updater.py -v "$VERSION_NUMBER" exit $? - name : Commit version number change in manifest.yml + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} working-directory: ./local_kernel run: | git add . git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml' - git push -u origin ${{ github.event.inputs.version_number }} + git push -u origin "$VERSION_NUMBER" - name: Generate SBOM uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main @@ -83,24 +95,32 @@ jobs: source_path: ./ - name: commit SBOM file + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} working-directory: ./local_kernel run: | git add . git commit -m '[AUTO][RELEASE]: Update SBOM' - git push -u origin ${{ github.event.inputs.version_number }} + git push -u origin "$VERSION_NUMBER" echo "COMMIT_SHA_2=$(git rev-parse HEAD)" >> $GITHUB_ENV - name: Release + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }} + COMMIT_SHA_2: ${{ env.COMMIT_SHA_2 }} + REPO_OWNER: ${{ github.repository_owner }} + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | # Install deps and run pip install -r ./tools/.github/scripts/release-requirements.txt - ./tools/.github/scripts/release.py ${{ github.repository_owner }} --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_2 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }} + ./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER" exit $? - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - name: Cleanup + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} working-directory: ./local_kernel run: | # Delete the branch created for Tag by SBOM generator - git push -u origin --delete ${{ github.event.inputs.version_number }} + git push -u origin --delete "$VERSION_NUMBER" diff --git a/tasks.c b/tasks.c index 147b1aade..421dea71d 100644 --- a/tasks.c +++ b/tasks.c @@ -3882,7 +3882,7 @@ void vTaskSuspendAll( void ) /* This must never be called from inside a critical section. */ configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 ); - /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that + /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that * do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER();