mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR.
This commit is contained in:
Richard Barry
parent
e0bab5981a
commit
0c7af1c2d3
|
|
@ -132,7 +132,8 @@ extern void vPortYieldFromISR( void );
|
|||
|
||||
/*
|
||||
* Set basepri back to 0 without effective other registers.
|
||||
* r0 is clobbered.
|
||||
* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
|
||||
*/
|
||||
#define portCLEAR_INTERRUPT_MASK() \
|
||||
__asm volatile \
|
||||
|
|
@ -142,6 +143,9 @@ extern void vPortYieldFromISR( void );
|
|||
:::"r0" \
|
||||
)
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a
|
||||
bug. Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before
|
||||
disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -173,7 +173,8 @@ typedef struct MPU_SETTINGS
|
|||
|
||||
/*
|
||||
* Set basepri back to 0 without effective other registers.
|
||||
* r0 is clobbered.
|
||||
* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
|
||||
*/
|
||||
#define portCLEAR_INTERRUPT_MASK() \
|
||||
__asm volatile \
|
||||
|
|
@ -183,6 +184,8 @@ typedef struct MPU_SETTINGS
|
|||
:::"r0" \
|
||||
)
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -132,7 +132,8 @@ extern void vPortYieldFromISR( void );
|
|||
|
||||
/*
|
||||
* Set basepri back to 0 without effective other registers.
|
||||
* r0 is clobbered.
|
||||
* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
|
||||
*/
|
||||
#define portCLEAR_INTERRUPT_MASK() \
|
||||
__asm volatile \
|
||||
|
|
@ -142,6 +143,9 @@ extern void vPortYieldFromISR( void );
|
|||
:::"r0" \
|
||||
)
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a
|
||||
bug. Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before
|
||||
disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -123,20 +123,18 @@ xPortPendSVHandler:
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
vPortSetInterruptMask:
|
||||
push { r0 }
|
||||
mov R0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
|
||||
msr BASEPRI, R0
|
||||
pop { R0 }
|
||||
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
|
||||
msr BASEPRI, r0
|
||||
|
||||
bx r14
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vPortClearInterruptMask:
|
||||
PUSH { r0 }
|
||||
MOV R0, #0
|
||||
MSR BASEPRI, R0
|
||||
POP { R0 }
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
mov r0, #0
|
||||
msr BASEPRI, r0
|
||||
|
||||
bx r14
|
||||
|
||||
|
|
|
|||
|
|
@ -127,6 +127,9 @@ extern void vPortClearInterruptMask( void );
|
|||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -136,6 +136,8 @@ vPortSetInterruptMask:
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
vPortClearInterruptMask:
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
mov r0, #0
|
||||
msr BASEPRI, r0
|
||||
|
||||
|
|
|
|||
|
|
@ -127,6 +127,9 @@ extern void vPortClearInterruptMask( void );
|
|||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -294,10 +294,8 @@ __asm void vPortSetInterruptMask( void )
|
|||
{
|
||||
PRESERVE8
|
||||
|
||||
push { r0 }
|
||||
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
|
||||
msr basepri, r0
|
||||
pop { r0 }
|
||||
bx r14
|
||||
}
|
||||
|
||||
|
|
@ -307,9 +305,9 @@ __asm void vPortClearInterruptMask( void )
|
|||
{
|
||||
PRESERVE8
|
||||
|
||||
push { r0 }
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
mov r0, #0
|
||||
msr basepri, r0
|
||||
pop { r0 }
|
||||
bx r14
|
||||
}
|
||||
|
|
|
|||
|
|
@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
|
|||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -369,6 +369,8 @@ __asm void vPortClearInterruptMask( void )
|
|||
{
|
||||
PRESERVE8
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
mov r0, #0
|
||||
msr basepri, r0
|
||||
bx r14
|
||||
|
|
|
|||
|
|
@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
|
|||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
|
||||
|
||||
|
|
|
|||
|
|
@ -126,10 +126,13 @@ extern void vPortYieldFromISR( void );
|
|||
|
||||
/*
|
||||
* Set basepri back to 0 without effective other registers.
|
||||
* r0 is clobbered.
|
||||
* r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
|
||||
*/
|
||||
#define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue