Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR.

FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h

@@ -132,7 +132,8 @@ extern void vPortYieldFromISR( void );
 	
 /*
  * Set basepri back to 0 without effective other registers.
- * r0 is clobbered.
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
  */
 #define portCLEAR_INTERRUPT_MASK()			\
 	__asm volatile							\
@@ -142,6 +143,9 @@ extern void vPortYieldFromISR( void );
 		:::"r0"								\
 	)
 
+/* FAQ:  Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a 
+bug.  Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before 
+disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;portSET_INTERRUPT_MASK()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	portCLEAR_INTERRUPT_MASK();(void)x
 

FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h

@@ -173,7 +173,8 @@ typedef struct MPU_SETTINGS
 
 /*
  * Set basepri back to 0 without effective other registers.
- * r0 is clobbered.
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
  */
 #define portCLEAR_INTERRUPT_MASK()			\
 	__asm volatile							\
@@ -183,6 +184,8 @@ typedef struct MPU_SETTINGS
 		:::"r0"								\
 	)
 
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;portSET_INTERRUPT_MASK()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	portCLEAR_INTERRUPT_MASK();(void)x
 

FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h

@@ -132,7 +132,8 @@ extern void vPortYieldFromISR( void );
 	
 /*
  * Set basepri back to 0 without effective other registers.
- * r0 is clobbered.
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
  */
 #define portCLEAR_INTERRUPT_MASK()			\
 	__asm volatile							\
@@ -142,6 +143,9 @@ extern void vPortYieldFromISR( void );
 		:::"r0"								\
 	)
 
+/* FAQ:  Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a 
+bug.  Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before 
+disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;portSET_INTERRUPT_MASK()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	portCLEAR_INTERRUPT_MASK();(void)x
 

FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s

@@ -123,20 +123,18 @@ xPortPendSVHandler:
 /*-----------------------------------------------------------*/
 
 vPortSetInterruptMask:
-	push { r0 }
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	mov R0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr BASEPRI, r0
-	msr BASEPRI, R0
-	pop { R0 }
 
 	bx r14
 	
 /*-----------------------------------------------------------*/
 
 vPortClearInterruptMask:
-	PUSH { r0 }
+	/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
-	MOV R0, #0
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
-	MSR BASEPRI, R0
+	mov r0, #0
-	POP	 { R0 }
+	msr BASEPRI, r0
 
 	bx r14
 

FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h

@@ -127,6 +127,9 @@ extern void vPortClearInterruptMask( void );
 #define portENABLE_INTERRUPTS()		vPortClearInterruptMask()
 #define portENTER_CRITICAL()					vPortEnterCritical()
 #define portEXIT_CRITICAL()						vPortExitCritical()
+
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;vPortSetInterruptMask()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask();(void)x
 

FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s

@@ -136,6 +136,8 @@ vPortSetInterruptMask:
 /*-----------------------------------------------------------*/
 
 vPortClearInterruptMask:
+	/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 	mov r0, #0
 	msr BASEPRI, r0
 

FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h

@@ -127,6 +127,9 @@ extern void vPortClearInterruptMask( void );
 #define portENABLE_INTERRUPTS()		vPortClearInterruptMask()
 #define portENTER_CRITICAL()					vPortEnterCritical()
 #define portEXIT_CRITICAL()						vPortExitCritical()
+
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;vPortSetInterruptMask()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask();(void)x
 

FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c

@@ -294,10 +294,8 @@ __asm void vPortSetInterruptMask( void )
 {
 	PRESERVE8
 
-	push { r0 }
 	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
 	msr basepri, r0
-	pop { r0 }
 	bx r14
 }
 
@@ -307,9 +305,9 @@ __asm void vPortClearInterruptMask( void )
 {
 	PRESERVE8
 
-	push { r0 }
+	/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 	mov r0, #0
 	msr basepri, r0
-	pop { r0 }
 	bx r14
 }

FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h

@@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
 #define portENABLE_INTERRUPTS()					vPortClearInterruptMask()
 #define portENTER_CRITICAL()					vPortEnterCritical()
 #define portEXIT_CRITICAL()						vPortExitCritical()
+
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;vPortSetInterruptMask()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask();(void)x
 

FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c

@@ -369,6 +369,8 @@ __asm void vPortClearInterruptMask( void )
 {
 	PRESERVE8
 
+	/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 	mov r0, #0
 	msr basepri, r0
 	bx r14

FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h

@@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
 #define portENABLE_INTERRUPTS()					vPortClearInterruptMask()
 #define portENTER_CRITICAL()					vPortEnterCritical()
 #define portEXIT_CRITICAL()						vPortExitCritical()
+
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;vPortSetInterruptMask()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask();(void)x
 

FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h

@@ -126,10 +126,13 @@ extern void vPortYieldFromISR( void );
 	
 /*
  * Set basepri back to 0 without effective other registers.
- * r0 is clobbered.
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
  */
 #define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )
 
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see 
+http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
 #define portSET_INTERRUPT_MASK_FROM_ISR()		0;portSET_INTERRUPT_MASK()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	portCLEAR_INTERRUPT_MASK();(void)x