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Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR.

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This commit is contained in:
Richard Barry 2012-08-14 13:04:22 +00:00
parent e0bab5981a
commit 0c7af1c2d3
12 changed files with 42 additions and 16 deletions
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6
FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
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@ -294,10 +294,8 @@ __asm void vPortSetInterruptMask( void )
{
PRESERVE8
push { r0 }
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
pop { r0 }
bx r14
}
@ -307,9 +305,9 @@ __asm void vPortClearInterruptMask( void )
{
PRESERVE8
push { r0 }
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
mov r0, #0
msr basepri, r0
pop { r0 }
bx r14
}

3
FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
View file

@ -127,6 +127,9 @@ extern void vPortExitCritical( void );
#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x