mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Continue development of MSP430X port.
This commit is contained in:
parent
e7e623f853
commit
0a31276719
|
@ -98,8 +98,8 @@ void vPortSetupTimerInterrupt( void );
|
|||
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
|
||||
{
|
||||
unsigned short usNibble;
|
||||
unsigned short *pus16BitPointer;
|
||||
unsigned long ulSP_PC_Combined;
|
||||
unsigned short *pusTopOfStack;
|
||||
|
||||
/*
|
||||
Place a few bytes of known values on the bottom of the stack.
|
||||
|
@ -117,17 +117,11 @@ unsigned long ulSP_PC_Combined;
|
|||
executing an ISR. We want the stack to look just as if this has happened
|
||||
so place a pointer to the start of the task on the stack first - followed
|
||||
by the flags we want the task to use when it starts up. */
|
||||
// pus16BitPointer = ( unsigned short * ) pxTopOfStack;
|
||||
// *pus16BitPointer = ( unsigned short ) pxCode;
|
||||
// pus16BitPointer--;
|
||||
|
||||
/* When placed on the stack, the top four bits of the status register
|
||||
contain bits 19:16 of the 20 bit return address (pxCode). */
|
||||
#ifdef GENERATE_ISR_STACK_FRAME
|
||||
usNibble = ( unsigned short ) ( ( ( unsigned long ) pxCode >> 15UL ) & 0x0fUL );
|
||||
// *pus16BitPointer = ( usNibble | portFLAGS_INT_ENABLED );
|
||||
// pus16BitPointer--;
|
||||
|
||||
// pxTopOfStack = ( portSTACK_TYPE * ) pus16BitPointer;
|
||||
|
||||
ulSP_PC_Combined = ( unsigned long ) pxCode;
|
||||
ulSP_PC_Combined <<= 16;
|
||||
|
@ -135,7 +129,14 @@ unsigned long ulSP_PC_Combined;
|
|||
ulSP_PC_Combined |= portFLAGS_INT_ENABLED;
|
||||
*pxTopOfStack = ulSP_PC_Combined;
|
||||
pxTopOfStack--;
|
||||
|
||||
#else
|
||||
*pxTopOfStack = ( portSTACK_TYPE ) pxCode;
|
||||
pusTopOfStack = ( unsigned short * ) pxTopOfStack;
|
||||
pusTopOfStack--;
|
||||
*pusTopOfStack = portFLAGS_INT_ENABLED;
|
||||
pusTopOfStack -= 2;
|
||||
pxTopOfStack = ( portSTACK_TYPE * ) pusTopOfStack;
|
||||
#endif
|
||||
/* Next the general purpose registers. */
|
||||
*pxTopOfStack = ( portSTACK_TYPE ) 0xffffff;
|
||||
pxTopOfStack--;
|
||||
|
@ -193,5 +194,12 @@ void vPortSetupTimerInterrupt( void )
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#pragma vector=configTICK_INTERRUPT_VECTOR
|
||||
__interrupt void vISR( void )
|
||||
{
|
||||
extern void vTickISR( void );
|
||||
|
||||
vTickISR();
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -79,9 +79,10 @@ portRESTORE_CONTEXT macro
|
|||
/* The last thing on the stack will be the status register.
|
||||
Ensure the power down bits are clear ready for the next
|
||||
time this power down register is popped from the stack. */
|
||||
bic.w #0xf0, 0( SP )
|
||||
bic.w #0xf0, 0( sp )
|
||||
|
||||
reti
|
||||
pop.w sr
|
||||
reta
|
||||
endm
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -62,7 +62,6 @@
|
|||
EXPORT vPortYield
|
||||
EXPORT xPortStartScheduler
|
||||
|
||||
RSEG CODE
|
||||
|
||||
/*
|
||||
* The RTOS tick ISR.
|
||||
|
@ -72,7 +71,9 @@
|
|||
*
|
||||
* If the preemptive scheduler is in use a context switch can also occur.
|
||||
*/
|
||||
RSEG ISR_CODE
|
||||
vTickISR:
|
||||
push.w sr
|
||||
portSAVE_CONTEXT
|
||||
|
||||
calla #vTaskIncrementTick
|
||||
|
@ -84,6 +85,7 @@ vTickISR:
|
|||
portRESTORE_CONTEXT
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
RSEG CODE
|
||||
|
||||
/*
|
||||
* Manual context switch called by the portYIELD() macro.
|
||||
|
@ -92,13 +94,13 @@ vPortYield:
|
|||
|
||||
/* Mimic an interrupt by combining the SR and the PC, the latter having
|
||||
already been pushed onto the stack. R14 is a scratch registers. */
|
||||
popx.a r14 /* r14 will hold the 20 bit PC. */
|
||||
push.w r14 /* Push just 16 bits of the 20bit PC back onto the stack. */
|
||||
rram.a #4, r14 /* Move the top 4 bits of the PC down ready to be combined with the SP. */
|
||||
and.w #0xf000, r14/* Ensure other bits are clear. */
|
||||
add.w sr, r14 /* Combine the top 4 bits of the PC with the SR. */
|
||||
push.w r14 /* Push the generated combined value onto the stack. */
|
||||
|
||||
// popx.a r14 /* r14 will hold the 20 bit PC. */
|
||||
// push.w r14 /* Push just 16 bits of the 20bit PC back onto the stack. */
|
||||
// rram.a #4, r14 /* Move the top 4 bits of the PC down ready to be combined with the SP. */
|
||||
// and.w #0xf000, r14/* Ensure other bits are clear. */
|
||||
// add.w sr, r14 /* Combine the top 4 bits of the PC with the SR. */
|
||||
// push.w r14 /* Push the generated combined value onto the stack. */
|
||||
push.w sr
|
||||
/* Now the SR is stacked we can disable interrupts. */
|
||||
dint
|
||||
nop
|
||||
|
@ -129,11 +131,13 @@ xPortStartScheduler:
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Install vTickISR as the timer A0 interrupt. */
|
||||
ASEG
|
||||
ORG 0xFFE0 + configTICK_INTERRUPT_VECTOR
|
||||
/* Install vTickISR as the interrupt on the vector specified by the
|
||||
application code. */
|
||||
/*COMMON INTVEC *./
|
||||
/*ORG 0xFF80 + configTICK_INTERRUPT_VECTOR
|
||||
ORG 0xFFEC
|
||||
|
||||
_vTickISR_: DC16 vTickISR
|
||||
__vTickISR__: DC16 0xabcd*/
|
||||
|
||||
|
||||
END
|
||||
|
|
Loading…
Reference in a new issue