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Renamed RISC-V_RV32_SiFive_HiFive1_IAR directory to RISC-V_RV32_SiFive_HiFive1-RevB_IAR as it targets the RevB hardware.

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This commit is contained in:
Richard Barry 2020-01-01 22:38:23 +00:00
parent 62b413627a
commit 0a29d350b1
35 changed files with 0 additions and 8090 deletions
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21
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/settings/RTOSDemo.Debug.driver.xcl Normal file
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"--core=RV32IMAC"
"-p"
"C:\devtools\IAR Systems\Embedded Workbench 8.3\riscv\config\debugger\SiFive\hifive1.ddf"
"--drv_verify_download"
"--jet_standard_reset=2,300,1500"
"--reset_style=\"0,-,0,Disabled__no_reset_\""
"--reset_style=\"1,-,0,Software\""
"--reset_style=\"2,-,1,Hardware\""
"--jet_emu_param=cJtagOpt=Fmt:OScan1"