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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Fix type misstake
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parent
2d12f54705
commit
09b63a9353
3 changed files with 13 additions and 12 deletions
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@ -166,9 +166,9 @@ task stack, not the ISR stack). */
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#if( __riscv_xlen == 64 )
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void vPortSetupTimerInterrupt( void )
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{
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volatile uint32_t * const pulTime = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
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volatile uint64_t * const pulTime = ( volatile uint64_t * const ) ( configMTIME_BASE_ADDRESS );
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volatile uint32_t ulHartId;
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volatile uint64_t ulHartId;
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__asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) );
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@ -189,7 +189,7 @@ task stack, not the ISR stack). */
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BaseType_t xPortStartScheduler( void )
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{
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extern void xPortStartFirstTask( void );
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extern void vPortStartFirstTask( void );
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#if( configASSERT_DEFINED == 1 )
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{
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@ -218,10 +218,10 @@ extern void xPortStartFirstTask( void );
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configure whichever clock is to be used to generate the tick interrupt. */
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vPortSetupTimerInterrupt();
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/* Enabling mtime and external interrupts will be made into xPortStartFirstTask function */
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xPortStartFirstTask();
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/* Enabling mtime and external interrupts will be made into vPortStartFirstTask function */
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vPortStartFirstTask();
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/* Should not get here as after calling xPortStartFirstTask() only tasks
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/* Should not get here as after calling vPortStartFirstTask() only tasks
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should be executing. */
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return pdFAIL;
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}
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@ -244,7 +244,7 @@ void vPortEndScheduler( void )
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"and t0, t0, t1 \n"
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"beqz t0, 1f \n" /* check if Q,F or D is present into misa */
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"csrr t0, mstatus \n" /* Floating point unit is present so need to put it into initial state */
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"lui t1, 0x2 \n" /* t1 = 0x1 << 12 */
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"lui t1, 0x2 \n" /* t1 = 0x2 << 11 --> 0x1 << 12 */
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"or t0, t0, t1 \n"
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"csrw mstatus, t0 \n" /* Set FS to initial state */
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"csrwi fcsr, 0 \n" /* Clear Floating-point Control and Status Register */
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@ -166,14 +166,13 @@ definitions. */
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#define portasmADDITIONAL_CONTEXT_WORDSIZE ((portasmADDITIONAL_CONTEXT_SIZE) * (portWORD_SIZE))
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#define portasmFPU_CONTEXT_WORDSIZE ((portasmFPU_CONTEXT_SIZE) * (portFPUWORD_SIZE))
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.global xPortStartFirstTask
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.global vPortStartFirstTask
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.global freertos_risc_v_trap_handler
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.global pxPortInitialiseStack
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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.extern xTaskIncrementTick
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.extern Timer_IRQHandler
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.extern pullMachineTimerCompareRegister
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.extern pullNextTime
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.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
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@ -441,7 +440,7 @@ handle_exception:
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is_exception:
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/* restore t0 and save sp in mscratch. */
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csrr t0, mscratch
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csrw mscratch, sp
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csrw mscratch, sp
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/* Switch to ISR stack before function call. */
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load_x sp, xISRStackTop
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portSAVE_BaseReg
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@ -462,6 +461,8 @@ is_exception:
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mret
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ecall_yield:
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/* restore t0 */
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csrr t0, mscratch
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portSAVE_BaseReg
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/* a4 = mepc
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* a5 = mstatus
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@ -600,7 +601,7 @@ end_trap_handler:
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.align 8
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.func
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xPortStartFirstTask:
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vPortStartFirstTask:
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#if( portasmHAS_SIFIVE_CLINT != 0 )
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/* If there is a clint then interrupts can branch directly to the FreeRTOS
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@ -48,7 +48,7 @@ extern "C" {
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#define portSTACK_TYPE uint64_t
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#define portBASE_TYPE int64_t
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#define portUBASE_TYPE uint64_t
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#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
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#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL
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#define portPOINTER_SIZE_TYPE uint64_t
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#elif __riscv_xlen == 32
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#define portSTACK_TYPE uint32_t
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