Fix type misstake

This commit is contained in:
Emmanuel Puerto 2020-09-22 22:14:56 +02:00
parent 2d12f54705
commit 09b63a9353
3 changed files with 13 additions and 12 deletions

View file

@ -166,9 +166,9 @@ task stack, not the ISR stack). */
#if( __riscv_xlen == 64 )
void vPortSetupTimerInterrupt( void )
{
volatile uint32_t * const pulTime = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
volatile uint64_t * const pulTime = ( volatile uint64_t * const ) ( configMTIME_BASE_ADDRESS );
volatile uint32_t ulHartId;
volatile uint64_t ulHartId;
__asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) );
@ -189,7 +189,7 @@ task stack, not the ISR stack). */
BaseType_t xPortStartScheduler( void )
{
extern void xPortStartFirstTask( void );
extern void vPortStartFirstTask( void );
#if( configASSERT_DEFINED == 1 )
{
@ -218,10 +218,10 @@ extern void xPortStartFirstTask( void );
configure whichever clock is to be used to generate the tick interrupt. */
vPortSetupTimerInterrupt();
/* Enabling mtime and external interrupts will be made into xPortStartFirstTask function */
xPortStartFirstTask();
/* Enabling mtime and external interrupts will be made into vPortStartFirstTask function */
vPortStartFirstTask();
/* Should not get here as after calling xPortStartFirstTask() only tasks
/* Should not get here as after calling vPortStartFirstTask() only tasks
should be executing. */
return pdFAIL;
}
@ -244,7 +244,7 @@ void vPortEndScheduler( void )
"and t0, t0, t1 \n"
"beqz t0, 1f \n" /* check if Q,F or D is present into misa */
"csrr t0, mstatus \n" /* Floating point unit is present so need to put it into initial state */
"lui t1, 0x2 \n" /* t1 = 0x1 << 12 */
"lui t1, 0x2 \n" /* t1 = 0x2 << 11 --> 0x1 << 12 */
"or t0, t0, t1 \n"
"csrw mstatus, t0 \n" /* Set FS to initial state */
"csrwi fcsr, 0 \n" /* Clear Floating-point Control and Status Register */

View file

@ -166,14 +166,13 @@ definitions. */
#define portasmADDITIONAL_CONTEXT_WORDSIZE ((portasmADDITIONAL_CONTEXT_SIZE) * (portWORD_SIZE))
#define portasmFPU_CONTEXT_WORDSIZE ((portasmFPU_CONTEXT_SIZE) * (portFPUWORD_SIZE))
.global xPortStartFirstTask
.global vPortStartFirstTask
.global freertos_risc_v_trap_handler
.global pxPortInitialiseStack
.extern pxCurrentTCB
.extern ulPortTrapHandler
.extern vTaskSwitchContext
.extern xTaskIncrementTick
.extern Timer_IRQHandler
.extern pullMachineTimerCompareRegister
.extern pullNextTime
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
@ -441,7 +440,7 @@ handle_exception:
is_exception:
/* restore t0 and save sp in mscratch. */
csrr t0, mscratch
csrw mscratch, sp
csrw mscratch, sp
/* Switch to ISR stack before function call. */
load_x sp, xISRStackTop
portSAVE_BaseReg
@ -462,6 +461,8 @@ is_exception:
mret
ecall_yield:
/* restore t0 */
csrr t0, mscratch
portSAVE_BaseReg
/* a4 = mepc
* a5 = mstatus
@ -600,7 +601,7 @@ end_trap_handler:
.align 8
.func
xPortStartFirstTask:
vPortStartFirstTask:
#if( portasmHAS_SIFIVE_CLINT != 0 )
/* If there is a clint then interrupts can branch directly to the FreeRTOS

View file

@ -48,7 +48,7 @@ extern "C" {
#define portSTACK_TYPE uint64_t
#define portBASE_TYPE int64_t
#define portUBASE_TYPE uint64_t
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL
#define portPOINTER_SIZE_TYPE uint64_t
#elif __riscv_xlen == 32
#define portSTACK_TYPE uint32_t