mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-02 12:24:07 -04:00
Add two Cortex-M4F demo applications.
This commit is contained in:
Richard Barry
parent
e7a1222c5f
commit
08ddd1d00d
102 changed files with 43902 additions and 0 deletions
2295
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/LPC43xx.h
Normal file
2295
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/LPC43xx.h
Normal file
File diff suppressed because it is too large
Load diff
59
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/config.h
Normal file
59
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/config.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*****************************************************************************
|
||||
* config.h: Header file for NXP LPC43xx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2011.6.22 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
|
||||
#define IRC_TRIM_VAL 0x34A /* IRC trim value for 12MHz output */
|
||||
#define XTAL_FREQ (12000000UL) /* Frequency of external xtal */
|
||||
#define EXT_FREQ (12000000UL) /* Frequency of external clock on EXT_TCK, ENET_RX_CLK or ENET_TX_CLK */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Retarget selection
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
typedef enum {
|
||||
RETARGET_USART0 = 0,
|
||||
RETARGET_UART1 = 1,
|
||||
RETARGET_USART2 = 2,
|
||||
RETARGET_USART3 = 3
|
||||
} RETARGET_Type;
|
||||
|
||||
#define RETARGET_UART_BUFSIZE 0x40
|
||||
extern volatile uint32_t UART0Count;
|
||||
extern volatile uint8_t UART0Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern volatile uint32_t UART1Count;
|
||||
extern volatile uint8_t UART1Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern volatile uint32_t UART2Count;
|
||||
extern volatile uint8_t UART2Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern volatile uint32_t UART3Count;
|
||||
extern volatile uint8_t UART3Buffer[RETARGET_UART_BUFSIZE];
|
||||
extern void RetargetInit(RETARGET_Type retarget, uint32_t baudrate);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Board selection
|
||||
*----------------------------------------------------------------------------*/
|
||||
//NXP LPC4300 validation board
|
||||
//#define NXP_VALIDATION_BOARD
|
||||
|
||||
//Hitex LPC4350 evaluation board
|
||||
//#define USE_HITEX_LPC4350_EVAL
|
||||
|
||||
#endif /* end __CONFIG_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
53
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cm4.c
Normal file
53
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cm4.c
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm4.c
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
1268
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cm4.h
Normal file
1268
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cm4.h
Normal file
File diff suppressed because it is too large
Load diff
844
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cmFunc.h
Normal file
844
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cmFunc.h
Normal file
|
|
@ -0,0 +1,844 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H__
|
||||
#define __CORE_CMFUNC_H__
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_CONTROL(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_CONTROL(uint32_t control);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_IPSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_APSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_xPSR(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_PSP(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_PSP(uint32_t topOfProcStack);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_MSP(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_MSP(uint32_t topOfMainStack);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_PRIMASK(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_PRIMASK(uint32_t priMask);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_BASEPRI(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_BASEPRI(uint32_t basePri);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern uint32_t __get_FAULTMASK(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __set_FAULTMASK(uint32_t faultMask);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & 1);
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#if defined (__ICCARM__)
|
||||
#include <intrinsics.h> /* IAR Intrinsics */
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_irq __enable_interrupt
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_irq __disable_interrupt
|
||||
|
||||
|
||||
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
static uint32_t __get_IPSR(void)
|
||||
{
|
||||
__ASM("mrs r0, ipsr");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
static uint32_t __get_APSR(void)
|
||||
{
|
||||
__ASM("mrs r0, apsr");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
static uint32_t __get_xPSR(void)
|
||||
{
|
||||
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
static uint32_t __get_PSP(void)
|
||||
{
|
||||
__ASM("mrs r0, psp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
static void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM("msr psp, r0");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
static uint32_t __get_MSP(void)
|
||||
{
|
||||
__ASM("mrs r0, msp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
static void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM("msr msp, r0");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
static __INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
static __INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
|
||||
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
|
||||
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM("vmrs r0, fpscr");
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM("vmsr fpscr, r0");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H__ */
|
||||
775
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cmInstr.h
Normal file
775
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/core_cmInstr.h
Normal file
|
|
@ -0,0 +1,775 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V2.01
|
||||
* @date 06. December 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H__
|
||||
#define __CORE_CMINSTR_H__
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
extern uint32_t __REV16(uint32_t value);
|
||||
#else /* (__ARMCC_VERSION >= 400677) */
|
||||
static __INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
extern int32_t __REVSH(int32_t value);
|
||||
#else /* (__ARMCC_VERSION >= 400677) */
|
||||
static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
extern void __CLREX(void);
|
||||
#else /* (__ARMCC_VERSION >= 400000) */
|
||||
#define __CLREX __clrex
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <intrinsics.h> /* IAR Intrinsics */
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __no_operation
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
static __INLINE void __WFI(void)
|
||||
{
|
||||
__ASM ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
static __INLINE void __WFE(void)
|
||||
{
|
||||
__ASM ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
static __INLINE void __SEV(void)
|
||||
{
|
||||
__ASM ("sev");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic void __ISB(void) (see intrinsics.h) */
|
||||
/* intrinsic void __DSB(void) (see intrinsics.h) */
|
||||
/* intrinsic void __DMB(void) (see intrinsics.h) */
|
||||
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
|
||||
/* intrinsic __SSAT (see intrinsics.h) */
|
||||
/* intrinsic __USAT (see intrinsics.h) */
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
__ASM("rev16 r0, r0");
|
||||
}
|
||||
|
||||
|
||||
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
__ASM("rbit r0, r0");
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
static uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("ldrexb r0, [r0]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
static uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("ldrexh r0, [r0]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
|
||||
static uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("ldrex r0, [r0]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("strexb r0, r0, [r1]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("strexh r0, r0, [r1]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
|
||||
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("strex r0, r0, [r1]");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
static __INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM ("clrex");
|
||||
}
|
||||
|
||||
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H__ */
|
||||
46
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/dma.h
Normal file
46
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/dma.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/***********************************************************************
|
||||
* $Id: dma.h 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Validation
|
||||
*
|
||||
* Description: DMA Test
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
#ifndef __DMA_H
|
||||
#define __DMA_H
|
||||
|
||||
#define DMA_SIZE 0x1000
|
||||
|
||||
#define M2M 0x00
|
||||
#define M2P 0x01
|
||||
#define P2M 0x02
|
||||
#define P2P 0x03
|
||||
|
||||
extern void DMA_IRQHandler (void);
|
||||
extern uint32_t DMA_Init_Matrix( uint32_t u32SrcAddr );
|
||||
|
||||
typedef struct _LinkedList {
|
||||
DWORD SRC;
|
||||
DWORD DST;
|
||||
DWORD LLI;
|
||||
DWORD CTRL;
|
||||
}LinkedList;
|
||||
|
||||
#endif /* end __DMA_H */
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
****************************************************************************/
|
||||
421
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/emc_LPC43xx.c
Normal file
421
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/emc_LPC43xx.c
Normal file
|
|
@ -0,0 +1,421 @@
|
|||
/***********************************************************************
|
||||
* $Id: emc_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC43xx.c
|
||||
*
|
||||
* Project: NXP LPC43xx Common
|
||||
*
|
||||
* Description: Initialisation of the external memory interface and
|
||||
* configuration for the specific memories connected to
|
||||
* the LPC43xx
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#include "LPC43xx.h"
|
||||
#include "system_LPC43xx.h"
|
||||
#include "scu.h"
|
||||
#include "config.h"
|
||||
#include "platform_config.h"
|
||||
|
||||
#include "emc_LPC43xx.h"
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
** Function prototypes
|
||||
**********************************************************************/
|
||||
#define DELAY_1usFreq (1000000) // 1MHz equivalent to 1usec
|
||||
static uint32_t delayBase1us; // calculated depending on M4/EMI frequency
|
||||
static void vDelay(uint32_t u32Delay); // delay function
|
||||
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Call the required memory setup functions from here
|
||||
*
|
||||
*
|
||||
****************************************************************************************/
|
||||
void EMC_Init( void )
|
||||
{
|
||||
// The address/data pins for the memory interface are required for the static and for
|
||||
// dynamic memories
|
||||
EMC_Config_Pinmux();
|
||||
|
||||
// Initialise the control signals for static memories
|
||||
#if (USE_EXT_STATIC_MEM == YES)
|
||||
|
||||
// Initialise the control signals for static memories
|
||||
EMC_Config_Static();
|
||||
|
||||
// #if (USE_EXT_DYNAMIC_MEM == NO)
|
||||
// LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
|
||||
// LPC_EMC->CONFIG = 0;
|
||||
// // Buffers for the static memories are enabled as well. If there is SDRAM as well,
|
||||
// // then this is done after the initialisation for the dynamic memory interface.
|
||||
// LPC_EMC->STATICCONFIG0 = 0x00080081;
|
||||
// #endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (USE_EXT_DYNAMIC_MEM == YES)
|
||||
|
||||
// The setup for dynamic memories (SDRAM)
|
||||
EMC_Init_SRDRAM(SDRAM_BASE, PART_WIDTH, PART_SIZE, EXT_WIDTH, COL_ADDR_BITS);
|
||||
|
||||
#elif (USE_EXT_DYNAMIC_MEM == NO)
|
||||
|
||||
LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
|
||||
LPC_EMC->CONFIG = 0;
|
||||
|
||||
#endif
|
||||
|
||||
// Buffers for the static memories can now be enabled as well. In a system with static and dynamic memory
|
||||
// this should only been done after the SDRAM initialisation --> here
|
||||
LPC_EMC->STATICCONFIG0 = 0x00080081;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Set up the address/data pins for external memory interface in LP43xx
|
||||
*
|
||||
* Modify this function in case not all of the address/data pins are needed.
|
||||
****************************************************************************************/
|
||||
void EMC_Config_Pinmux(void)
|
||||
{
|
||||
|
||||
// Disable the external memory controller before changing pin control configuration
|
||||
LPC_EMC->CONTROL = 0x00000000;
|
||||
|
||||
// EMC_OUT (PUP_CLEAR | SLEWRATE_FAST | FILTER_DISABLE)
|
||||
// EMC_IO (PUP_CLEAR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
// Data line configuration
|
||||
scu_pinmux(0x1, 7, EMC_IO, FUNC3); // P1_7: D0
|
||||
scu_pinmux(0x1, 8, EMC_IO, FUNC3); // P1_8: D1
|
||||
scu_pinmux(0x1, 9, EMC_IO, FUNC3); // P1_9: D2
|
||||
scu_pinmux(0x1, 10, EMC_IO, FUNC3); // P1_10: D3
|
||||
scu_pinmux(0x1, 11, EMC_IO, FUNC3); // P1_11: D4
|
||||
scu_pinmux(0x1, 12, EMC_IO, FUNC3); // P1_12: D5
|
||||
scu_pinmux(0x1, 13, EMC_IO, FUNC3); // P1_13: D6
|
||||
scu_pinmux(0x1, 14, EMC_IO, FUNC3); // P1_14: D7
|
||||
scu_pinmux(0x5, 4, EMC_IO, FUNC2); // P5_4: D8
|
||||
scu_pinmux(0x5, 5, EMC_IO, FUNC2); // P5_5: D9
|
||||
scu_pinmux(0x5, 6, EMC_IO, FUNC2); // P5_6: D10
|
||||
scu_pinmux(0x5, 7, EMC_IO, FUNC2); // P5_7: D11
|
||||
scu_pinmux(0x5, 0, EMC_IO, FUNC2); // P5_0: D12
|
||||
scu_pinmux(0x5, 1, EMC_IO, FUNC2); // P5_1: D13
|
||||
scu_pinmux(0x5, 2, EMC_IO, FUNC2); // P5_2: D14
|
||||
scu_pinmux(0x5, 3, EMC_IO, FUNC2); // P5_3: D15
|
||||
scu_pinmux(0xD, 2, EMC_IO, FUNC2); // PD_2: D16
|
||||
scu_pinmux(0xD, 3, EMC_IO, FUNC2); // PD_3: D17
|
||||
scu_pinmux(0xD, 4, EMC_IO, FUNC2); // PD_4: D18
|
||||
scu_pinmux(0xD, 5, EMC_IO, FUNC2); // PD_5: D19
|
||||
scu_pinmux(0xD, 6, EMC_IO, FUNC2); // PD_6: D20
|
||||
scu_pinmux(0xD, 7, EMC_IO, FUNC2); // PD_7: D21
|
||||
scu_pinmux(0xD, 8, EMC_IO, FUNC2); // PD_8: D22
|
||||
scu_pinmux(0xD, 9, EMC_IO, FUNC2); // PD_9: D23
|
||||
scu_pinmux(0xE, 5, EMC_IO, FUNC3); // PE_5: D24
|
||||
scu_pinmux(0xE, 6, EMC_IO, FUNC3); // PE_6: D25
|
||||
scu_pinmux(0xE, 7, EMC_IO, FUNC3); // PE_7: D26
|
||||
scu_pinmux(0xE, 8, EMC_IO, FUNC3); // PE_8: D27
|
||||
scu_pinmux(0xE, 9, EMC_IO, FUNC3); // PE_9: D28
|
||||
scu_pinmux(0xE, 10, EMC_IO, FUNC3); // PE_10: D29
|
||||
scu_pinmux(0xE, 11, EMC_IO, FUNC3); // PE_11: D30
|
||||
scu_pinmux(0xE, 12, EMC_IO, FUNC3); // PE_12: D31
|
||||
|
||||
// Address line configuration
|
||||
scu_pinmux(0x2, 9, EMC_IO, FUNC3); // P2_9: A0
|
||||
scu_pinmux(0x2, 10, EMC_IO, FUNC3); // P2_10: A1
|
||||
scu_pinmux(0x2, 11, EMC_IO, FUNC3); // P2_11: A2
|
||||
scu_pinmux(0x2, 12, EMC_IO, FUNC3); // P2_12: A3
|
||||
scu_pinmux(0x2, 13, EMC_IO, FUNC3); // P2_13: A4
|
||||
scu_pinmux(0x1, 0, EMC_IO, FUNC2); // P1_0: A5
|
||||
scu_pinmux(0x1, 1, EMC_IO, FUNC2); // P1_1: A6
|
||||
scu_pinmux(0x1, 2, EMC_IO, FUNC2); // P1_2: A7
|
||||
scu_pinmux(0x2, 8, EMC_IO, FUNC3); // P2_8: A8
|
||||
scu_pinmux(0x2, 7, EMC_IO, FUNC3); // P2_7: A9
|
||||
scu_pinmux(0x2, 6, EMC_IO, FUNC2); // P2_6: A10
|
||||
scu_pinmux(0x2, 2, EMC_IO, FUNC2); // P2_2: A11
|
||||
scu_pinmux(0x2, 1, EMC_IO, FUNC2); // P2_0: A12
|
||||
scu_pinmux(0x2, 0, EMC_IO, FUNC2); // P2_0: A13
|
||||
scu_pinmux(0x6, 8, EMC_IO, FUNC1); // P6_8: A14
|
||||
scu_pinmux(0x6, 7, EMC_IO, FUNC1); // P6_7: A15
|
||||
scu_pinmux(0xD, 16, EMC_IO, FUNC2); // PD_16: A16
|
||||
scu_pinmux(0xD, 15, EMC_IO, FUNC2); // PD_15: A17
|
||||
scu_pinmux(0xE, 0, EMC_IO, FUNC3); // PE_0: A18
|
||||
scu_pinmux(0xE, 1, EMC_IO, FUNC3); // PE_1: A19
|
||||
scu_pinmux(0xE, 2, EMC_IO, FUNC3); // PE_2: A20
|
||||
scu_pinmux(0xE, 3, EMC_IO, FUNC3); // PE_3: A21
|
||||
scu_pinmux(0xE, 4, EMC_IO, FUNC3); // PE_4: A22
|
||||
|
||||
// Control signals for static memory
|
||||
scu_pinmux(0x1, 6, EMC_IO, FUNC3); // P1_6: WE
|
||||
scu_pinmux(0x1, 5, EMC_IO, FUNC3); // P1_5: CS0
|
||||
scu_pinmux(0x1, 3, EMC_IO, FUNC3); // P1_6: OE
|
||||
scu_pinmux(0x1, 4, EMC_IO, FUNC3); // P1_5: BLS0
|
||||
scu_pinmux(0x6, 6, EMC_IO, FUNC1); // P1_6: BLS1
|
||||
scu_pinmux(0xD, 12, EMC_IO, FUNC2); // PD_12: CS2
|
||||
|
||||
#if (USE_EXT_DYNAMIC_MEM == YES)
|
||||
// Control signals for dynamic memory
|
||||
scu_pinmux(0x6, 9, EMC_IO, FUNC3); // P6_9: DYCS0
|
||||
scu_pinmux(0x6, 4, EMC_IO, FUNC3); // P6_4: CAS
|
||||
scu_pinmux(0x6, 5, EMC_IO, FUNC3); // P6_5: RAS
|
||||
scu_pinmux(0x6, 11, EMC_IO, FUNC3); // P6_11: CKEOUT0
|
||||
scu_pinmux(0x6, 12, EMC_IO, FUNC3); // P6_12: DQMOUT0
|
||||
scu_pinmux(0x6, 10, EMC_IO, FUNC3); // P6_10: DQMOUT1
|
||||
|
||||
LPC_SCU_CLK(0) = 0 + EMC_IO; // EMC_CLK0 signal on pin CLK0 (needed for SDRAM)
|
||||
LPC_SCU_CLK(1) = 0 + EMC_IO;
|
||||
LPC_SCU_CLK(2) = 0 + EMC_IO;
|
||||
LPC_SCU_CLK(3) = 0 + EMC_IO;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Configure CS0 for 70ns 16-bit flash memory on the Hitex board
|
||||
* Configure CS2 for 55ns 16-bit SRAM on the Hitex board
|
||||
*
|
||||
****************************************************************************************/
|
||||
void EMC_Config_Static(void)
|
||||
{
|
||||
|
||||
// Configure CS0 for flash memory
|
||||
// @120MHz there should be 8 or 9 waitstates for the 70ns flash, apparently it works with 7
|
||||
LPC_EMC->STATICCONFIG0 = 0x00000081; // CS0: 16 bit = WE
|
||||
LPC_EMC->STATICWAITOEN0 = 0; // CS0: WAITOEN = 0
|
||||
|
||||
#if (PLATFORM == HITEX_A2_BOARD)
|
||||
|
||||
LPC_EMC->STATICWAITRD0 = 7; // CS0: WAITRD = 7
|
||||
|
||||
// The Hitex board has external SRAM on CS2
|
||||
// @120MHz there should be 7 waitstates for the 55ns SRAM, it should work with 6
|
||||
LPC_EMC->STATICCONFIG0 = 0x00000081; // CS2: 16 bit = WE
|
||||
LPC_EMC->STATICWAITOEN2 = 0; // CS2: WAITOEN = 0
|
||||
LPC_EMC->STATICWAITRD2 = 7; // CS2: WAITRD = 6
|
||||
|
||||
#elif (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
LPC_EMC->STATICWAITRD0 = check 9; // CS0: WAITRD = 8
|
||||
// to be added
|
||||
|
||||
LPC_EMC->STATICCONFIG0 = check 0x00000081; // CS2: 16 bit = WE
|
||||
LPC_EMC->STATICWAITOEN2 = check 0; // CS2: WAITOEN = 0
|
||||
LPC_EMC->STATICWAITRD2 = check 7; // CS2: WAITRD = 6
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
// Defines for EMC signal delay settings
|
||||
#define EMC_B_ENABLE (1 << 19)
|
||||
#define EMC_ENABLE (1 << 0)
|
||||
#define EMC_CE_ENABLE (1 << 0)
|
||||
#define EMC_CS_ENABLE (1 << 1)
|
||||
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
|
||||
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
|
||||
#define EMC_INIT(i) ((i) << 7)
|
||||
#define EMC_NORMAL (0)
|
||||
#define EMC_MODE (1)
|
||||
#define EMC_PRECHARGE_ALL (2)
|
||||
#define EMC_NOP (3)
|
||||
|
||||
/****************************************************************************************
|
||||
* Configure the delays for the SDRAM
|
||||
*
|
||||
* - on the Hitex board (IS42S16400D-7TL)
|
||||
* - on the NXP evaluation board (MT48LC4M32B2)
|
||||
* - on the NXP validation board (MT48LC4M32B2)
|
||||
*
|
||||
****************************************************************************************/
|
||||
#if (PLATFORM == HITEX_A2_BOARD) || (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
// Defines for SDRAM devices
|
||||
#define DOUT_DELAY 0
|
||||
#define CLK0_DELAY 5
|
||||
#define CLKE0_DELAY 5
|
||||
#define RAS_DELAY 0
|
||||
#define CAS_DELAY 0
|
||||
#define WE_DELAY 0
|
||||
#define DYCS0_DELAY 0
|
||||
#define DQM0_DELAY 0
|
||||
#define FBCLK0_DELAY 0
|
||||
#define CCLK_DELAY 0
|
||||
#define ADDR_DELAY 0
|
||||
#define DIN_DELAY 0
|
||||
#define DEN_DELAY 0
|
||||
|
||||
#endif
|
||||
|
||||
void initEmiDelays(void)
|
||||
{
|
||||
// eventually configure delays, defaults are zero
|
||||
|
||||
// CLK & CLKE0 delay
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD00) = ((CLK0_DELAY << 16) | (CLKE0_DELAY << 0) );
|
||||
|
||||
// EMCCTRLDELAY, address 0x4008 6D04
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD04) = ((WE_DELAY << 12)| (CAS_DELAY << 4) | (RAS_DELAY << 0) );
|
||||
|
||||
// DYCS0_DELAY, address 0x4008 6D08
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD08) = ((DYCS0_DELAY << 0));
|
||||
|
||||
// data out delay for D0 to D31 EMCDOUTDELAY
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD0C) = ((DOUT_DELAY << 28) | (DOUT_DELAY << 24) | (DOUT_DELAY << 20) | (DOUT_DELAY << 16)|(DQM0_DELAY << 12) | (DQM0_DELAY << 8) | (DQM0_DELAY << 4) | (DQM0_DELAY << 0)) ;
|
||||
|
||||
// EMCFBCLKDELAY, address 0x4008 6D10
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD10) = ((CCLK_DELAY << 16)|(FBCLK0_DELAY << 12) | (FBCLK0_DELAY << 8) | (FBCLK0_DELAY << 4) | (FBCLK0_DELAY << 0)) ;
|
||||
|
||||
// EMCADDRDELAY, address 0x4008 6D14, 0x4008 6D18, 0x4008 6D1C)
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD14) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD18) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD1C) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
|
||||
|
||||
// data in delay for D0 to D31 EMCDINDELAY
|
||||
*(uint32_t*)(LPC_SCU_BASE + 0xD24) = ((DEN_DELAY << 28)|(DEN_DELAY << 24)|(DEN_DELAY << 20)|(DEN_DELAY << 16)|(DIN_DELAY << 12)|(DIN_DELAY << 8)|(DIN_DELAY << 4)|(DIN_DELAY << 0));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************************
|
||||
* Configure the EMI for the SDRAM
|
||||
*
|
||||
* - on the Hitex board (IS42S16400D-7TL)
|
||||
* - on the NXP validation board (MT48LC4M32B2)
|
||||
*
|
||||
****************************************************************************************/
|
||||
void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
|
||||
{
|
||||
|
||||
// calculate a 1 usec delay base
|
||||
delayBase1us = M4Frequency / DELAY_1usFreq;
|
||||
|
||||
// eventually adjust the CCU delays for EMI (default to zero)
|
||||
initEmiDelays();
|
||||
|
||||
// Initialize EMC to interface with SDRAM. The EMC needs to run for this.
|
||||
LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller
|
||||
LPC_EMC->CONFIG = 0;
|
||||
|
||||
#if (PLATFORM == HITEX_A2_BOARD)
|
||||
|
||||
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.
|
||||
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0.
|
||||
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.
|
||||
LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period
|
||||
LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period
|
||||
LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time
|
||||
LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time
|
||||
LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.
|
||||
LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time
|
||||
LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period
|
||||
LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period
|
||||
LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time
|
||||
LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency
|
||||
LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
|
||||
|
||||
// Write configuration data to SDRAM device
|
||||
if(u32DataBus == 0) // 16-bit data bus, the EMC enforces a burst size 8
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
|
||||
}
|
||||
else // burst size 4 (which is not an option for 16-bit data bus anyway)
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
|
||||
}
|
||||
#endif // HITEX_BOARD
|
||||
|
||||
|
||||
#if (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));
|
||||
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8);
|
||||
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
|
||||
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
|
||||
LPC_EMC->DYNAMICRAS = 2;
|
||||
LPC_EMC->DYNAMICSREX = 5;
|
||||
LPC_EMC->DYNAMICAPR = 0;
|
||||
LPC_EMC->DYNAMICDAL = 4;
|
||||
LPC_EMC->DYNAMICWR = 1;
|
||||
LPC_EMC->DYNAMICRC = 5;
|
||||
LPC_EMC->DYNAMICRFC = 5;
|
||||
LPC_EMC->DYNAMICXSR = 5;
|
||||
LPC_EMC->DYNAMICRRD = 0;
|
||||
LPC_EMC->DYNAMICMRD = 0;
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 2;
|
||||
vDelay(100);
|
||||
|
||||
LPC_EMC->DYNAMICREFRESH = 83;
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
|
||||
|
||||
// Write configuration data to SDRAM device
|
||||
if(u32DataBus == 0) // burst size 8
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
|
||||
}
|
||||
else // burst size 4
|
||||
{
|
||||
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
|
||||
}
|
||||
#endif // Validation board
|
||||
|
||||
LPC_EMC->DYNAMICCONTROL = 0;
|
||||
LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
** Function name:
|
||||
**
|
||||
** Description:
|
||||
**
|
||||
** Parameters:
|
||||
**
|
||||
** Returned value:
|
||||
**********************************************************************/
|
||||
static void vDelay(uint32_t u32Delay)
|
||||
{
|
||||
volatile uint32_t i;
|
||||
|
||||
for(i = 0; i < (u32Delay * delayBase1us); i++);
|
||||
}
|
||||
|
||||
89
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/emc_LPC43xx.h
Normal file
89
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/emc_LPC43xx.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
//BF: take over the whole file
|
||||
|
||||
/***********************************************************************
|
||||
* $Id: emc_LPC43xx.h 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC18xx_43xx.h
|
||||
*
|
||||
* Project: NXP LPC18xx/LPC43xx Common
|
||||
*
|
||||
* Description: Header file for emc_LPC18xx_43xx.c
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef EMC_LPC43XX_H_
|
||||
#define EMC_LPC43XX_H_
|
||||
|
||||
|
||||
enum {
|
||||
PART_WIDTH_8 = 0,
|
||||
PART_WIDTH_16 = 1,
|
||||
PART_WIDTH_32 = 2
|
||||
};
|
||||
|
||||
enum {
|
||||
PART_SIZE_16 = 0,
|
||||
PART_SIZE_64 = 1,
|
||||
PART_SIZE_128 = 2,
|
||||
PART_SIZE_256 = 3,
|
||||
PART_SIZE_512 = 4
|
||||
};
|
||||
|
||||
enum {
|
||||
EXT_WIDTH_16 = 0,
|
||||
EXT_WIDTH_32 = 1
|
||||
};
|
||||
|
||||
|
||||
#if (PLATFORM == HITEX_A2_BOARD) //defined USE_HITEX_A2
|
||||
|
||||
#define SDRAM_SIZE 0x00800000 // 8 MByte SDRAM IS42S16400D-7TL
|
||||
#define SDRAM_BASE 0x28000000 // base address for DYCS0
|
||||
|
||||
// We have 16 data lines connected to the SDRAM
|
||||
#define PART_WIDTH (PART_WIDTH_16) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.
|
||||
#define PART_SIZE (PART_SIZE_64)
|
||||
#define EXT_WIDTH (EXT_WIDTH_16) // external memory bus width
|
||||
#define COL_ADDR_BITS (8) // for calculating how to write mode bits
|
||||
|
||||
#endif
|
||||
|
||||
#if (PLATFORM == NXP_VALIDATION_BOARD)
|
||||
|
||||
#define SDRAM_SIZE 0x01000000 // 16 MByte SDRAM MT48LC4M32
|
||||
#define SDRAM_BASE 0x28000000 // base address for DYCS0
|
||||
|
||||
// We have 32 data lines connected to the SDRAM
|
||||
#define PART_WIDTH (PART_WIDTH_32) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.
|
||||
#define PART_SIZE (PART_SIZE_128)
|
||||
#define EXT_WIDTH (EXT_WIDTH_32) // external memory bus width
|
||||
#define COL_ADDR_BITS (8) // for calculating how to write mode bits
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Function prototypes
|
||||
void EMC_Init( void );
|
||||
void EMC_Config_Pinmux( void );
|
||||
void EMC_Config_Static( void );
|
||||
void initEmiDelays( void );
|
||||
void EMC_Init_SRDRAM( uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits );
|
||||
|
||||
|
||||
#endif /* EMC_LPC43XX_H_ */
|
||||
|
||||
|
||||
|
||||
69
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/fpu_init.c
Normal file
69
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/fpu_init.c
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/***********************************************************************
|
||||
* $Id: fpu_init.c
|
||||
*
|
||||
* Project: LPC43xx
|
||||
*
|
||||
* Description: fpu initialization routine
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#define LPC_CPACR 0xE000ED88
|
||||
|
||||
#define SCB_MVFR0 0xE000EF40
|
||||
#define SCB_MVFR0_RESET 0x10110021
|
||||
|
||||
#define SCB_MVFR1 0xE000EF44
|
||||
#define SCB_MVFR1_RESET 0x11000011
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
void fpuInit(void)
|
||||
{
|
||||
// from arm trm manual:
|
||||
// ; CPACR is located at address 0xE000ED88
|
||||
// LDR.W R0, =0xE000ED88
|
||||
// ; Read CPACR
|
||||
// LDR R1, [R0]
|
||||
// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||
// ORR R1, R1, #(0xF << 20)
|
||||
// ; Write back the modified value to the CPACR
|
||||
// STR R1, [R0]
|
||||
|
||||
|
||||
volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
|
||||
volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
|
||||
volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
|
||||
volatile uint32_t Cpacr;
|
||||
volatile uint32_t Mvfr0;
|
||||
volatile uint32_t Mvfr1;
|
||||
char vfpPresent = 0;
|
||||
|
||||
Mvfr0 = *regMvfr0;
|
||||
Mvfr1 = *regMvfr1;
|
||||
|
||||
vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
|
||||
|
||||
if(vfpPresent)
|
||||
{
|
||||
Cpacr = *regCpacr;
|
||||
Cpacr |= (0xF << 20);
|
||||
*regCpacr = Cpacr; // enable CP10 and CP11 for full access
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
29
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/fpu_init.h
Normal file
29
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/fpu_init.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/***********************************************************************
|
||||
* $Id: fpu_init.h
|
||||
*
|
||||
* Project: LPC43xx
|
||||
*
|
||||
* Description: fpu initialization routine header
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __FPU_INIT_H
|
||||
#define __FPU_INIT_H
|
||||
|
||||
void fpuInit(void);
|
||||
|
||||
#endif /* __FPU_INIT_H */
|
||||
37
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/scu.c
Normal file
37
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/scu.c
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/***********************************************************************
|
||||
* $Id: scu.c 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* This file contains code to configure the PINMUX
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#if defined CORE_M4
|
||||
#include "LPC43xx.h" /* LPC43xx definitions */
|
||||
#endif
|
||||
|
||||
#ifdef CORE_M0
|
||||
#include "LPC43xx_M0.h" /* LPC43xx definitions */
|
||||
#endif
|
||||
|
||||
#include "type.h"
|
||||
#include "scu.h"
|
||||
|
||||
void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func)
|
||||
{
|
||||
volatile unsigned int * const scu_base=(unsigned int*)(LPC_SCU_BASE);
|
||||
scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func;
|
||||
} /* scu_pinmux */
|
||||
125
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/scu.h
Normal file
125
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/scu.h
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/***********************************************************************
|
||||
* $Id: scu.h 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* Header file for PINMUX configuration
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
#ifndef __SCU_H
|
||||
#define __SCU_H
|
||||
|
||||
#define PORT_OFFSET 0x80
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin modes */
|
||||
//#define MD_PUP (0x0<<3)
|
||||
//#define MD_BUK (0x1<<3)
|
||||
//#define MD_PLN (0x2<<3)
|
||||
//#define MD_PDN (0x3<<3)
|
||||
//#define MD_EHS (0x1<<5)
|
||||
//#define MD_EZI (0x1<<6)
|
||||
//#define MD_ZI (0x1<<7)
|
||||
//#define MD_EHD0 (0x1<<8)
|
||||
//#define MD_EHD1 (0x1<<8)
|
||||
|
||||
/* Pin modes
|
||||
* =========
|
||||
* The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip
|
||||
* pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the
|
||||
* selection of the repeater mode.
|
||||
* The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
|
||||
* pull-up/pull-down. The default value is pull-up enabled.
|
||||
*
|
||||
* The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
|
||||
* the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
|
||||
* known state if it is configured as an input and is not driven externally. Repeater mode may
|
||||
* typically be used to prevent a pin from floating (and potentially using significant power if it
|
||||
* floats to an indeterminate state) if it is temporarily not driven.
|
||||
*
|
||||
* To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
|
||||
* the pin configuration registers. By default, the input buffer is disabled.
|
||||
* For pads that support both a digital and an analog function, the input buffer must be
|
||||
* disabled before enabling the analog function
|
||||
*
|
||||
* All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
|
||||
* off. By default, the glitch filter is on. The glitch filter should be disabled for
|
||||
* clocking signals with frequencies higher than 30 MHz.
|
||||
*
|
||||
* Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
|
||||
* between lower noise and low speed or higher noise and high speed . The typical
|
||||
* frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for
|
||||
* high-speed pins.
|
||||
*/
|
||||
|
||||
/* these definitions allow to set or clear single configuration bits */
|
||||
#define PDN_SET (1 << 3)
|
||||
#define PDN_CLR (0)
|
||||
#define PUP_SET (0)
|
||||
#define PUP_CLR (1 << 4)
|
||||
|
||||
/* these definitions allow to configure the port in one specific mode */
|
||||
/* within scu_pinmux() function */
|
||||
#define PDN_ENABLE (0x3 << 3) /* pull down */
|
||||
#define PUP_ENABLE (0x0 << 3) /* pull up */
|
||||
#define REPEATER_ENABLE (0x1 << 3) /* repeater */
|
||||
#define PLAIN_ENABLE (0x2 << 3) /* no pull up, no pull down (plain) */
|
||||
|
||||
#define SLEWRATE_SLOW (0)
|
||||
#define SLEWRATE_FAST (1 << 5)
|
||||
|
||||
/* enable / disable the input buffer */
|
||||
#define INBUF_ENABLE (1 << 6)
|
||||
#define INBUF_DISABLE (0)
|
||||
|
||||
/* enable / disable the filter */
|
||||
#define FILTER_ENABLE (0)
|
||||
#define FILTER_DISABLE (1 << 7)
|
||||
|
||||
/* define the drive strenght */
|
||||
#define DRIVE_8MA (0x1 << 8) // Drive strength of 8mA
|
||||
#define DRIVE_14MA (0x1 << 9) // Drive strength of 14mA
|
||||
#define DRIVE_20MA (0x3 << 8) // Drive strength of 20mA
|
||||
|
||||
|
||||
|
||||
// Configuration examples for external memory bus pins
|
||||
#define EMC_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE)
|
||||
#define EMC_IO (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
// Configuration examples
|
||||
#define CLK_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE)
|
||||
#define CLK_IN (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
/* Pin functions */
|
||||
#define FUNC0 0x0
|
||||
#define FUNC1 0x1
|
||||
#define FUNC2 0x2
|
||||
#define FUNC3 0x3
|
||||
#define FUNC4 0x4
|
||||
#define FUNC5 0x5
|
||||
#define FUNC6 0x6
|
||||
#define FUNC7 0x7
|
||||
|
||||
extern void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func);
|
||||
|
||||
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
|
||||
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
|
||||
|
||||
|
||||
#endif /* end __SCU_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
422
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/startup_LPC43xx.s
Normal file
422
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/startup_LPC43xx.s
Normal file
|
|
@ -0,0 +1,422 @@
|
|||
;/***********************************************************************
|
||||
; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
; *
|
||||
; * Project: LPC43xx CMSIS Package
|
||||
; *
|
||||
; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx
|
||||
; * Device Series.
|
||||
; *
|
||||
; * Copyright(C) 2011, NXP Semiconductor
|
||||
; * All rights reserved.
|
||||
; *
|
||||
; ***********************************************************************
|
||||
; * Software that is described herein is for illustrative purposes only
|
||||
; * which provides customers with programming information regarding the
|
||||
; * products. This software is supplied "AS IS" without any warranties.
|
||||
; * NXP Semiconductors assumes no responsibility or liability for the
|
||||
; * use of the software, conveys no license or title under any patent,
|
||||
; * copyright, or mask work right to the product. NXP Semiconductors
|
||||
; * reserves the right to make changes in the software without
|
||||
; * notification. NXP Semiconductors also make no representation or
|
||||
; * warranty that such application will be suitable for the specified
|
||||
; * use without further testing or modification.
|
||||
; **********************************************************************/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __endVectors
|
||||
|
||||
Sign_Value EQU 0x5A5A5A5A
|
||||
|
||||
; IF :DEF:EXT_FLASH
|
||||
;
|
||||
;Signature_Size EQU 0x10
|
||||
; DCD 0x000200DA
|
||||
; DCD 0x00000000
|
||||
; DCD 0x00000000
|
||||
; DCD 0x00000000
|
||||
; SPACE Signature_Size
|
||||
; DCD __initial_sp
|
||||
; DCD Reset_Handler ; 1 Reset Handler
|
||||
; FILL 256 - 8 - 16
|
||||
; ENDIF
|
||||
|
||||
|
||||
__Vectors DCD __initial_sp ; 0 Top of Stack
|
||||
DCD Reset_Handler ; 1 Reset Handler
|
||||
DCD NMI_Handler ; 2 NMI Handler
|
||||
DCD HardFault_Handler ; 3 Hard Fault Handler
|
||||
DCD MemManage_Handler ; 4 MPU Fault Handler
|
||||
DCD BusFault_Handler ; 5 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; 6 Usage Fault Handler
|
||||
DCD Sign_Value ; 7 Reserved
|
||||
DCD 0 ; 8 Reserved
|
||||
DCD 0 ; 9 Reserved
|
||||
DCD 0 ; 10 Reserved
|
||||
DCD SVC_Handler ; 11 SVCall Handler
|
||||
DCD DebugMon_Handler ; 12 Debug Monitor Handler
|
||||
DCD 0 ; 13 Reserved
|
||||
DCD PendSV_Handler ; 14 PendSV Handler
|
||||
DCD SysTick_Handler ; 15 SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DAC_IRQHandler ; 16 D/A Converter
|
||||
DCD M0_IRQHandler ; 17 M0
|
||||
DCD DMA_IRQHandler ; 18 General Purpose DMA
|
||||
DCD 0 ; 19 Reserved
|
||||
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
|
||||
DCD ETH_IRQHandler ; 21 Ethernet
|
||||
DCD SDIO_IRQHandler ; 22 SD/MMC
|
||||
DCD LCD_IRQHandler ; 23 LCD
|
||||
DCD USB0_IRQHandler ; 24 USB0
|
||||
DCD USB1_IRQHandler ; 25 USB1
|
||||
DCD SCT_IRQHandler ; 26 State Configurable Timer
|
||||
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
|
||||
DCD TIMER0_IRQHandler ; 28 Timer0
|
||||
DCD TIMER1_IRQHandler ; 29 Timer1
|
||||
DCD TIMER2_IRQHandler ; 30 Timer2
|
||||
DCD TIMER3_IRQHandler ; 31 Timer3
|
||||
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
|
||||
DCD ADC0_IRQHandler ; 33 A/D Converter 0
|
||||
DCD I2C0_IRQHandler ; 34 I2C0
|
||||
DCD I2C1_IRQHandler ; 35 I2C1
|
||||
DCD SPI_IRQHandler ; 36 SPI
|
||||
DCD ADC1_IRQHandler ; 37 A/D Converter 1
|
||||
DCD SSP0_IRQHandler ; 38 SSP0
|
||||
DCD SSP1_IRQHandler ; 39 SSP1
|
||||
DCD UART0_IRQHandler ; 40 UART0
|
||||
DCD UART1_IRQHandler ; 41 UART1
|
||||
DCD UART2_IRQHandler ; 42 UART2
|
||||
DCD UART3_IRQHandler ; 43 UART3
|
||||
DCD I2S0_IRQHandler ; 44 I2S0
|
||||
DCD I2S1_IRQHandler ; 45 I2S1
|
||||
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
|
||||
DCD SGPIO_IRQHandler ; 47 SGPIO
|
||||
DCD GPIO0_IRQHandler ; 48 GPIO0
|
||||
DCD GPIO1_IRQHandler ; 49 GPIO1
|
||||
DCD GPIO2_IRQHandler ; 50 GPIO2
|
||||
DCD GPIO3_IRQHandler ; 51 GPIO3
|
||||
DCD GPIO4_IRQHandler ; 52 GPIO4
|
||||
DCD GPIO5_IRQHandler ; 53 GPIO5
|
||||
DCD GPIO6_IRQHandler ; 54 GPIO6
|
||||
DCD GPIO7_IRQHandler ; 55 GPIO7
|
||||
DCD GINT0_IRQHandler ; 56 GINT0
|
||||
DCD GINT1_IRQHandler ; 57 GINT1
|
||||
DCD EVRT_IRQHandler ; 58 Event Router
|
||||
DCD CAN1_IRQHandler ; 59 C_CAN1
|
||||
DCD 0 ; 60 Reserved
|
||||
DCD VADC_IRQHandler ; 61 VADC
|
||||
DCD ATIMER_IRQHandler ; 62 ATIMER
|
||||
DCD RTC_IRQHandler ; 63 RTC
|
||||
DCD 0 ; 64 Reserved
|
||||
DCD WDT_IRQHandler ; 65 WDT
|
||||
DCD 0 ; 66 Reserved
|
||||
DCD CAN0_IRQHandler ; 67 C_CAN0
|
||||
DCD QEI_IRQHandler ; 68 QEI
|
||||
|
||||
__endVectors
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
|
||||
IF :DEF:EXT_FLASH
|
||||
|
||||
; Extend the address bus, as the bootloader configured only [A13:0]
|
||||
; *(uint32_t*)(0x40086320) = 0x000000F1;
|
||||
; P6_8: A14 (function 1)
|
||||
LDR R0, =0x40086320
|
||||
LDR R1, =0x000000F1
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x4008631C) = 0x000000F1;
|
||||
; P6_7: A15 (function 1)
|
||||
LDR R0, =0x4008631C
|
||||
LDR R1, =0x000000F1
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x400866C0) = 0x000000F2;
|
||||
; PD_16: A16 (function 2)
|
||||
LDR R0, =0x400866C0
|
||||
LDR R1, =0x000000F2
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x400866BC) = 0x000000F2;
|
||||
; PD_15: A17 (function 2)
|
||||
LDR R0, =0x400866BC
|
||||
LDR R1, =0x000000F2
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086700) = 0x000000F3;
|
||||
; PE_0: A18 (function 3)
|
||||
LDR R0, =0x40086700
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086704) = 0x000000F3;
|
||||
; PE_1: A19 (function 3)
|
||||
LDR R0, =0x40086704
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086708) = 0x000000F3;
|
||||
; PE_2: A20 (function 3)
|
||||
LDR R0, =0x40086708
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x4008670C) = 0x000000F3;
|
||||
; PE_3: A21 (function 3)
|
||||
LDR R0, =0x4008670C
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
; *(uint32_t*)(0x40086710) = 0x000000F3;
|
||||
; PE_4: A22 (function 3)
|
||||
LDR R0, =0x40086710
|
||||
LDR R1, =0x000000F3
|
||||
STR R1, [R0,#0]
|
||||
|
||||
; IMPORT _startup_configureFlash
|
||||
; LDR R0, =_startup_configureFlash
|
||||
; NOP
|
||||
; NOP
|
||||
; NOP
|
||||
; BLX R0
|
||||
|
||||
ENDIF
|
||||
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
; FreeRTOS handler
|
||||
vPortSVCHandler\
|
||||
PROC
|
||||
EXPORT vPortSVCHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
; FreeRTOS handler
|
||||
xPortPendSVHandler\
|
||||
PROC
|
||||
EXPORT xPortPendSVHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
; FreeRTOS handler
|
||||
xPortSysTickHandler\
|
||||
PROC
|
||||
EXPORT xPortSysTickHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT M0_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USB1_IRQHandler [WEAK]
|
||||
EXPORT SCT_IRQHandler [WEAK]
|
||||
EXPORT RIT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT I2S1_IRQHandler [WEAK]
|
||||
EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SGPIO_IRQHandler [WEAK]
|
||||
EXPORT GPIO0_IRQHandler [WEAK]
|
||||
EXPORT GPIO1_IRQHandler [WEAK]
|
||||
EXPORT GPIO2_IRQHandler [WEAK]
|
||||
EXPORT GPIO3_IRQHandler [WEAK]
|
||||
EXPORT GPIO4_IRQHandler [WEAK]
|
||||
EXPORT GPIO5_IRQHandler [WEAK]
|
||||
EXPORT GPIO6_IRQHandler [WEAK]
|
||||
EXPORT GPIO7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT EVRT_IRQHandler [WEAK]
|
||||
EXPORT CAN1_IRQHandler [WEAK]
|
||||
EXPORT VADC_IRQHandler [WEAK]
|
||||
EXPORT ATIMER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT CAN0_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
|
||||
|
||||
|
||||
|
||||
DAC_IRQHandler
|
||||
M0_IRQHandler
|
||||
DMA_IRQHandler
|
||||
FLASH_EEPROM_IRQHandler
|
||||
ETH_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
LCD_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USB1_IRQHandler
|
||||
SCT_IRQHandler
|
||||
RIT_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
I2S1_IRQHandler
|
||||
SPIFI_IRQHandler
|
||||
SGPIO_IRQHandler
|
||||
GPIO0_IRQHandler
|
||||
GPIO1_IRQHandler
|
||||
GPIO2_IRQHandler
|
||||
GPIO3_IRQHandler
|
||||
GPIO4_IRQHandler
|
||||
GPIO5_IRQHandler
|
||||
GPIO6_IRQHandler
|
||||
GPIO7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
EVRT_IRQHandler
|
||||
CAN1_IRQHandler
|
||||
VADC_IRQHandler
|
||||
ATIMER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
CAN0_IRQHandler
|
||||
QEI_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
590
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/system_LPC43xx.c
Normal file
590
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/system_LPC43xx.c
Normal file
|
|
@ -0,0 +1,590 @@
|
|||
/***********************************************************************
|
||||
* $Id: system_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* CMSIS Cortex-M4 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC43xx Device Series
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#if defined CORE_M4
|
||||
#include "LPC43xx.h" /* LPC18xx definitions */
|
||||
#endif
|
||||
|
||||
#ifdef CORE_M0
|
||||
#include "LPC43xx_M0.h" /* LPC18xx definitions */
|
||||
#endif
|
||||
|
||||
#include "scu.h"
|
||||
#include "type.h"
|
||||
#include "config.h"
|
||||
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------*/
|
||||
//#define OTP
|
||||
#define FLASH_SETUP 0
|
||||
#define FLASHCFG_Val 0x0000303A
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
|
||||
#error "SCS: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
|
||||
#error "CLKSRCSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
|
||||
#error "PLL0CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
|
||||
#error "PLL1CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
|
||||
#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
||||
#error "USBCLKCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
||||
#error "PCLKSEL0: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
||||
#error "PCLKSEL1: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
||||
#error "PCONP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
||||
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
/* Flash Accelerator Configuration -------------------------------------------*/
|
||||
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
|
||||
#error "FLASHCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t XtalFrequency = 0;
|
||||
uint32_t PL160M_0Frequency = 0;
|
||||
uint32_t PL160M_1Frequency = 0;
|
||||
uint32_t PL160M_2Frequency = 0;
|
||||
uint32_t PL550Frequency = 0;
|
||||
uint32_t PL550FracFrequency = 0; //New in Falcon
|
||||
uint32_t IDIVAFrequency = 0;
|
||||
uint32_t IDIVBFrequency = 0;
|
||||
uint32_t IDIVCFrequency = 0;
|
||||
uint32_t IDIVDFrequency = 0;
|
||||
uint32_t IDIVEFrequency = 0;
|
||||
uint32_t USB1Frequency = 0;
|
||||
uint32_t M4Frequency = 0;
|
||||
uint32_t SPIFIFrequency = 0;
|
||||
uint32_t SPIFrequency = 0;
|
||||
uint32_t EnetRxFrequency = 0;
|
||||
uint32_t EnetTxFrequency = 0;
|
||||
uint32_t EXTFrequency = 0;
|
||||
uint32_t VPB1Frequency = 0;
|
||||
uint32_t VPB3Frequency = 0;
|
||||
uint32_t LCDFrequency = 0;
|
||||
uint32_t SCIFrequency = 0;
|
||||
uint32_t VADCFrequency = 0;
|
||||
uint32_t SDIOFrequency = 0;
|
||||
uint32_t SSP0Frequency = 0;
|
||||
uint32_t SSP1Frequency = 0;
|
||||
uint32_t UART0Frequency = 0;
|
||||
uint32_t UART1Frequency = 0;
|
||||
uint32_t UART2Frequency = 0;
|
||||
uint32_t UART3Frequency = 0;
|
||||
uint32_t OUTFrequency = 0;
|
||||
uint32_t AOTESTFrequency = 0;
|
||||
uint32_t ISOFrequency = 0;
|
||||
uint32_t BSRFrequency = 0;
|
||||
uint32_t CLK_TESTFrequency = 0;
|
||||
uint32_t APLLFrequency = 0;
|
||||
uint32_t SPARE0Frequency = 0;
|
||||
uint32_t SPARE1Frequency = 0;
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#ifdef OTP
|
||||
// Set IRC trim if OTP is not programmed.
|
||||
if( *(uint32_t *)LPC_OTP_CTRL_BASE == 0x00FF ||
|
||||
*(uint32_t *)(LPC_OTP_CTRL_BASE+4) == 0x0000)
|
||||
{
|
||||
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
|
||||
}
|
||||
#else
|
||||
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
|
||||
#endif
|
||||
|
||||
// Set all GPIO as input.
|
||||
LPC_GPIO0->DIR = 0x0000;
|
||||
LPC_GPIO1->DIR = 0x0000;
|
||||
LPC_GPIO2->DIR = 0x0000;
|
||||
LPC_GPIO3->DIR = 0x0000;
|
||||
LPC_GPIO4->DIR = 0x0000;
|
||||
LPC_GPIO5->DIR = 0x0000;
|
||||
LPC_GPIO6->DIR = 0x0000;
|
||||
LPC_GPIO7->DIR = 0x0000;
|
||||
|
||||
// M4 runs on IRC by default
|
||||
M4Frequency = IRC_OSC;
|
||||
XtalFrequency = XTAL_FREQ;
|
||||
EXTFrequency = EXT_FREQ;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set Clock
|
||||
*
|
||||
* @param target PLL, source clock, division
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup a clock
|
||||
*/
|
||||
void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div)
|
||||
{
|
||||
volatile uint32_t target_clk_adr;
|
||||
volatile uint8_t auto_block=TRUE;
|
||||
uint32_t src_freq;
|
||||
|
||||
EnableSourceClk(src_clk);
|
||||
|
||||
switch(div)
|
||||
{
|
||||
case(DIV1): // Divide by 1 == no division
|
||||
break;
|
||||
case(DIV2):
|
||||
LPC_CGU->IDIVA_CTRL = (src_clk<<24) | (1<<2) | AUTO_BLOCK;
|
||||
IDIVAFrequency = GetClockFrequency(src_clk)/2;
|
||||
src_clk = SRC_IDIV_0; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV4):
|
||||
LPC_CGU->IDIVB_CTRL = (src_clk<<24) | (3<<2) |AUTO_BLOCK;
|
||||
IDIVBFrequency = GetClockFrequency(src_clk)/4;
|
||||
src_clk = SRC_IDIV_1; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV8):
|
||||
LPC_CGU->IDIVC_CTRL = (src_clk<<24) | (7<<2) |AUTO_BLOCK;
|
||||
IDIVCFrequency = GetClockFrequency(src_clk)/8;
|
||||
src_clk = SRC_IDIV_2; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV16):
|
||||
LPC_CGU->IDIVD_CTRL = (src_clk<<24) | (15<<2) |AUTO_BLOCK;
|
||||
IDIVDFrequency = GetClockFrequency(src_clk)/16;
|
||||
src_clk = SRC_IDIV_3; // Set new src_clk for target_clk
|
||||
break;
|
||||
case(DIV256):
|
||||
LPC_CGU->IDIVE_CTRL = (src_clk<<24) | (255<<2) |AUTO_BLOCK; // MAX 128? IDIV bit 2:9 = 7 bits = 127 max
|
||||
IDIVEFrequency = GetClockFrequency(src_clk)/256;
|
||||
src_clk = SRC_IDIV_4; // Set new src_clk for target_clk
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
src_freq = GetClockFrequency(src_clk);
|
||||
|
||||
switch(target_clk)
|
||||
{
|
||||
case(BASE_OUT_CLK):
|
||||
{
|
||||
LPC_SCU->SFSCLK_0 = 1; // function 1; CGU clk out, diable pull down, disable pull-up
|
||||
auto_block = FALSE;
|
||||
break;
|
||||
}
|
||||
case(XTAL):
|
||||
{
|
||||
XtalFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
|
||||
break;
|
||||
}
|
||||
case(ENET_RX):
|
||||
{
|
||||
EnetRxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
|
||||
break;
|
||||
}
|
||||
case(ENET_TX):
|
||||
{
|
||||
EnetTxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
|
||||
break;
|
||||
}
|
||||
case(BASE_USB1_CLK):
|
||||
{
|
||||
USB1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_M4_CLK):
|
||||
{
|
||||
M4Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPIFI_CLK):
|
||||
{
|
||||
SPIFIFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPI_CLK):
|
||||
{
|
||||
SPIFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_PHY_RX_CLK):
|
||||
{
|
||||
EnetRxFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_PHY_TX_CLK):
|
||||
{
|
||||
EnetTxFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_VPB1_CLK):
|
||||
{
|
||||
VPB1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_VPB3_CLK):
|
||||
{
|
||||
VPB3Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_LCD_CLK):
|
||||
{
|
||||
LCDFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case (BASE_VADC_CLK) :
|
||||
{
|
||||
VADCFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SDIO_CLK):
|
||||
{
|
||||
SDIOFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SSP0_CLK):
|
||||
{
|
||||
SSP0Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SSP1_CLK):
|
||||
{
|
||||
SSP1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART0_CLK):
|
||||
{
|
||||
UART0Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART1_CLK):
|
||||
{
|
||||
UART1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART2_CLK):
|
||||
{
|
||||
UART2Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_UART3_CLK):
|
||||
{
|
||||
UART3Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_AOTEST_CLK):
|
||||
{
|
||||
AOTESTFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_ISO_TCK):
|
||||
{
|
||||
ISOFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_BSR_TCK):
|
||||
{
|
||||
BSRFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_CLK_TEST):
|
||||
{
|
||||
CLK_TESTFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_APLL_CLK): //New in Falcon
|
||||
{
|
||||
APLLFrequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPARE0_CLK): //New in Falcon
|
||||
{
|
||||
SPARE0Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
case(BASE_SPARE1_CLK): //New in Falcon
|
||||
{
|
||||
SPARE1Frequency = src_freq;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if(target_clk<200)
|
||||
{
|
||||
target_clk_adr = (uint32_t) &LPC_CGU->IDIVA_CTRL + (target_clk-2)*4;
|
||||
*(uint32_t *)target_clk_adr = (src_clk<<24) | (auto_block<<11);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Get Clock Frequency
|
||||
*
|
||||
* @param source clock
|
||||
* @return frequency
|
||||
*
|
||||
* @brief returns the current frequency of a base clock
|
||||
*/
|
||||
uint32_t GetClockFrequency(CLKSRC_Type src_clk)
|
||||
{
|
||||
switch(src_clk)
|
||||
{
|
||||
case(SRC_OSC32K):
|
||||
return RTC_CLK;
|
||||
case(SRC_IRC):
|
||||
return IRC_OSC;
|
||||
case(SRC_ENET_RX_CLK):
|
||||
return EnetRxFrequency;
|
||||
case(SRC_ENET_TX_CLK):
|
||||
return EnetTxFrequency;
|
||||
case(SRC_EXT_TCK):
|
||||
return EXTFrequency;
|
||||
case(SRC_XTAL):
|
||||
return XtalFrequency;
|
||||
case(SRC_PL550M_0):
|
||||
return PL550Frequency;
|
||||
case(SRC_PL550M_FRAC): //New in Falcon
|
||||
return PL550FracFrequency;
|
||||
case(SRC_PL160M_0):
|
||||
return PL160M_0Frequency;
|
||||
case(SRC_PL160M_1):
|
||||
return PL160M_1Frequency;
|
||||
case(SRC_PL160M_2):
|
||||
return PL160M_2Frequency;
|
||||
case(SRC_IDIV_0):
|
||||
return IDIVAFrequency;
|
||||
case(SRC_IDIV_1):
|
||||
return IDIVBFrequency;
|
||||
case(SRC_IDIV_2):
|
||||
return IDIVCFrequency;
|
||||
case(SRC_IDIV_3):
|
||||
return IDIVDFrequency;
|
||||
case(SRC_IDIV_4):
|
||||
return IDIVEFrequency;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set PL160M
|
||||
*
|
||||
* @param source clock, desired frequency
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the PL160M PLL
|
||||
* If frequency equals 0 then disable PLL
|
||||
* Integer mode only (fbsel=1, direct=0)
|
||||
* Fclkout = M * Fclkin/N
|
||||
* Fcc0 = 2 * P * Fclkout = 2 * P * M * Fclkin/N
|
||||
* msel+1 = feedback-divider value M (1 to 2^15)
|
||||
* nsel+1 = pre-divider value N (1 to 2^8)
|
||||
* psel+1 = post-divider value P(x2) (1 to 2^5)
|
||||
*/
|
||||
void SetPL160M(CLKSRC_Type src_clk, uint32_t mult)
|
||||
{
|
||||
uint32_t msel=0, nsel=0, psel=0, pval=1;
|
||||
|
||||
// EnableSourceClk(src_clk);
|
||||
|
||||
if(mult==0)
|
||||
{
|
||||
LPC_CGU->PLL1_CTRL |= PD_ENABLE; // Power down PLL
|
||||
DisableSourceClk(src_clk);
|
||||
}
|
||||
else
|
||||
{
|
||||
EnableSourceClk(src_clk);
|
||||
|
||||
switch(src_clk)
|
||||
{
|
||||
case(SRC_OSC32K):
|
||||
PL160M_0Frequency = mult * RTC_CLK;
|
||||
break;
|
||||
case(SRC_IRC):
|
||||
PL160M_0Frequency = mult * IRC_OSC;
|
||||
break;
|
||||
case(SRC_ENET_RX_CLK):
|
||||
PL160M_0Frequency = mult * EnetRxFrequency;
|
||||
break;
|
||||
case(SRC_ENET_TX_CLK):
|
||||
PL160M_0Frequency = mult * EnetTxFrequency;
|
||||
break;
|
||||
case(SRC_EXT_TCK):
|
||||
PL160M_0Frequency = mult * EXTFrequency;
|
||||
break;
|
||||
case(SRC_XTAL):
|
||||
PL160M_0Frequency = mult * XtalFrequency;
|
||||
break;
|
||||
default:
|
||||
PL160M_0Frequency = mult * IRC_OSC;
|
||||
break;
|
||||
}
|
||||
|
||||
// CCO must be in range of 156 - 320 MHz
|
||||
// Increase P if FCCO is too low.
|
||||
msel = mult-1;
|
||||
//psel is encoded such that 0=1, 1=2, 2=4, 3=8
|
||||
while(2*(pval)*PL160M_0Frequency < 156000000) {
|
||||
psel++;
|
||||
pval*=2;
|
||||
}
|
||||
// if(2*(pval)*PL160M_0Frequency > 320000000) {
|
||||
// THIS IS OUT OF RANGE!!!
|
||||
// HOW DO WE ASSERT IN SAMPLE CODE?
|
||||
// __breakpoint(0);
|
||||
// }
|
||||
LPC_CGU->PLL1_CTRL = (src_clk<<24) | (msel<<16) | (nsel<<12) | (psel<<8) | FBSEL;
|
||||
while((LPC_CGU->PLL1_STAT&1) == 0x0); // Wait for PLL lock
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set PLL USB (PL550M)
|
||||
*
|
||||
* @param enable
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the USB PLL to 480 MHz
|
||||
* If enable equals 0 then disable PLL
|
||||
* Only clock sources IRC and XTAL are valid
|
||||
* Mode1a only: Normal operating mode without post- and pre-divider
|
||||
* Fclkout = 2 * M * Fclkin
|
||||
* msel+1 = feedback-divider value M (1 to 2^15)
|
||||
*/
|
||||
void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable)
|
||||
{
|
||||
if(!enable)
|
||||
{
|
||||
LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL
|
||||
}
|
||||
else
|
||||
{
|
||||
// Setup PLL550 to generate 480MHz from 12 MHz crystal
|
||||
LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL
|
||||
// P N
|
||||
LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);
|
||||
// SELP SELI SELR MDEC
|
||||
LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);
|
||||
LPC_CGU->PLL0USB_CTRL =(SRC_XTAL<<24) | (0x3<<2) | CLKEN;
|
||||
|
||||
// Set the USB0 clock source to PLL550 (480MHz)
|
||||
LPC_CGU->BASE_USB0_CLK = (0<<0) | (1<<11) | (SRC_PL550M_0<<24);
|
||||
|
||||
while((LPC_CGU->PLL0USB_STAT&1) == 0x0); // Wait for PLL lock
|
||||
}
|
||||
|
||||
PL550Frequency = 480000000UL;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable source clock pheripheral
|
||||
*
|
||||
* @param clock source
|
||||
* @return none
|
||||
*
|
||||
* @brief Enable clock specific peripherals
|
||||
*/
|
||||
void EnableSourceClk(CLKSRC_Type src_clk)
|
||||
{
|
||||
uint32_t i=0;
|
||||
|
||||
if(src_clk == SRC_OSC32K)
|
||||
{
|
||||
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset
|
||||
LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k
|
||||
}
|
||||
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC3); // enet_rx_clk on PC_0 func 3
|
||||
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC0); // enet_tx_clk on P1_19 func 0
|
||||
if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1))
|
||||
{
|
||||
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M
|
||||
for(i=0;i<0xFFFF;i++);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable source clock pheripheral
|
||||
*
|
||||
* @param clock source
|
||||
* @return none
|
||||
*
|
||||
* @brief Disable clock specific peripherals
|
||||
*/
|
||||
void DisableSourceClk(CLKSRC_Type src_clk)
|
||||
{
|
||||
uint32_t i=0;
|
||||
|
||||
if(src_clk == SRC_OSC32K)
|
||||
{
|
||||
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k
|
||||
LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode
|
||||
}
|
||||
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC0); // nc on PC_0 func 0
|
||||
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC2); // nc on P1_19 func 2
|
||||
if(src_clk == SRC_XTAL)
|
||||
{
|
||||
LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M
|
||||
for(i=0;i<0xFFFF;i++);
|
||||
}
|
||||
}
|
||||
186
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/system_LPC43xx.h
Normal file
186
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/system_LPC43xx.h
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/***********************************************************************
|
||||
* $Id: system_LPC43xx.h 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* CMSIS Cortex-M4 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC43xx Device Series
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC18xx_H
|
||||
#define __SYSTEM_LPC18xx_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "scu.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BUTTON0 !((LPC_GPIO3->PIN>>6)&1) // P6.10
|
||||
#define BUTTON1 !((LPC_GPIO2->PIN>>0)&1) // P4.0
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
DO NOT SET MANUALLY, SET WITH SetClock AND SetPL160M
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern uint32_t XtalFrequency;
|
||||
extern uint32_t PL160M_0Frequency;
|
||||
extern uint32_t PL160M_1Frequency;
|
||||
extern uint32_t PL160M_2Frequency;
|
||||
extern uint32_t PL550Frequency;
|
||||
extern uint32_t PL550FracFrequency; //New in Falcon
|
||||
extern uint32_t IDIVAFrequency;
|
||||
extern uint32_t IDIVBFrequency;
|
||||
extern uint32_t IDIVCFrequency;
|
||||
extern uint32_t IDIVDFrequency;
|
||||
extern uint32_t IDIVEFrequency;
|
||||
extern uint32_t M0Frequency;
|
||||
extern uint32_t USB1Frequency;
|
||||
extern uint32_t M4Frequency;
|
||||
extern uint32_t SPIFIFrequency;
|
||||
extern uint32_t SPIFrequency;
|
||||
extern uint32_t EnetRxFrequency;
|
||||
extern uint32_t EnetTxFrequency;
|
||||
extern uint32_t EXTFrequency;
|
||||
extern uint32_t VPB1Frequency;
|
||||
extern uint32_t VPB3Frequency;
|
||||
extern uint32_t LCDFrequency;
|
||||
extern uint32_t SCIFrequency;
|
||||
extern uint32_t SDIOFrequency;
|
||||
extern uint32_t SSP0Frequency;
|
||||
extern uint32_t SSP1Frequency;
|
||||
extern uint32_t UART0Frequency;
|
||||
extern uint32_t UART1Frequency;
|
||||
extern uint32_t UART2Frequency;
|
||||
extern uint32_t UART3Frequency;
|
||||
extern uint32_t OUTFrequency;
|
||||
extern uint32_t AOTESTFrequency;
|
||||
extern uint32_t ISOFrequency;
|
||||
extern uint32_t BSRFrequency;
|
||||
extern uint32_t CLK_TESTFrequency;
|
||||
extern uint32_t APLLFrequency;
|
||||
extern uint32_t SPARE0Frequency;
|
||||
extern uint32_t SPARE1Frequency;
|
||||
|
||||
|
||||
typedef enum CLKDIV
|
||||
{
|
||||
DIV1 = 1,
|
||||
DIV2 = 2,
|
||||
DIV4 = 4,
|
||||
DIV8 = 8,
|
||||
DIV16 = 16,
|
||||
DIV256 = 256,
|
||||
} CLKDIV_Type;
|
||||
|
||||
typedef enum CLKSRC
|
||||
{
|
||||
SRC_OSC32K = 0,
|
||||
SRC_IRC = 1,
|
||||
SRC_ENET_RX_CLK = 2,
|
||||
SRC_ENET_TX_CLK = 3,
|
||||
SRC_EXT_TCK = 4,
|
||||
RESERVED = 5, // Do NOT use
|
||||
SRC_XTAL = 6,
|
||||
SRC_PL550M_0 = 7,
|
||||
SRC_PL550M_FRAC = 8, //New in Falcon
|
||||
SRC_PL160M_0 = 9,
|
||||
SRC_PL160M_1 = 10,
|
||||
SRC_PL160M_2 = 11,
|
||||
SRC_IDIV_0 = 12,
|
||||
SRC_IDIV_1 = 13,
|
||||
SRC_IDIV_2 = 14,
|
||||
SRC_IDIV_3 = 15,
|
||||
SRC_IDIV_4 = 16,
|
||||
NOT_DEFINED = 0xFFFFFFF, // Force a signed int enum, so every possible frequency can be entered
|
||||
} CLKSRC_Type;
|
||||
|
||||
typedef enum CLKBASE
|
||||
{
|
||||
PL550M = 0, //PL550Frac is new, should be added???
|
||||
PL160M = 1,
|
||||
IDIVA_4 = 2,
|
||||
IDIVB_16 = 3,
|
||||
IDIVC_16 = 4,
|
||||
IDIVD_16 = 5,
|
||||
IDIVE_256 = 6,
|
||||
BASE_SAFE_CLK = 7,
|
||||
BASE_USB0_CLK = 8,
|
||||
BASE_M0_CLK = 9,
|
||||
BASE_USB1_CLK = 10,
|
||||
BASE_M4_CLK = 11,
|
||||
BASE_SPIFI_CLK = 12,
|
||||
BASE_SPI_CLK = 13,
|
||||
BASE_PHY_RX_CLK = 14,
|
||||
BASE_PHY_TX_CLK = 15,
|
||||
BASE_VPB1_CLK = 16,
|
||||
BASE_VPB3_CLK = 17,
|
||||
BASE_LCD_CLK = 18,
|
||||
BASE_VADC_CLK = 19, //New
|
||||
BASE_SDIO_CLK = 20,
|
||||
BASE_SSP0_CLK = 21,
|
||||
BASE_SSP1_CLK = 22,
|
||||
BASE_UART0_CLK = 23,
|
||||
BASE_UART1_CLK = 24,
|
||||
BASE_UART2_CLK = 25,
|
||||
BASE_UART3_CLK = 26,
|
||||
BASE_OUT_CLK = 27,
|
||||
BASE_AOTEST_CLK = 28,
|
||||
BASE_ISO_TCK = 29,
|
||||
BASE_BSR_TCK = 30,
|
||||
BASE_CLK_TEST = 31,
|
||||
BASE_APLL_CLK = 32, //New in Falcon
|
||||
BASE_SPARE0_CLK = 33, //New in Falcon
|
||||
BASE_SPARE1_CLK = 34, //New in Falcon
|
||||
XTAL = 253,
|
||||
ENET_RX = 254,
|
||||
ENET_TX = 255,
|
||||
}CLKBASE_Type;
|
||||
|
||||
// PL550M
|
||||
#define MODE1A (0x3<<2) // Normal operating mode without post-divider and without pre-divider
|
||||
#define MODE1B (0x2<<2) // Normal operating mode with post-divider and without pre-divider
|
||||
#define MODE1C (0x1<<2) // Normal operating mode without post-divider and with pre-divider
|
||||
#define MODE1D (0x0<<2) // Normal operating mode with post-divider and with pre-divider.
|
||||
#define BYPASSOFF (0<<1)
|
||||
#define CLKEN (1<<4)
|
||||
|
||||
// PL160M
|
||||
#define FBSEL (1<<6)
|
||||
#define MSEL_FBDIV(n) (n<<16) // MSEL = feedback-divider value 2*M (1 to 2^15)
|
||||
#define NSEL_PREDIV(n) (n<<12) // NSEL = pre-divider value N (1 to 2^8)
|
||||
#define PSEL_POSTDIV(n) (n<<8) // PSEL = post-divider value P*2 (1 to 2^5)
|
||||
|
||||
// Generic clock properties
|
||||
#define AUTO_BLOCK (1<<11)
|
||||
#define PD_ENABLE (1<<0)
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div);
|
||||
extern void SetPL160M(CLKSRC_Type src_clk, uint32_t mult);
|
||||
extern void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable);
|
||||
extern void EnableSourceClk(CLKSRC_Type src_clk);
|
||||
extern void DisableSourceClk(CLKSRC_Type src_clk);
|
||||
extern void IOInit(void);
|
||||
extern uint32_t GetClockFrequency(CLKSRC_Type src_clk);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC43xx_H */
|
||||
78
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/type.h
Normal file
78
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/type.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/***********************************************************************
|
||||
* $Id: type.h 8242 2011-10-11 15:15:25Z nxp28536 $
|
||||
*
|
||||
* Project: LPC43xx Common
|
||||
*
|
||||
* Description:
|
||||
* Type definition Header file for NXP LPC4300 Family
|
||||
* Microprocessors
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __TYPE_H__
|
||||
#define __TYPE_H__
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
#define ABS(value) (value<0 ? -value : value)
|
||||
|
||||
/**
|
||||
* @brief Flag Status and Interrupt Flag Status type definition
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
|
||||
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
|
||||
|
||||
/**
|
||||
* @brief Functional State Definition
|
||||
*/
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
|
||||
|
||||
/**
|
||||
* @ Status type definition
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
|
||||
|
||||
typedef unsigned char BYTE;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned long DWORD;
|
||||
typedef unsigned int BOOL;
|
||||
|
||||
typedef union _BITS
|
||||
{
|
||||
unsigned char value;
|
||||
struct _bits
|
||||
{
|
||||
unsigned char bit0:1;
|
||||
unsigned char bit1:1;
|
||||
unsigned char bit2:1;
|
||||
unsigned char bit3:1;
|
||||
unsigned char bit4:1;
|
||||
unsigned char bit5:1;
|
||||
unsigned char bit6:1;
|
||||
unsigned char bit7:1;
|
||||
}bits;
|
||||
}BITS;
|
||||
|
||||
#endif /* __TYPE_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue