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Add two Cortex-M4F demo applications.

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This commit is contained in:
Richard Barry 2011-12-08 10:48:36 +00:00
parent e7a1222c5f
commit 08ddd1d00d
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1
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M0/ReadMe.txt Normal file
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This version supports only the cortex-M4F core. Future versions will also support the Cortex-M0 core.

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Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "LPC43xx.h"
#include "core_cm4.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 120000000UL )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 75 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. This example uses I2C to write to the LEDs. As
this takes a finite time, and because a timer callback writes to an LED, the
priority of the timer task is kept to a minimum to ensure it does not disrupt
test tasks that check their own execution times. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 0 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 5 /* 32 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#endif /* FREERTOS_CONFIG_H */

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/******************************************************************************/
/* LPC43XX-FLASH-DEBUG.INI: External Memory Interface initialization for */
/* LPC43xx first revision (Sept 2011). */
/* The purpose is to be able to debug a program */
/* located in the external flash. */
/******************************************************************************/
FUNC void Pre_Setup (void) {
/* configure M0 for infinite loop */
_WDWORD(0x10080000,0x00001F00); /* dummy stack pointer */
_WDWORD(0x10080004,0x000000D5); /* reset handler */
_WDWORD(0x100800D4,0xE7FEE7FE); /* jump to itself instruction for M0a */
_WDWORD(0x40043404,0x10080000); /* M0 shadow pointer. */
/* release M0 from reset to allow Jtag access */
_WDWORD(0x40053104,(~(_RDWORD(0x40053154))) & (~(1<<24)));
// u32Val = (~(u32REG) & (~(1 << 24))); // clear the control bit
// LPC_RGU->RESET_CTRL1 = (~( LPC_RGU->RESET_ACTIVE_STATUS1 )) & (0 << 24); //Release M0
}
FUNC void Setup (void)
{
// With the values used here, the program had to be linked to CS0 memory
// located at 0x1C000000 in the LPC43xx.
/* This would be used in case there is a 16-byte header in the image */
/*
SP = _RDWORD(0x1c000100); // Setup Stack Pointer
PC = _RDWORD(0x1C000104); // Setup Program Counter
_WDWORD(0xE000ED08, 0x1C000100); // Setup Vector Table Offset Register
*/
/* This is used for plain images, without a 16-byte header */
SP = _RDWORD(0x1C000000); // Setup Stack Pointer
PC = _RDWORD(0x1C000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x1C000000); // Setup Vector Table Offset Register
}
FUNC void emc_setup (void)
{
// bus signals for external memory
_WDWORD(0x4008609C, 0x000000F3); /* P1_7: D0 (function 3) */
_WDWORD(0x400860A0, 0x000000F3); /* P1_8: D1 (function 3) */
_WDWORD(0x400860A4, 0x000000F3); /* P1_9: D2 (function 3) */
_WDWORD(0x400860A8, 0x000000F3); /* P1_10: D3 (function 3) */
_WDWORD(0x400860AC, 0x000000F3); /* P1_11: D4 (function 3) */
_WDWORD(0x400860B0, 0x000000F3); /* P1_12: D5 (function 3) */
_WDWORD(0x400860B4, 0x000000F3); /* P1_13: D6 (function 3) */
_WDWORD(0x400860B8, 0x000000F3); /* P1_14: D7 (function 3) */
_WDWORD(0x40086280, 0x000000F2); /* P5_0: D12 (function 2) */
_WDWORD(0x40086284, 0x000000F2); /* P5_1: D13 (function 2) */
_WDWORD(0x40086288, 0x000000F2); /* P5_2: D14 (function 2) */
_WDWORD(0x4008628C, 0x000000F2); /* P5_3: D15 (function 2) */
_WDWORD(0x40086290, 0x000000F2); /* P5_4: D8 (function 2) */
_WDWORD(0x40086294, 0x000000F2); /* P5_5: D9 (function 2) */
_WDWORD(0x40086298, 0x000000F2); /* P5_6: D10 (function 2) */
_WDWORD(0x4008629C, 0x000000F2); /* P5_7: D11 (function 2) */
_WDWORD(0x40086688, 0x000000F2); /* PD_2: D16 (function 2) */
_WDWORD(0x4008668C, 0x000000F2); /* PD_3: D17 (function 2) */
_WDWORD(0x40086690, 0x000000F2); /* PD_4: D18 (function 2) */
_WDWORD(0x40086694, 0x000000F2); /* PD_5: D19 (function 2) */
_WDWORD(0x40086698, 0x000000F2); /* PD_6: D20 (function 2) */
_WDWORD(0x4008669C, 0x000000F2); /* PD_7: D21 (function 2) */
_WDWORD(0x400866A0, 0x000000F2); /* PD_8: D22 (function 2) */
_WDWORD(0x400866A4, 0x000000F2); /* PD_9: D23 (function 2) */
_WDWORD(0x40086714, 0x000000F3); /* PE_5: D24 (function 3) */
_WDWORD(0x40086718, 0x000000F3); /* PE_6: D25 (function 3) */
_WDWORD(0x4008671C, 0x000000F3); /* PE_7: D26 (function 3) */
_WDWORD(0x40086720, 0x000000F3); /* PE_8: D27 (function 3) */
_WDWORD(0x40086724, 0x000000F3); /* PE_9: D28 (function 3) */
_WDWORD(0x40086728, 0x000000F3); /* PE_10: D29 (function 3) */
_WDWORD(0x4008672C, 0x000000F3); /* PE_11: D30 (function 3) */
_WDWORD(0x40086730, 0x000000F3); /* PE_12: D31 (function 3) */
_WDWORD(0x40086124, 0x000000F3); /* P2_9: A0 (function 3) */
_WDWORD(0x40086128, 0x000000F3); /* P2_10: A1 (function 3) */
_WDWORD(0x4008612C, 0x000000F3); /* P2_11: A2 (function 3) */
_WDWORD(0x40086130, 0x000000F3); /* P2_12: A3 (function 3) */
_WDWORD(0x40086134, 0x000000F3); /* P2_13: A4 (function 3) */
_WDWORD(0x40086080, 0x000000F2); /* P1_0: A5 (function 2) */
_WDWORD(0x40086084, 0x000000F2); /* P1_1: A6 (function 2) */
_WDWORD(0x40086088, 0x000000F2); /* P1_2: A7 (function 2) */
_WDWORD(0x40086120, 0x000000F3); /* P2_8: A8 (function 3) */
_WDWORD(0x4008611C, 0x000000F3); /* P2_7: A9 (function 3) */
_WDWORD(0x40086118, 0x000000F2); /* P2_6: A10 (function 2) */
_WDWORD(0x40086108, 0x000000F2); /* P2_2: A11 (function 2) */
_WDWORD(0x40086104, 0x000000F2); /* P2_1: A12 (function 2) */
_WDWORD(0x40086100, 0x000000F2); /* P2_0: A13 (function 2) */
_WDWORD(0x40086320, 0x000000F1); /* P6_8: A14 (function 1) */
_WDWORD(0x4008631C, 0x000000F1); /* P6_7: A15 (function 1) */
_WDWORD(0x400866C0, 0x000000F2); /* PD_16: A16 (function 2) */
_WDWORD(0x400866BC, 0x000000F2); /* PD_15: A17 (function 2) */
_WDWORD(0x40086700, 0x000000F3); /* PE_0: A18 (function 3) */
_WDWORD(0x40086704, 0x000000F3); /* PE_1: A19 (function 3) */
_WDWORD(0x40086708, 0x000000F3); /* PE_2: A20 (function 3) */
_WDWORD(0x4008670C, 0x000000F3); /* PE_3: A21 (function 3) */
_WDWORD(0x40086710, 0x000000F3); /* PE_4: A22 (function 3) */
// control signals for static memory
_WDWORD(0x40086094, 0x000000F3); /* P1_5: CS0 (function 3) */
_WDWORD(0x400866B0, 0x000000F2); /* PD_12: CS2 (function 2) */
_WDWORD(0x40086098, 0x000000F3); /* P1_6: WE (function 3) */
_WDWORD(0x4008608C, 0x000000F3); /* P1_3: OE (function 3) */
_WDWORD(0x40086090, 0x000000F3); /* P1_4: BLS0 (function 3) */
_WDWORD(0x40086318, 0x000000F1); /* P6_6: BLS1 (function 1) */
// configure EMC static memory registers
_WDWORD(0x40005000, 0x00000001); /* Enable the EMC block */
_WDWORD(0x40005200, 0x00000081); /* CS0: 16 bit, WE */
_WDWORD(0x40005208, 0x00000000); /* CS0: WAITOEN = 0 */
_WDWORD(0x4000520C, 0x00000008); /* CS0: WAITRD = 8 @120MHz for 70ns flash */
_WDWORD(0x40005240, 0x00000081); /* CS2: 16 bit, WE */
_WDWORD(0x40005248, 0x00000000); /* CS2: WAITOEN = 0 */
_WDWORD(0x4000524C, 0x00000007); /* CS2: WAITRD = 7 */
}
/******************************************************************************/
/* */
/* */
/* */
/******************************************************************************/
_sleep_(100);
//Pre_setup();
// Just set up the memory interface to enable the correct access to the external
// flash memory on CS0.
emc_setup();
// Download the image. This is not a physical download as the image is
// (already) in the flash.
// If working with ULINK devices an alternative is to check the checkbox "Load Application at Startup" in the
// debug settings of µVision (comment the LOAD instruction out).
// This mechanism is not used here, because somehow it does not work with the JLINK devices.
LOAD Flash\LPC43xx_M4_FLASH.axf INCREMENTAL
// Setup for running from a specific memory location
Setup();

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/******************************************************************************/
/* LPC43XX-FLASH-PROGRAM.INI: External Memory Interface initialization for */
/* LPC43xx first revision (Sept 2011). */
/* The purpose is to be able to program the */
/* external flash using the KEIL µVision utility. */
/******************************************************************************/
FUNC void emc_setup (void)
{
// bus signals for external memory
_WDWORD(0x4008609C, 0x000000F3); /* P1_7: D0 (function 3) */
_WDWORD(0x400860A0, 0x000000F3); /* P1_8: D1 (function 3) */
_WDWORD(0x400860A4, 0x000000F3); /* P1_9: D2 (function 3) */
_WDWORD(0x400860A8, 0x000000F3); /* P1_10: D3 (function 3) */
_WDWORD(0x400860AC, 0x000000F3); /* P1_11: D4 (function 3) */
_WDWORD(0x400860B0, 0x000000F3); /* P1_12: D5 (function 3) */
_WDWORD(0x400860B4, 0x000000F3); /* P1_13: D6 (function 3) */
_WDWORD(0x400860B8, 0x000000F3); /* P1_14: D7 (function 3) */
_WDWORD(0x40086280, 0x000000F2); /* P5_0: D12 (function 2) */
_WDWORD(0x40086284, 0x000000F2); /* P5_1: D13 (function 2) */
_WDWORD(0x40086288, 0x000000F2); /* P5_2: D14 (function 2) */
_WDWORD(0x4008628C, 0x000000F2); /* P5_3: D15 (function 2) */
_WDWORD(0x40086290, 0x000000F2); /* P5_4: D8 (function 2) */
_WDWORD(0x40086294, 0x000000F2); /* P5_5: D9 (function 2) */
_WDWORD(0x40086298, 0x000000F2); /* P5_6: D10 (function 2) */
_WDWORD(0x4008629C, 0x000000F2); /* P5_7: D11 (function 2) */
_WDWORD(0x40086688, 0x000000F2); /* PD_2: D16 (function 2) */
_WDWORD(0x4008668C, 0x000000F2); /* PD_3: D17 (function 2) */
_WDWORD(0x40086690, 0x000000F2); /* PD_4: D18 (function 2) */
_WDWORD(0x40086694, 0x000000F2); /* PD_5: D19 (function 2) */
_WDWORD(0x40086698, 0x000000F2); /* PD_6: D20 (function 2) */
_WDWORD(0x4008669C, 0x000000F2); /* PD_7: D21 (function 2) */
_WDWORD(0x400866A0, 0x000000F2); /* PD_8: D22 (function 2) */
_WDWORD(0x400866A4, 0x000000F2); /* PD_9: D23 (function 2) */
_WDWORD(0x40086714, 0x000000F3); /* PE_5: D24 (function 3) */
_WDWORD(0x40086718, 0x000000F3); /* PE_6: D25 (function 3) */
_WDWORD(0x4008671C, 0x000000F3); /* PE_7: D26 (function 3) */
_WDWORD(0x40086720, 0x000000F3); /* PE_8: D27 (function 3) */
_WDWORD(0x40086724, 0x000000F3); /* PE_9: D28 (function 3) */
_WDWORD(0x40086728, 0x000000F3); /* PE_10: D29 (function 3) */
_WDWORD(0x4008672C, 0x000000F3); /* PE_11: D30 (function 3) */
_WDWORD(0x40086730, 0x000000F3); /* PE_12: D31 (function 3) */
_WDWORD(0x40086124, 0x000000F3); /* P2_9: A0 (function 3) */
_WDWORD(0x40086128, 0x000000F3); /* P2_10: A1 (function 3) */
_WDWORD(0x4008612C, 0x000000F3); /* P2_11: A2 (function 3) */
_WDWORD(0x40086130, 0x000000F3); /* P2_12: A3 (function 3) */
_WDWORD(0x40086134, 0x000000F3); /* P2_13: A4 (function 3) */
_WDWORD(0x40086080, 0x000000F2); /* P1_0: A5 (function 2) */
_WDWORD(0x40086084, 0x000000F2); /* P1_1: A6 (function 2) */
_WDWORD(0x40086088, 0x000000F2); /* P1_2: A7 (function 2) */
_WDWORD(0x40086120, 0x000000F3); /* P2_8: A8 (function 3) */
_WDWORD(0x4008611C, 0x000000F3); /* P2_7: A9 (function 3) */
_WDWORD(0x40086118, 0x000000F2); /* P2_6: A10 (function 2) */
_WDWORD(0x40086108, 0x000000F2); /* P2_2: A11 (function 2) */
_WDWORD(0x40086104, 0x000000F2); /* P2_1: A12 (function 2) */
_WDWORD(0x40086100, 0x000000F2); /* P2_0: A13 (function 2) */
_WDWORD(0x40086320, 0x000000F1); /* P6_8: A14 (function 1) */
_WDWORD(0x4008631C, 0x000000F1); /* P6_7: A15 (function 1) */
_WDWORD(0x400866C0, 0x000000F2); /* PD_16: A16 (function 2) */
_WDWORD(0x400866BC, 0x000000F2); /* PD_15: A17 (function 2) */
_WDWORD(0x40086700, 0x000000F3); /* PE_0: A18 (function 3) */
_WDWORD(0x40086704, 0x000000F3); /* PE_1: A19 (function 3) */
_WDWORD(0x40086708, 0x000000F3); /* PE_2: A20 (function 3) */
_WDWORD(0x4008670C, 0x000000F3); /* PE_3: A21 (function 3) */
_WDWORD(0x40086710, 0x000000F3); /* PE_4: A22 (function 3) */
// signals for static memory
_WDWORD(0x40086094, 0x000000F3); /* P1_5: CS0 (function 3) */
_WDWORD(0x400866B0, 0x000000F2); /* PD_12: CS2 (function 2) */
_WDWORD(0x40086098, 0x000000F3); /* P1_6: WE (function 3) */
_WDWORD(0x4008608C, 0x000000F3); /* P1_3: OE (function 3) */
_WDWORD(0x40086090, 0x000000F3); /* P1_4: BLS0 (function 3) */
_WDWORD(0x40086318, 0x000000F1); /* P6_6: BLS1 (function 1) */
// configure EMC static memory registers
_WDWORD(0x40005000, 0x00000001); /* Enable */
_WDWORD(0x40005200, 0x00000081); /* CS0: 16 bit, WE */
_WDWORD(0x40005208, 0x00000000); /* CS0: WAITOEN = 0 */
_WDWORD(0x4000520C, 0x00000008); /* CS0: WAITRD = 8 */
_WDWORD(0x40005240, 0x00000081); /* CS2: 16 bit, WE */
_WDWORD(0x40005248, 0x00000000); /* CS2: WAITOEN = 0 */
_WDWORD(0x4000524C, 0x00000007); /* CS2: WAITRD = 7 */
}
/******************************************************************************/
/* */
/* */
/* */
/******************************************************************************/
_sleep_(100);
// Just set up the memory interface to enable the correct access to the external
// flash memory on CS0.
emc_setup();

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>LPC43xx_M4_FLASH</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>0</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\FLASH\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
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Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/M4.uvproj Normal file
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<UserProg2Name></UserProg2Name>
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>1</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin -o "$L@L.bin" "$L@L.axf"</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DLM.DLL</SimDlgDll>
<SimDlgDllArguments>-pEMBER</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TLM.DLL</TargetDlgDll>
<TargetDlgDllArguments></TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>0</RestoreWatchpoints>
<RestoreMemoryDisplay>0</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>0</RestoreToolbox>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>.\LPC43XX-M4-FLASH-DEBUG.ini</InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4>.\LPC43XX-M4-FLASH-PROGRAM.ini</Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>0</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x8000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<VariousControls>
<MiscControls>--no_allow_fpreg_for_nonfpdata</MiscControls>
<Define>CORE_M4</Define>
<Undefine></Undefine>
<IncludePath>..\system;..\platform;..\..\Common\include;..\M4;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\platform\M4_PeripheralLibraryFiles</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>1</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<VariousControls>
<MiscControls></MiscControls>
<Define>NO_CRP EXT_FLASH</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10000000</TextAddressRange>
<DataAddressRange>0x10004000</DataAddressRange>
<ScatterFile>..\platform\M4_Flash.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--debug --pad=0xFF</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings>6312</DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>System Code</GroupName>
<Files>
<File>
<FileName>startup_LPC43xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\platform\startup_LPC43xx.s</FilePath>
</File>
<File>
<FileName>system_LPC43xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\system\system_LPC43xx.c</FilePath>
</File>
<File>
<FileName>core_cm4.c</FileName>
<FileType>1</FileType>
<FilePath>..\system\core_cm4.c</FilePath>
</File>
<File>
<FileName>emc_LPC43xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\system\emc_LPC43xx.c</FilePath>
</File>
<File>
<FileName>scu.c</FileName>
<FileType>1</FileType>
<FilePath>..\system\scu.c</FilePath>
</File>
<File>
<FileName>fpu_init.c</FileName>
<FileType>1</FileType>
<FilePath>..\system\fpu_init.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Platform</GroupName>
<Files>
<File>
<FileName>platform_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\platform\platform_config.h</FilePath>
</File>
<File>
<FileName>platform_config.c</FileName>
<FileType>1</FileType>
<FilePath>..\platform\platform_config.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Application_Source</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
<File>
<FileName>ParTest.c</FileName>
<FileType>1</FileType>
<FilePath>.\ParTest.c</FilePath>
</File>
<File>
<FileName>RegTest.c</FileName>
<FileType>1</FileType>
<FilePath>.\RegTest.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FreeRTOS_Source</GroupName>
<Files>
<File>
<FileName>port.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
</File>
<File>
<FileName>heap_2.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\portable\MemMang\heap_2.c</FilePath>
</File>
<File>
<FileName>timers.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\timers.c</FilePath>
</File>
<File>
<FileName>list.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\list.c</FilePath>
</File>
<File>
<FileName>queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\queue.c</FilePath>
</File>
<File>
<FileName>tasks.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\tasks.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Common_Demo_Source</GroupName>
<Files>
<File>
<FileName>sp_flop.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\sp_flop.c</FilePath>
</File>
<File>
<FileName>BlockQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\BlockQ.c</FilePath>
</File>
<File>
<FileName>blocktim.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\blocktim.c</FilePath>
</File>
<File>
<FileName>countsem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\countsem.c</FilePath>
</File>
<File>
<FileName>death.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\death.c</FilePath>
</File>
<File>
<FileName>dynamic.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\dynamic.c</FilePath>
</File>
<File>
<FileName>flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\flash.c</FilePath>
</File>
<File>
<FileName>GenQTest.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\GenQTest.c</FilePath>
</File>
<File>
<FileName>integer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\integer.c</FilePath>
</File>
<File>
<FileName>PollQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\PollQ.c</FilePath>
</File>
<File>
<FileName>recmutex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\recmutex.c</FilePath>
</File>
<File>
<FileName>semtest.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Common\Minimal\semtest.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Peripheral_Library</GroupName>
<Files>
<File>
<FileName>lpc43xx_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\platform\M4_PeripheralLibraryFiles\lpc43xx_i2c.c</FilePath>
</File>
<File>
<FileName>lpc43xx_cgu.c</FileName>
<FileType>1</FileType>
<FilePath>..\platform\M4_PeripheralLibraryFiles\lpc43xx_cgu.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>

188
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/ParTest.c Normal file
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/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Normally, a demo application would define ParTest (parallel port test)
* functions to write to an LED. In this case, four '*' symbols that are
* output to the debug printf() port are used to simulate LED outputs.
*-----------------------------------------------------------*/
/* Standard includes. */
#include <stdio.h>
#include <string.h>
/* Library includes. */
#include "lpc43xx_i2c.h"
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Standard demo include. */
#include "partest.h"
/* The number of LED outputs. */
#define partstMAX_LEDS 4
/* Commands written to the PCA9502. */
#define partstIO_WRITE_COMMAND ( ( unsigned char ) ( 0x0BU << 3U ) )
#define partstIO_DIR_COMMAND ( ( unsigned char ) ( 0x0AU << 3U ) )
#define partstSLAVE_ADDRESS ( ( unsigned char ) ( 0x9AU >> 1U ) )
/* Just defines the length of the queue used to pass toggle commands to the I2C
gatekeeper task. */
#define partstLED_COMMAND_QUEUE_LENGTH ( 6 )
/*-----------------------------------------------------------*/
/*
* The LEDs are connected to an I2C port expander. Therefore, writing to an
* LED takes longer than might be expected if the LED was connected directly
* to a GPIO pin. As several tasks, and a timer, toggle LEDs, it is convenient
* to use a gatekeeper task to ensure access is both mutually exclusive and
* serialised. Tasks other than this gatekeeper task must not access the I2C
* port directly.
*/
static void prvI2CGateKeeperTask( void *pvParameters );
/* The queue used to communicate toggle commands with the I2C gatekeeper
task. */
static xQueueHandle xI2CCommandQueue = NULL;
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
unsigned char ucBuffer[ 2 ];
I2C_M_SETUP_Type xI2CMessage;
/* The LEDs are on an I2C IO expander. Initialise the I2C interface. */
I2C_Init( LPC_I2C0, 300000 );
I2C_Cmd( LPC_I2C0, ENABLE );
/* GPIO0-GPIO2 to output. */
ucBuffer[ 0 ] = partstIO_DIR_COMMAND;
ucBuffer[ 1 ] = 0x0f;
xI2CMessage.sl_addr7bit = partstSLAVE_ADDRESS;
xI2CMessage.tx_data = ucBuffer ;
xI2CMessage.tx_length = sizeof( ucBuffer );
xI2CMessage.rx_data = NULL;
xI2CMessage.rx_length = 0;
xI2CMessage.retransmissions_max = 3;
I2C_MasterTransferData( LPC_I2C0, &xI2CMessage, I2C_TRANSFER_POLLING );
/* Create the mutex used to guard access to the I2C bus. */
xI2CCommandQueue = xQueueCreate( partstLED_COMMAND_QUEUE_LENGTH, sizeof( unsigned char ) );
configASSERT( xI2CCommandQueue );
/* Create the I2C gatekeeper task itself. */
xTaskCreate( prvI2CGateKeeperTask, ( signed char * ) "I2C", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned long ulLED )
{
unsigned char ucLED = ( unsigned char ) ulLED;
/* Only the gatekeeper task will actually access the I2C port, so send the
toggle request to the gatekeeper task. A block time of zero is used as
this function is called by a software timer callback. */
xQueueSend( xI2CCommandQueue, &ucLED, 0UL );
}
/*-----------------------------------------------------------*/
static void prvI2CGateKeeperTask( void *pvParameters )
{
unsigned char ucBuffer[ 2 ], ucLED;
static unsigned char ucLEDState = 0xffU;
static I2C_M_SETUP_Type xI2CMessage; /* Static so it is not on the stack as this is called from task code. */
/* Just to remove compiler warnings. */
( void ) pvParameters;
for( ;; )
{
/* Wait for the next command. */
xQueueReceive( xI2CCommandQueue, &ucLED, portMAX_DELAY );
/* Only this task is allowed to touch the I2C port, so there is no need
for additional mutual exclusion. */
if( ucLED < partstMAX_LEDS )
{
/* Which bit is being manipulated? */
ucLED = 0x01 << ucLED;
/* Is the bit currently set or clear? */
if( ( ucLEDState & ucLED ) == 0U )
{
ucLEDState |= ucLED;
}
else
{
ucLEDState &= ~ucLED;
}
ucBuffer[ 0 ] = partstIO_WRITE_COMMAND;
ucBuffer[ 1 ] = ucLEDState;
xI2CMessage.sl_addr7bit = partstSLAVE_ADDRESS;
xI2CMessage.tx_data = ucBuffer ;
xI2CMessage.tx_length = sizeof( ucBuffer );
xI2CMessage.rx_data = NULL;
xI2CMessage.rx_length = 0;
xI2CMessage.retransmissions_max = 3;
I2C_MasterTransferData( LPC_I2C0, &xI2CMessage, I2C_TRANSFER_POLLING );
}
}
}
/*-----------------------------------------------------------*/

502
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/RegTest.c Normal file
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@ -0,0 +1,502 @@
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
__asm vRegTest1Task( void )
{
PRESERVE8
IMPORT ulRegTest1LoopCounter
/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
/* Fill the VFP registers with known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg1_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
reg1_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg1_error_loopf
reg1_loopf_pass
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, =ulRegTest1LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg1_loop
reg1_error_loop
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
nop
}
/*-----------------------------------------------------------*/
__asm vRegTest2Task( void )
{
PRESERVE8
IMPORT ulRegTest2LoopCounter
/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
/* Set all the VFP to known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg2_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
reg2_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
/* Increment the loop counter to indicate this test is still functioning
correctly. */
push { r0-r1 }
ldr r0, =ulRegTest2LoopCounter
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg2_loop
reg2_error_loop
/* If this line is hit then there was an error in a core register value.
This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
nop
}
/*-----------------------------------------------------------*/
__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
{
PRESERVE8
/* Clobber the auto saved registers. */
vmov d0, r0, r0
vmov d1, r0, r0
vmov d2, r0, r0
vmov d3, r0, r0
vmov d4, r0, r0
vmov d5, r0, r0
vmov d6, r0, r0
vmov d7, r0, r0
bx lr
}
/*-----------------------------------------------------------*/
__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
{
PRESERVE8
vmov r1, s0
cmp r0, r1
bne return_error
vmov r1, s1
cmp r0, r1
bne return_error
vmov r1, s2
cmp r0, r1
bne return_error
vmov r1, s3
cmp r0, r1
bne return_error
vmov r1, s4
cmp r0, r1
bne return_error
vmov r1, s5
cmp r0, r1
bne return_error
vmov r1, s6
cmp r0, r1
bne return_error
vmov r1, s7
cmp r0, r1
bne return_error
vmov r1, s8
cmp r0, r1
bne return_error
vmov r1, s9
cmp r0, r1
bne return_error
vmov r1, s10
cmp r0, r1
bne return_error
vmov r1, s11
cmp r0, r1
bne return_error
vmov r1, s12
cmp r0, r1
bne return_error
vmov r1, s13
cmp r0, r1
bne return_error
vmov r1, s14
cmp r0, r1
bne return_error
vmov r1, s15
cmp r0, r1
bne return_error
return_pass
mov r0, #1
bx lr
return_error
mov r0, #0
bx lr
}

442
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/main.c Normal file
View file

@ -0,0 +1,442 @@
/*
FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/******************************************************************************
* >>>>>> NOTE 1: <<<<<<
*
* main() can be configured to create either a very simple LED flasher demo, or
* a more comprehensive test/demo application.
*
* To create a very simple LED flasher example, set the
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant (defined below) to 1. When
* this is done, only the standard demo flash tasks are created. The standard
* demo flash example creates three tasks, each of which toggle an LED at a
* fixed but different frequency.
*
* To create a more comprehensive test and demo application, set
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0.
******************************************************************************
*
* main() creates all the demo application tasks and software timers, then starts
* the scheduler. The web documentation provides more details of the standard
* demo application tasks, which provide no particular functionality, but do
* provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" timer - The check software timer period is initially set to three
* seconds. The callback function associated with the check software timer
* checks that all the standard demo tasks, and the register check tasks, are
* not only still executing, but are executing without reporting any errors. If
* the check software timer discovers that a task has either stalled, or
* reported an error, then it changes its own execution period from the initial
* three seconds, to just 200ms. The check software timer callback function
* also toggles an LED each time it is called. This provides a visual
* indication of the system status: If the LED toggles every three seconds,
* then no issues have been discovered. If the LED toggles every 200ms, then
* an issue has been discovered with at least one task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "flop.h"
#include "integer.h"
#include "PollQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "death.h"
/* Hardware includes. */
#include "platform_config.h"
/* Priorities for the demo application tasks. */
#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
/* The LED used by the check timer. */
#define mainCHECK_LED ( 3UL )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( 0UL )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_RATE_MS constant. */
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_RATE_MS constant. */
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
/* Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 1 to create a simple demo.
Set mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY to 0 to create a much more
comprehensive test application. See the comments at the top of this file, and
the documentation page on the http://www.FreeRTOS.org web site for more
information. */
#define mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* Set up the hardware ready to run this demo.
*/
static void prvSetupHardware( void );
/*
* The check timer callback function, as described at the top of this file.
*/
static void prvCheckTimerCallback( xTimerHandle xTimer );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file.
*/
extern void vRegTest1Task( void *pvParameters );
extern void vRegTest2Task( void *pvParameters );
extern void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue );
extern unsigned long ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue );
/*
* This file can be used to create either a simple LED flasher example, or a
* comprehensive test/demo application - depending on the setting of the
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY constant defined above. If
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 1, then the following
* function will create a lot of additional tasks and a software timer. If
* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0, then the following
* function will do nothing.
*/
static void prvOptionallyCreateComprehensveTestApplication( void );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check software timer. If the variables keep
incrementing, then the register check tasks has not discovered any errors. If
a variable stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
int main(void)
{
/* Configure the hardware ready to run the test. */
prvSetupHardware();
/* Start standard demo/test application flash tasks. See the comments at
the top of this file. The LED flash tasks are always created. The other
tasks are only created if mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to
0 (at the top of this file). See the comments at the top of this file for
more information. */
vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
/* The following function will only create more tasks and timers if
mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY is set to 0 (at the top of this
file). See the comments at the top of this file for more information. */
prvOptionallyCreateComprehensveTestApplication();
/* Start the scheduler. */
vTaskStartScheduler();
/* Infinite loop */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTimerCallback( xTimerHandle xTimer )
{
static long lChangedTimerPeriodAlready = pdFALSE;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorFound = pdFALSE;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 0UL;
}
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 1UL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 2UL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 3UL;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 4UL;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 5UL;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 6UL;
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 7UL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 8UL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 0x01UL << 9UL;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorFound |= 0x01UL << 10UL;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorFound |= 0x01UL << 11UL;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
everything is ok. A faster toggle indicates an error. */
vParTestToggleLED( mainCHECK_LED );
/* Have any errors been latch in ulErrorFound? If so, shorten the
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
This will result in an increase in the rate at which mainCHECK_LED
toggles. */
if( ulErrorFound != pdFALSE )
{
if( lChangedTimerPeriodAlready == pdFALSE )
{
lChangedTimerPeriodAlready = pdTRUE;
/* This call to xTimerChangePeriod() uses a zero block time.
Functions called from inside of a timer callback function must
*never* attempt to block. */
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup system (clock, PLL and Flash configuration) */
platformInit();
/* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 );
/* Setup the LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static void prvOptionallyCreateComprehensveTestApplication( void )
{
#if ( mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY == 0 )
{
xTimerHandle xCheckTimer = NULL;
/* Start all the other standard demo/test tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
/* Most importantly, start the tasks that use the FPU. */
vStartMathTasks( mainFLOP_TASK_PRIORITY );
/* Create the register check tasks, as described at the top of this
file */
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
/* Create the software timer that performs the 'check' functionality,
as described at the top of this file. */
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
);
if( xCheckTimer != NULL )
{
xTimerStart( xCheckTimer, mainDONT_BLOCK );
}
/* This task has to be created last as it keeps account of the number of
tasks it expects to see running. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
}
#else /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */
{
/* Just to prevent compiler warnings when the configuration options are
set such that these static functions are not used. */
( void ) vRegTest1Task;
( void ) vRegTest2Task;
( void ) prvCheckTimerCallback;
( void ) prvSetupNestedFPUInterruptsTest;
}
#endif /* mainCREATE_SIMPLE_LED_FLASHER_DEMO_ONLY */
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
}
/*-----------------------------------------------------------*/

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project>
<PathAndName>.\M4\M4.uvproj</PathAndName>
<NodeIsActive>1</NodeIsActive>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
</ProjectWorkspace>

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IPC demo program based on mailbox
-----------------------------------------
- within the file platform_config.h the user needs to specify the system configuration.
The user can specifiy:
* which mailboxes are required (host, slave, or both)
* if the M0 memory has to be initialized to a specific value before download
* the usage of an optional 32-bit parameter for the mailboxes
* the availability of a callback function for the mailboxes
* the priority of the interrupt associated with the IPC communication
* the memory locations of the M0 code/data, buffers for M0 and M4, location of the mailboxes
* if the M4 shall download the M0 and start it via INITIALIZE_M0_IMAGE (YES/NO)
The linker scatter file needs to be consistent with the provided ROM/RAM addresses in case of changes.
Set it to NO if you want to debug the M0 application separately.
Set to YES means the M4 will reset, download, and release the M0. In this case, the debug connection could be lost.
For debugging, in this scenario the .ini file shall be modified, not to download the application but just to connect to the processor.
- according to the number of mailbox desired, if callbacks are enabled, the user has to provide a callback table within the Mx_usr_mbx_callbacks.c file.
In Mx_usr_mbx_callbacks.h file the mailbox numbering is defined. Within the callback table, each callback gets associated to the related mailbox number.
The order in the table is not important, since the callback function addresses are plugged-in at runtime by the IPC initialization routines.
- The mailbox table defined in ipc_buffer.c needs also to be updated accordingly to accomodate the desired number of mailboxes. There can be
- since the callbacks are executed within the ISR, their usage is meant for quick operations that need to be performed in reaction to the mailbox event
For normal application processing, message pending flags are provided and shall rather be used, to avoid increasing unnecessarily interrupt latency
- the type of logical messages for the mailboxes are defined within the Mx_ipc_msg.h file
- the application runs completely from RAM and exchanges messages between the processors, showing how to post and read from the mailboxes.

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; memory map assignment
; check with platform_config.h header
; check the ranges
; #define M4_ROM_START 0x1C000000
; #define M4_ROM_LEN 0x400000 /* 4 Mbytes */
LR_IROM1 0x1C000000 0x400000 { ; load region size_region
ER_IROM1 0x1C000000 0x400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; #define M4_RAM_START 0x10000000 /* 96 Kbytes */
; #define M4_RAM_LEN 0x18000
; this region includes just the relocated vector table
; not used by anything else
ER_RELOCIRQ 0x10000000 0xC0 {
}
RW_IRAM1 +0 (0x18000 - 0xC0) { ; RW data
.ANY (+RW +ZI)
}
; #define M4_BUF_START 0x20000000
; #define M4_BUF_LEN 0x4000
RW_IRAM_BUFFERS 0x20000000 0x4000 { ; rw buffers
}
; #define M4_MBX_START 0x20008000
; #define M4_MBX_LEN 0x2000
RW_IRAM_MBX 0x20008000 0x2000 {
}
}

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/**********************************************************************
* $Id$ lpc43xx_cgu.c 2011-06-02
*//**
* @file lpc43xx_cgu.c
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup CGU
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
#include "lpc43xx_scu.h"
#include "lpc43xx_cgu.h"
/** This define used to fix mistake when run with IAR compiler */
#ifdef __ICCARM__
#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001
#else
#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01
#endif
/*TODO List:
* SET PLL0
* UPDATE Clock from PLL0
* SetDIV uncheck value
* GetBaseStatus BASE_SAFE
* */
/* Local definition */
#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))
/* Local Variable */
const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {
-1, //CGU_CLKSRC_32KHZ_OSC,
-1, //CGU_CLKSRC_IRC,
-1, //CGU_CLKSRC_ENET_RX_CLK,
-1, //CGU_CLKSRC_ENET_TX_CLK,
-1, //CGU_CLKSRC_GP_CLKIN,
-1, //CGU_CLKSRC_TCK,
0x18, //CGU_CLKSRC_XTAL_OSC,
0x20, //CGU_CLKSRC_PLL0,
0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**
0x44, //CGU_CLKSRC_PLL1,
-1, //CGU_CLKSRC_RESERVE,
-1, //CGU_CLKSRC_RESERVE,
0x48, //CGU_CLKSRC_IDIVA,,
0x4C, //CGU_CLKSRC_IDIVB,
0x50, //CGU_CLKSRC_IDIVC,
0x54, //CGU_CLKSRC_IDIVD,
0x58, //CGU_CLKSRC_IDIVE,
0x5C, //CGU_BASE_SAFE,
0x60, //CGU_BASE_USB0,
-1, //CGU_BASE_RESERVE,
0x68, //CGU_BASE_USB1,
0x6C, //CGU_BASE_M3,
0x70, //CGU_BASE_SPIFI,
-1, //CGU_BASE_RESERVE,
0x78, //CGU_BASE_PHY_RX,
0x7C, //CGU_BASE_PHY_TX,
0x80, //CGU_BASE_APB1,
0x84, //CGU_BASE_APB3,
0x88, //CGU_BASE_LCD,
0X8C, //CGU_BASE_ENET_CSR, **REV A**
0x90, //CGU_BASE_SDIO,
0x94, //CGU_BASE_SSP0,
0x98, //CGU_BASE_SSP1,
0x9C, //CGU_BASE_UART0,
0xA0, //CGU_BASE_UART1,
0xA4, //CGU_BASE_UART2,
0xA8, //CGU_BASE_UART3,
0xAC, //CGU_BASE_CLKOUT
-1,
-1,
-1,
-1,
0xC0, //CGU_BASE_APLL
0xC4, //CGU_BASE_OUT0
0xC8 //CGU_BASE_OUT1
};
const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {
// 3 I E E G T X P P P x x D D D D D S U x U M S x P P A A L E S S S U U U U C x x x x A O O
// 2 R R T P C T L L L I I I I I A S S 3 P H H P P C N D S S R R R R O P U U
// C X X I K A 0 A 1 A B C D E F B B F RxTx1 3 D T I 0 1 0 1 2 3 L T T
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_32KHZ_OSC = 0,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IRC,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_RX_CLK,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_TX_CLK,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_GP_CLKIN,*/
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0},/*CGU_CLKSRC_TCK,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_XTAL_OSC,*/
{0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1},/*CGU_CLKSRC_PLL0,*/
{0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL0_AUDIO,*/
{0,0,0,0,0,0,0,1,1,0,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL1,*/
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
{0,0,0,0,0,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVB,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVC,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVD,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1}/*CGU_CLKSRC_IDIVE,*/
};
const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {
/* Register Clock | Peripheral Clock
| BASE | BRANCH | BASE | BRANCH */
{CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,
{CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,
{CGU_BASE_M3, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,
//// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
{CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,
{CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,
{CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,
{CGU_BASE_M3, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,
{CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,
{CGU_BASE_M3, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,
{CGU_BASE_M3, 0x1430, CGU_BASE_M3, 0x1478, 0},//CGU_PERIPHERAL_EMC,
{CGU_BASE_M3, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,
{CGU_ENTITY_NONE,0x0000, CGU_BASE_PHY_TX, 0x0000, 0},//CGU_PERIPHERAL_ETHERNET_TX
{CGU_BASE_M3, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,
{CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,
{CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,
{CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,
{CGU_BASE_M3, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,
{CGU_BASE_M3, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,
{CGU_BASE_M3, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,
{CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,
{CGU_BASE_M3, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,
{CGU_BASE_M3, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,
{CGU_BASE_M3, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,
{CGU_BASE_M3, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,
{CGU_BASE_M3, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,
{CGU_BASE_M3, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,
{CGU_BASE_M3, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,
{CGU_BASE_M3, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,
{CGU_BASE_M3, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,
{CGU_BASE_M3, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,
{CGU_BASE_M3, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,
{CGU_BASE_M3, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,
{CGU_BASE_M3, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,
{CGU_BASE_M3, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,
{CGU_BASE_M3, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,
{CGU_BASE_M3, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,
{CGU_BASE_M3, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,
{CGU_BASE_M3, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,
{CGU_BASE_M3, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,
};
uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0,12000000,0,0,0,0, 0, 480000000,0,0,0,0,0,0,0,0,0};
#define CGU_CGU_ADDR ((uint32_t)LPC_CGU)
#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))
#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))
#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))
#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))
#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))
/*********************************************************************//**
* @brief Initialize default clock for LPC4300 Eval board
* @param[in] None
* @return Initialize status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_Init(void){
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// Disable PLL1 CPU hang???
//CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);
CGU_SetPLL1(6);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
CGU_UpdateClock();
return 0;
}
/*********************************************************************//**
* @brief Configure power for individual peripheral
* @param[in] PPType peripheral type, should be:
* - CGU_PERIPHERAL_ADC0 :ADC0
* - CGU_PERIPHERAL_ADC1 :ADC1
* - CGU_PERIPHERAL_AES :AES
* - CGU_PERIPHERAL_APB1_BUS :APB1 bus
* - CGU_PERIPHERAL_APB3_BUS :APB3 bus
* - CGU_PERIPHERAL_CAN :CAN
* - CGU_PERIPHERAL_CREG :CREG
* - CGU_PERIPHERAL_DAC :DAC
* - CGU_PERIPHERAL_DMA :DMA
* - CGU_PERIPHERAL_EMC :EMC
* - CGU_PERIPHERAL_ETHERNET :ETHERNET
* - CGU_PERIPHERAL_GPIO :GPIO
* - CGU_PERIPHERAL_I2C0 :I2C0
* - CGU_PERIPHERAL_I2C1 :I2C1
* - CGU_PERIPHERAL_I2S :I2S
* - CGU_PERIPHERAL_LCD :LCD
* - CGU_PERIPHERAL_M3CORE :M3 core
* - CGU_PERIPHERAL_M3_BUS :M3 bus
* - CGU_PERIPHERAL_MOTOCON :Motor control
* - CGU_PERIPHERAL_QEI :QEI
* - CGU_PERIPHERAL_RITIMER :RIT timer
* - CGU_PERIPHERAL_SCT :SCT
* - CGU_PERIPHERAL_SCU :SCU
* - CGU_PERIPHERAL_SDIO :SDIO
* - CGU_PERIPHERAL_SPIFI :SPIFI
* - CGU_PERIPHERAL_SSP0 :SSP0
* - CGU_PERIPHERAL_SSP1 :SSP1
* - CGU_PERIPHERAL_TIMER0 :TIMER0
* - CGU_PERIPHERAL_TIMER1 :TIMER1
* - CGU_PERIPHERAL_TIMER2 :TIMER2
* - CGU_PERIPHERAL_TIMER3 :TIMER3
* - CGU_PERIPHERAL_UART0 :UART0
* - CGU_PERIPHERAL_UART1 :UART1
* - CGU_PERIPHERAL_UART2 :UART2
* - CGU_PERIPHERAL_UART3 :UART3
* - CGU_PERIPHERAL_USB0 :USB0
* - CGU_PERIPHERAL_USB1 :USB1
* - CGU_PERIPHERAL_WWDT :WWDT
* @param[in] en status, should be:
* - ENABLE: Enable power
* - DISABLE: Disable power
* @return Configure status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en){
if(PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0)
return CGU_ERROR_INVALID_PARAM;
if(en == DISABLE){/* Going to disable clock */
/*Get Reg branch status */
if(CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0 &&
CGU_REG_BRANCH_STATUS(PPType) & 1){
CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
while(CGU_REG_BRANCH_STATUS(PPType) & 1);
}
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) &&
CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0){
/* Disable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity,0);
}
/* Same for Peripheral */
if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
while(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);
}
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity!=CGU_ENTITY_NONE) &&
CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0){
/* Disable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity,0);
}
}else{
/* enable */
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK){
/* Enable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);
}
/*Get Reg branch status */
if((CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
while(!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
}
/* Same for Peripheral */
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
(CGU_PER_BASE_CTRL(PPType) & 1)){
/* Enable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);
}
/*Get Reg branch status */
if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
while(!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
}
}
if(CGU_PERIPHERAL_Info[PPType].next){
return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);
}
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Get peripheral clock frequency
* @param[in] Clock Peripheral type, should be:
* - CGU_PERIPHERAL_ADC0 :ADC0
* - CGU_PERIPHERAL_ADC1 :ADC1
* - CGU_PERIPHERAL_AES :AES
* - CGU_PERIPHERAL_APB1_BUS :APB1 bus
* - CGU_PERIPHERAL_APB3_BUS :APB3 bus
* - CGU_PERIPHERAL_CAN :CAN
* - CGU_PERIPHERAL_CREG :CREG
* - CGU_PERIPHERAL_DAC :DAC
* - CGU_PERIPHERAL_DMA :DMA
* - CGU_PERIPHERAL_EMC :EMC
* - CGU_PERIPHERAL_ETHERNET :ETHERNET
* - CGU_PERIPHERAL_GPIO :GPIO
* - CGU_PERIPHERAL_I2C0 :I2C0
* - CGU_PERIPHERAL_I2C1 :I2C1
* - CGU_PERIPHERAL_I2S :I2S
* - CGU_PERIPHERAL_LCD :LCD
* - CGU_PERIPHERAL_M3CORE :M3 core
* - CGU_PERIPHERAL_M3_BUS :M3 bus
* - CGU_PERIPHERAL_MOTOCON :Motor control
* - CGU_PERIPHERAL_QEI :QEI
* - CGU_PERIPHERAL_RITIMER :RIT timer
* - CGU_PERIPHERAL_SCT :SCT
* - CGU_PERIPHERAL_SCU :SCU
* - CGU_PERIPHERAL_SDIO :SDIO
* - CGU_PERIPHERAL_SPIFI :SPIFI
* - CGU_PERIPHERAL_SSP0 :SSP0
* - CGU_PERIPHERAL_SSP1 :SSP1
* - CGU_PERIPHERAL_TIMER0 :TIMER0
* - CGU_PERIPHERAL_TIMER1 :TIMER1
* - CGU_PERIPHERAL_TIMER2 :TIMER2
* - CGU_PERIPHERAL_TIMER3 :TIMER3
* - CGU_PERIPHERAL_UART0 :UART0
* - CGU_PERIPHERAL_UART1 :UART1
* - CGU_PERIPHERAL_UART2 :UART2
* - CGU_PERIPHERAL_UART3 :UART3
* - CGU_PERIPHERAL_USB0 :USB0
* - CGU_PERIPHERAL_USB1 :USB1
* - CGU_PERIPHERAL_WWDT :WWDT
* @return Return frequently value
**********************************************************************/
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock){
uint32_t ClkSrc;
if(Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0)
return CGU_ERROR_INVALID_PARAM;
if(CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE){
/* Get Base Clock Source */
ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
/* GetBase Status*/
if(CGU_PER_BASE_CTRL(Clock) & 1)
return 0;
/* check Branch if it is enabled */
if((CGU_PERIPHERAL_Info[Clock].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;
}else{
if(CGU_REG_BASE_CTRL(Clock) & 1) return 0;
ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
/* check Branch if it is enabled */
if((CGU_PERIPHERAL_Info[Clock].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;
}
return CGU_ClockSourceFrequency[ClkSrc];
}
/*********************************************************************//**
* @brief Update clock
* @param[in] None
* @return None
**********************************************************************/
void CGU_UpdateClock(void){
uint32_t ClkSrc;
uint32_t div;
uint32_t divisor;
int32_t RegOffset;
/* 32OSC */
if(ISBITSET(LPC_CREG->CREG0,1) && ISBITCLR(LPC_CREG->CREG0,3))
CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;
else
CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;
/*PLL0*/
/* PLL1 */
if(ISBITCLR(LPC_CGU->PLL1_CTRL,1) /* Enabled */
&& (LPC_CGU->PLL1_STAT&1)){ /* Locked? */
ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *
(((LPC_CGU->PLL1_CTRL>>16)&0xFF)+1);
}else
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;
/* DIV */
for(div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++){
RegOffset = CGU_Entity_ControlReg_Offset[div];
if(ISBITCLR(CGU_ADDRESS32(LPC_CGU,RegOffset),1)){
ClkSrc = (CGU_ADDRESS32(LPC_CGU,RegOffset) & CGU_CTRL_SRC_MASK) >> 24;
divisor = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>2) & 0xFF;
divisor ++;
CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;
}else
CGU_ClockSourceFrequency[div] = 0;
}
}
/*********************************************************************//**
* @brief Set XTAL oscillator value
* @param[in] ClockFrequency XTAL Frequency value
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range
**********************************************************************/
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency){
if(ClockFrequency < 15000000){
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2);
}else if(ClockFrequency < 25000000){
LPC_CGU->XTAL_OSC_CTRL |= (1<<2);
}else
return CGU_ERROR_FREQ_OUTOF_RANGE;
CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Set clock divider
* @param[in] SelectDivider Clock source, should be:
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* @param[in] divisor Divisor value, should be: 0..255
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_INVALID_ENTITY: Invalid entity
**********************************************************************/
/* divisor number must >=1*/
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor){
int32_t RegOffset;
uint32_t tempReg;
if(SelectDivider>=CGU_CLKSRC_IDIVA && SelectDivider<=CGU_CLKSRC_IDIVE){
RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);
tempReg &= ~(0xFF<<2);
tempReg |= ((divisor-1)&0xFF)<<2;
CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;
return CGU_ERROR_SUCCESS;
}
return CGU_ERROR_INVALID_ENTITY;
}
/*********************************************************************//**
* @brief Enable clock entity
* @param[in] ClockEntity Clock entity, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
* - CGU_CLKSRC_IRC :IRC clock
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @param[in] en status, should be:
* - ENABLE: Enable power
* - DISABLE: Disable power
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_INVALID_ENTITY: Invalid entity
**********************************************************************/
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en){
int32_t RegOffset;
int32_t i;
if(ClockEntity == CGU_CLKSRC_32KHZ_OSC){
if(en){
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2));
LPC_CREG->CREG0 |= (1<<1)|(1<<0);
}else{
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0));
LPC_CREG->CREG0 |= (1<<3);
}
for(i = 0;i<1000000;i++);
}else if(ClockEntity == CGU_CLKSRC_ENET_RX_CLK){
scu_pinmux(0xC ,0 , MD_PLN, FUNC3);
}else if(ClockEntity == CGU_CLKSRC_ENET_TX_CLK){
scu_pinmux(0x1 ,19 , MD_PLN, FUNC0);
}else if(ClockEntity == CGU_CLKSRC_GP_CLKIN){
}else if(ClockEntity == CGU_CLKSRC_TCK){
}else if(ClockEntity == CGU_CLKSRC_XTAL_OSC){
if(!en)
LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;
else
LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;
/*Delay for stable clock*/
for(i = 0;i<1000000;i++);
}else{
RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
if(!en){
CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) |= CGU_CTRL_EN_MASK;
}else{
CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) &= ~CGU_CTRL_EN_MASK;
/*if PLL is selected check if it is locked */
if(ClockEntity == CGU_CLKSRC_PLL0){
while((LPC_CGU->PLL0USB_STAT&1) == 0x0);
}
if(ClockEntity == CGU_CLKSRC_PLL1){
while((LPC_CGU->PLL1_STAT&1) == 0x0);
/*post check lock status */
if(!(LPC_CGU->PLL1_STAT&1))
while(1);
}
}
}
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Connect entity clock source
* @param[in] ClockSource Clock source, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
* - CGU_CLKSRC_IRC :IRC clock
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* @param[in] ClockEntity Clock entity, should be:
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together
* - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error
* - CGU_ERROR_INVALID_ENTITY: Invalid entity error
**********************************************************************/
/* Connect one entity into clock source */
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity){
int32_t RegOffset;
uint32_t tempReg;
if(ClockSource > CGU_CLKSRC_IDIVE)
return CGU_ERROR_INVALID_CLOCK_SOURCE;
if(ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT){
if(CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]){
RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];
if(RegOffset != -1){
if(ClockEntity<=CGU_CLKSRC_IDIVE &&
ClockEntity>=CGU_CLKSRC_PLL0)
{
//RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;
if(((CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)& 0xF) == ClockEntity)
return CGU_ERROR_CONNECT_TOGETHER;
}
}
RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);
tempReg &= ~CGU_CTRL_SRC_MASK;
tempReg |= ClockSource<<24 | CGU_CTRL_AUTOBLOCK_MASK;
CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;
return CGU_ERROR_SUCCESS;
}else
return CGU_ERROR_INVALID_CLOCK_SOURCE;
}else
return CGU_ERROR_INVALID_ENTITY;
}
/*********************************************************************//**
* @brief Get current USB PLL clock from XTAL
* @param[in] None
* @return Returned clock value
**********************************************************************/
uint32_t CGU_SetPLL0(void){
// Setup PLL550 to generate 480MHz from 12 MHz crystal
LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL
// P N
LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);
// SELP SELI SELR MDEC
LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);
LPC_CGU->PLL0USB_CTRL =(CGU_CLKSRC_XTAL_OSC<<24) | (0x3<<2) | (1<<4);
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Setting PLL1
* @param[in] mult Multiple value
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_INVALID_PARAM: Invalid parameter error
**********************************************************************/
uint32_t CGU_SetPLL1(uint32_t mult){
uint32_t msel=0, nsel=0, psel=0, pval=1;
uint32_t freq;
uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;
freq = CGU_ClockSourceFrequency[ClkSrc];
freq *= mult;
msel = mult-1;
LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |
CGU_PLL1_BYPASS_MASK |
CGU_PLL1_DIRECT_MASK |
(0x03<<8) | (0xFF<<16) | (0x03<<12));
if(freq<156000000){
//psel is encoded such that 0=1, 1=2, 2=4, 3=8
while(2*(pval)*freq < 156000000) {
psel++;
pval*=2;
}
// if(2*(pval)*freq > 320000000) {
// //THIS IS OUT OF RANGE!!!
// //HOW DO WE ASSERT IN SAMPLE CODE?
// //__breakpoint(0);
// return CGU_ERROR_INVALID_PARAM;
// }
LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) | CGU_PLL1_FBSEL_MASK;
}else if(freq<320000000){
LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) |CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;
}else
return CGU_ERROR_INVALID_PARAM;
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Get current base status
* @param[in] Base Base type, should be:
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* @return Always return 0
**********************************************************************/
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base){
switch(Base){
/*CCU1*/
case CGU_BASE_APB3:
return LPC_CCU1->BASE_STAT & 1;
case CGU_BASE_APB1:
return (LPC_CCU1->BASE_STAT>>1) & 1;
case CGU_BASE_SPIFI:
return (LPC_CCU1->BASE_STAT>>2) & 1;
case CGU_BASE_M3:
return (LPC_CCU1->BASE_STAT>>3) & 1;
case CGU_BASE_USB0:
return (LPC_CCU1->BASE_STAT>>7) & 1;
case CGU_BASE_USB1:
return (LPC_CCU1->BASE_STAT>>8) & 1;
/*CCU2*/
case CGU_BASE_UART3:
return (LPC_CCU2->BASE_STAT>>1) & 1;
case CGU_BASE_UART2:
return (LPC_CCU2->BASE_STAT>>2) & 1;
case CGU_BASE_UART1:
return (LPC_CCU2->BASE_STAT>>3) & 1;
case CGU_BASE_UART0:
return (LPC_CCU2->BASE_STAT>>4) & 1;
case CGU_BASE_SSP1:
return (LPC_CCU2->BASE_STAT>>5) & 1;
case CGU_BASE_SSP0:
return (LPC_CCU2->BASE_STAT>>6) & 1;
case CGU_BASE_SDIO:
return (LPC_CCU2->BASE_STAT>>7) & 1;
/*BASE SAFE is used by WWDT and RGU*/
case CGU_BASE_SAFE:
break;
default:
break;
}
return 0;
}
/*********************************************************************//**
* @brief Compare one source clock to IRC clock
* @param[in] Clock Clock entity that will be compared to IRC, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @param[in] m Multiple value pointer
* @param[in] d Divider value pointer
* @return Compare status, could be:
* - (-1): fail
* - 0: successful
* @note Formula used to compare:
* FClock = F_IRC* m / d
**********************************************************************/
int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d){
uint32_t n,c,temp;
int i;
/* Maximum allow RCOUNT number */
c= 511;
/* Check Source Clock Freq is larger or smaller */
LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;
while(LPC_CGU->FREQ_MON & (1 <<23));
for(i=0;i<10000;i++);
temp = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;
if(temp == 0) /* too low F < 12000000/511*/
return -1;
if(temp > 511){ /* larger */
c = 511 - (LPC_CGU->FREQ_MON&0x1FF);
}else{
do{
c--;
LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;
while(LPC_CGU->FREQ_MON & (1 <<23));
for(i=0;i<10000;i++);
n = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;
}while(n==temp);
c++;
}
*m = temp;
*d = c;
return 0;
}
/*********************************************************************//**
* @brief Compare one source clock to another source clock
* @param[in] Clock Clock entity that will be compared to second source, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @param[in] CompareToClock Clock source that to be compared to first source, should be different
* to first source.
* @param[in] m Multiple value pointer
* @param[in] d Divider value pointer
* @return Compare status, could be:
* - (-1): fail
* - 0: successful
* @note Formula used to compare:
* FClock = m*FCompareToClock/d
**********************************************************************/
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d){
uint32_t m1,m2,d1,d2;
/* Check Parameter */
if((Clock>CGU_CLKSRC_IDIVE) || (CompareToClock>CGU_CLKSRC_IDIVE))
return CGU_ERROR_INVALID_PARAM;
/* Check for Clock Enable - Not yet implement
* The Comparator will hang if Clock has not been set*/
CGU_FrequencyMonitor(Clock, &m1, &d1);
CGU_FrequencyMonitor(CompareToClock, &m2, &d2);
*m= m1*d2;
*d= d1*m2;
return 0;
}
/**
* @}
*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc43xx_cgu.h 2011-06-02
*//**
* @file llpc43xx_cgu.h
* @brief Contains all macro definitions and function prototypes
* support for Clock Generation and Clock Control firmware
* library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CGU CGU (Clock Generation Unit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_CGU_H_
#define lpc43xx_CGU_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros -------------------------------------------------------------- */
/** @defgroup CGU_Private_Macros CGU Private Macros
* @{
*/
/** Branch clocks from CGU_BASE_SAFE */
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
/** Check bit at specific position is clear or not */
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
/** Check bit at specific position is set or not */
#define ISBITSET(x,bit) (x&(1<<bit))
/** Set mask */
#define ISMASKSET(x,mask) (x&mask)
/** CGU number of clock source */
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
/*********************************************************************//**
* Macro defines for CGU control mask bit definitions
**********************************************************************/
/** CGU control enable mask bit */
#define CGU_CTRL_EN_MASK 1
/** CGU control clock-source mask bit */
#define CGU_CTRL_SRC_MASK (0xF<<24)
/** CGU control auto block mask bit */
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
/*********************************************************************//**
* Macro defines for CGU PLL1 mask bit definitions
**********************************************************************/
/** CGU PLL1 feedback select mask bit */
#define CGU_PLL1_FBSEL_MASK (1<<6)
/** CGU PLL1 Input clock bypass control mask bit */
#define CGU_PLL1_BYPASS_MASK (1<<1)
/** CGU PLL1 direct CCO output mask bit */
#define CGU_PLL1_DIRECT_MASK (1<<7)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CGU_Public_Types CGU Public Types
* @{
*/
/*********************************************************************//**
* @brief CGU enumeration
**********************************************************************/
/*
* @brief CGU clock source enumerate definition
*/
typedef enum {
/* Clock Source */
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
CGU_CLKSRC_TCK, /**< TCK clock source */
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
CGU_CLKSRC_PLL0_AUDIO,
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
/* Base */
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
CGU_BASE_USB0, /**< USB0 base clock */
CGU_BASE_USB1 = CGU_BASE_USB0 + 2, /**< USB1 base clock */
CGU_BASE_M3, /**< ARM Cortex-M3 Core base clock */
CGU_BASE_SPIFI, /**< SPIFI base clock */
//CGU_BASE_SPI,
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
CGU_BASE_LCD, /**< LCD base clock */
CGU_BASE_ENET_CSR,
CGU_BASE_SDIO, /**< SDIO base clock */
CGU_BASE_SSP0, /**< SSP0 base clock */
CGU_BASE_SSP1, /**< SSP1 base clock */
CGU_BASE_UART0, /**< UART0 base clock */
CGU_BASE_UART1, /**< UART1 base clock */
CGU_BASE_UART2, /**< UART2 base clock */
CGU_BASE_UART3, /**< UART3 base clock */
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
CGU_BASE_OUT0,
CGU_BASE_OUT1,
CGU_ENTITY_NUM /**< Number or clock source entity */
} CGU_ENTITY_T;
/*
* @brief CGU PPL0 mode enumerate definition
*/
typedef enum {
CGU_PLL0_MODE_1d = 0,
CGU_PLL0_MODE_1c,
CGU_PLL0_MODE_1b,
CGU_PLL0_MODE_1a
}CGU_PLL0_MODE;
/*
* @brief CGU peripheral enumerate definition
*/
typedef enum {
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
CGU_PERIPHERAL_ADC1, /**< ADC1 */
CGU_PERIPHERAL_AES, /**< AES */
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
CGU_PERIPHERAL_CAN, /**< CAN */
CGU_PERIPHERAL_CREG, /**< CREG */
CGU_PERIPHERAL_DAC, /**< DAC */
CGU_PERIPHERAL_DMA, /**< DMA */
CGU_PERIPHERAL_EMC, /**< EMC */
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
CGU_PERIPHERAL_GPIO, /**< GPIO */
CGU_PERIPHERAL_I2C0, /**< I2C0 */
CGU_PERIPHERAL_I2C1, /**< I2C1 */
CGU_PERIPHERAL_I2S, /**< I2S */
CGU_PERIPHERAL_LCD, /**< LCD */
CGU_PERIPHERAL_M3CORE, /**< ARM Cortex-M3 Core */
CGU_PERIPHERAL_M3_BUS, /**< ARM Cortex-M3 Bus */
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
CGU_PERIPHERAL_QEI, /**< QEI */
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
CGU_PERIPHERAL_SCT, /**< SCT */
CGU_PERIPHERAL_SCU, /**< SCU */
CGU_PERIPHERAL_SDIO, /**< SDIO */
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
CGU_PERIPHERAL_SSP0, /**< SSP0 */
CGU_PERIPHERAL_SSP1, /**< SSP1 */
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
CGU_PERIPHERAL_UART0, /**< UART0 */
CGU_PERIPHERAL_UART1, /**< UART1 */
CGU_PERIPHERAL_UART2, /**< UART2 */
CGU_PERIPHERAL_UART3, /**< UART3 */
CGU_PERIPHERAL_USB0, /**< USB0 */
CGU_PERIPHERAL_USB1, /**< USB1 */
CGU_PERIPHERAL_WWDT, /**< WWDT */
CGU_PERIPHERAL_NUM
} CGU_PERIPHERAL_T;
/**
* @brief CGU error status enumerate definition
*/
typedef enum {
CGU_ERROR_SUCCESS = 0,
CGU_ERROR_CONNECT_TOGETHER,
CGU_ERROR_INVALID_ENTITY,
CGU_ERROR_INVALID_CLOCK_SOURCE,
CGU_ERROR_INVALID_PARAM,
CGU_ERROR_FREQ_OUTOF_RANGE
} CGU_ERROR;
/********************************************************************//**
* @brief CGU structure definitions
**********************************************************************/
/*
* @brief CGU peripheral clock structure
*/
typedef struct {
uint8_t RegBaseEntity; /**< Base register address */
uint16_t RegBranchOffset; /**< Branch register offset */
uint8_t PerBaseEntity; /**< Base peripheral address */
uint16_t PerBranchOffset; /**< Base peripheral offset */
uint8_t next; /**< Pointer to next structure */
} CGU_PERIPHERAL_S;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CGU_Public_Functions CGU Public Functions
* @{
*/
/** Clock generate initialize/de-initialize */
uint32_t CGU_Init(void);
uint32_t CGU_DeInit(void);
/** Clock Generator and Clock Control */
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
/** Clock Source and Base Clock operation */
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
uint32_t CGU_SetPLL0(void);
uint32_t CGU_SetPLL1(uint32_t mult);
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
void CGU_UpdateClock(void);
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_CGU_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc43xx_i2c.h 2011-06-02
*//**
* @file lpc43xx_i2c.h
* @brief Contains all macro definitions and function prototypes
* support for I2C firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2C I2C (Inter-Integrated Circuit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_I2C_H_
#define lpc43xx_I2C_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc43xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2C_Private_Macros I2C Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*******************************************************************//**
* I2C Control Set register description
*********************************************************************/
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
/*******************************************************************//**
* I2C Control Clear register description
*********************************************************************/
/** Assert acknowledge Clear bit */
#define I2C_I2CONCLR_AAC ((1<<2))
/** I2C interrupt Clear bit */
#define I2C_I2CONCLR_SIC ((1<<3))
/** START flag Clear bit */
#define I2C_I2CONCLR_STAC ((1<<5))
/** I2C interface Disable bit */
#define I2C_I2CONCLR_I2ENC ((1<<6))
/********************************************************************//**
* I2C Status Code definition (I2C Status register)
*********************************************************************/
/* Return Code in I2C status register */
#define I2C_STAT_CODE_BITMASK ((0xF8))
/* I2C return status code definitions ----------------------------- */
/** No relevant information */
#define I2C_I2STAT_NO_INF ((0xF8))
/* Master transmit mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_TX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))
/** SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
/** SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
/** Arbitration lost in SLA+R/W or Data bytes */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
/* Master receive mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_RX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))
/** Arbitration lost */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
/** SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
/** SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
/** Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
/** Data has been received, NACK has been return */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
/* Slave receive mode -------------------------------------------- */
/** Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
/** Own SLA+W has been received, ACK returned */
//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
/** General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
/** General call address has been received, ACK has been returned */
//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
/** Previously addressed with own SLV address;
* Data has been received, ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
/** Previously addressed with own SLA;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
/** Previously addressed with General Call;
* Data has been received and ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
/** Previously addressed with General Call;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
/** A STOP condition or repeated START condition has
* been received while still addressed as SLV/REC
* (Slave Receive) or SLV/TRX (Slave Transmit) */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
/** Slave transmit mode */
/** Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
/** Own SLA+R has been received, ACK has been returned */
//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
/** Last data byte in I2DAT has been transmitted (AA = 0);
ACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
/** Time out in case of using I2C slave mode */
#define I2C_SLAVE_TIME_OUT 0x10000UL
/********************************************************************//**
* I2C Data register definition
*********************************************************************/
/** Mask for I2DAT register*/
#define I2C_I2DAT_BITMASK ((0xFF))
/** Idle data value will be send out in slave mode in case of the actual
* expecting data requested from the master is greater than its sending data
* length that can be supported */
#define I2C_I2DAT_IDLE_CHAR (0xFF)
/********************************************************************//**
* I2C Monitor mode control register description
*********************************************************************/
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/********************************************************************//**
* I2C Data buffer register description
*********************************************************************/
/** I2C Data buffer register bit mask */
#define I2DATA_BUFFER_BITMASK ((0xFF))
/********************************************************************//**
* I2C Slave Address registers definition
*********************************************************************/
/** General Call enable bit */
#define I2C_I2ADR_GC ((1<<0))
/** I2C Slave Address registers bit mask */
#define I2C_I2ADR_BITMASK ((0xFF))
/********************************************************************//**
* I2C Mask Register definition
*********************************************************************/
/** I2C Mask Register mask field */
#define I2C_I2MASK_MASK(n) ((n&0xFE))
/********************************************************************//**
* I2C SCL HIGH duty cycle Register definition
*********************************************************************/
/** I2C SCL HIGH duty cycle Register bit mask */
#define I2C_I2SCLH_BITMASK ((0xFFFF))
/********************************************************************//**
* I2C SCL LOW duty cycle Register definition
*********************************************************************/
/** I2C SCL LOW duty cycle Register bit mask */
#define I2C_I2SCLL_BITMASK ((0xFFFF))
/* I2C status values */
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
/*********************************************************************//**
* I2C monitor control configuration defines
**********************************************************************/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macros check I2C slave address */
#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
/** Macro to determine if it is valid SSP port number */
#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
/* Macros check I2C monitor configuration type */
#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2C_Public_Types I2C Public Types
* @{
*/
/**
* @brief I2C Own slave address setting structure
*/
typedef struct {
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
should be in range from 0..3
*/
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
when I2C control being in Slave mode, should be:
- ENABLE: Enable General Call function.
- DISABLE: Disable General Call function.
*/
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
which is set to '1' will cause an automatic compare on
the corresponding bit of the received address when it
is compared to the SlaveAddr_7bit value associated with this
mask register. In other words, bits in SlaveAddr_7bit value
which are masked are not taken into account in determining
an address match
*/
} I2C_OWNSLAVEADDR_CFG_Type;
/**
* @brief Master transfer setup data structure definitions
*/
typedef struct
{
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
is not used*/
uint32_t tx_count; /**< Current Transmit data counter */
uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is
not used */
uint32_t rx_count; /**< Current Receive data counter */
uint32_t retransmissions_max; /**< Max Re-Transmission value */
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to Call back function when transmission complete
used in interrupt transfer mode */
} I2C_M_SETUP_Type;
/**
* @brief Slave transfer setup data structure definitions
*/
typedef struct
{
uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */
uint32_t tx_count; /**< Current transmit data counter */
uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */
uint32_t rx_count; /**< Current receive data counter */
uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to call-back function when transmission complete
used by interrupt transfer mode */
} I2C_S_SETUP_Type;
/**
* @brief Transfer option type definitions
*/
typedef enum {
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
} I2C_TRANSFER_OPT_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2C_Public_Functions I2C Public Functions
* @{
*/
/* I2C Init/DeInit functions ---------- */
void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
/* I2C transfer data functions -------- */
Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
/* I2C Monitor functions ---------------*/
void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
/* I2C Interrupt handler functions ------*/
void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* lpc43xx_I2C_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc43xx_libcfg_default.h 2011-06-02
*//**
* @file lpc43xx_libcfg_default.h
* @brief Default Library configuration header file
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Library Configuration group ----------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef lpc43xx_LIBCFG_DEFAULT_H_
#define lpc43xx_LIBCFG_DEFAULT_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
* @{
*/
/************************** DEBUG MODE DEFINITIONS *********************************/
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
the "CHECK_PARAM" macro in the FW library code */
//#define DEBUG
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
/* Comment the line below to disable the specific peripheral inclusion */
/* GPIO ------------------------------- */
#define _GPIO
/* EXTI ------------------------------- */
#define _EXTI
/* UART ------------------------------- */
#define _UART
#define _UART0
#define _UART1
#define _UART2
#define _UART3
/* SPI ------------------------------- */
#define _SPI
/* SYSTICK --------------------------- */
#define _SYSTICK
/* SSP ------------------------------- */
#define _SSP
#define _SSP0
#define _SSP1
/* I2C ------------------------------- */
#define _I2C
#define _I2C0
#define _I2C1
#define _I2C2
/* TIMER ------------------------------- */
#define _TIM
/* WWDT ------------------------------- */
#define _WWDT
/* GPDMA ------------------------------- */
#define _GPDMA
/* DAC ------------------------------- */
#define _DAC
/* DAC ------------------------------- */
#define _ADC
/* PWM ------------------------------- */
#define _PWM
#define _PWM1
/* RTC ------------------------------- */
#define _RTC
/* I2S ------------------------------- */
#define _I2S
/* USB device ------------------------------- */
#define _USBDEV
#define _USB_DMA
/* QEI ------------------------------- */
#define _QEI
/* MCPWM ------------------------------- */
#define _MCPWM
/* CAN--------------------------------*/
#define _C_CAN
/* RIT ------------------------------- */
#define _RIT
/* EMAC ------------------------------ */
#define _EMAC
/* SCT ------------------------------ */
#define _SCT
/* LCD ------------------------------ */
#define _LCD
/* ATIMER ------------------------------ */
#define _ATIMER
/* RGU ------------------------------ */
#define _RGU
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
#ifdef DEBUG
/*******************************************************************************
* @brief The CHECK_PARAM macro is used for function's parameters check.
* It is used only if the library is compiled in DEBUG mode.
* @param[in] expr - If expr is false, it calls check_failed() function
* which reports the name of the source file and the source
* line number of the call that failed.
* - If expr is true, it returns no value.
* @return None
*******************************************************************************/
#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
#else
#define CHECK_PARAM(expr)
#endif /* DEBUG */
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
* @{
*/
#ifdef DEBUG
void check_failed(uint8_t *file, uint32_t line);
#endif
/**
* @}
*/
#endif /* lpc43xx_LIBCFG_DEFAULT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc43xx_scu.h 2011-06-02
*//**
* @file lpc43xx_scu.h
* @brief Contains all macro definitions and function prototypes
* support for SCU firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SCU SCU (System Control Unit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __SCU_H
#define __SCU_H
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup SCT_Private_Macros SCT Private Macros
* @{
*/
/** Port offset definition */
#define PORT_OFFSET 0x80
/** Pin offset definition */
#define PIN_OFFSET 0x04
/* Pin modes */
#define MD_PUP (0x0<<3)
#define MD_BUK (0x1<<3)
#define MD_PLN (0x2<<3)
#define MD_PDN (0x3<<3)
#define MD_EHS (0x1<<5)
#define MD_EZI (0x1<<6)
#define MD_ZI (0x1<<7)
#define MD_EHD0 (0x1<<8)
#define MD_EHD1 (0x1<<8)
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
// 0xF0
/* Pin function */
#define FUNC0 0x0 /** Function 0 */
#define FUNC1 0x1 /** Function 1 */
#define FUNC2 0x2 /** Function 2 */
#define FUNC3 0x3 /** Function 3 */
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SCU_Public_Functions SCU Public Functions
* @{
*/
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* end __SCU_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_types.h 2011-06-02
*//**
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Type group ----------------------------------------------------------- */
/** @defgroup LPC_Types LPC_Types
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC_TYPES_H
#define LPC_TYPES_H
/* Includes ------------------------------------------------------------------- */
#include <stdint.h>
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum
{
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_Type;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t(*PFI)();
/**
* @}
*/
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1<<(n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f,v) ((v)<<(f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void*) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility ------------------------------------------ */
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/** SMA type for character type */
typedef char CHAR;
/** SMA type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** SMA type for 8 bit signed value */
typedef int8_t INT_8;
/** SMA type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** SMA type for 16 bit signed value */
typedef int16_t INT_16;
/** SMA type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** SMA type for 32 bit signed value */
typedef int32_t INT_32;
/** SMA type for 64 bit signed value */
typedef int64_t INT_64;
/** SMA type for 64 bit unsigned value */
typedef uint64_t UNS_64;
/** 32 bit boolean type */
typedef Bool BOOL_32;
/** 16 bit boolean type */
typedef Bool BOOL_16;
/** 8 bit boolean type */
typedef Bool BOOL_8;
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
/**
* @}
*/
#endif /* LPC_TYPES_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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#ifndef __PLATFORM_CHECK_H
#define __PLATFORM_CHECK_H
#warning "************ PLATFORM CONFIG ************"
/* this is used to check the build platform */
#if (PLATFORM == NXP_VALIDATION_BOARD)
#warning "*** Building for NXP VALIDATION BOARD ***"
#elif (PLATFORM == HITEX_A2_BOARD)
#warning "Building for HITEX LPC4350EVA-2 platform"
#else
#error "Platform not supported, check platform_config.h"
#endif
/* this is to ensure memory ranges are defined */
#ifndef M4_ROM_START
#error "M4_ROM_START not defined, check platform_config.h"
#endif
#ifndef M4_ROM_LEN
#error "M4_ROM_LEN not defined, check platform_config.h"
#endif
#ifndef M4_RAM_START
#error "M4_RAM_START not defined, check platform_config.h"
#endif
#ifndef M4_RAM_LEN
#error "M4_RAM_LEN not defined, check platform_config.h"
#endif
#ifndef M0_ROM_START
#error "M0_ROM_START not defined, check platform_config.h"
#endif
#ifndef M0_ROM_LEN
#error "M0_ROM_LEN not defined, check platform_config.h"
#endif
#ifndef M0_RAM_START
#error "M0_RAM_START not defined, check platform_config.h"
#endif
#ifndef M0_RAM_LEN
#error "M0_RAM_LEN not defined, check platform_config.h"
#endif
/* feedback for mailboxes usage */
/* configuration checks for M0 */
#ifdef CORE_M4
#if (USE_M4_MAILBOX == YES)
#warning "*** M4 mailbox: YES ***"
#if (USE_MAILBOX_PARAMETER == YES)
#warning "*** M4 mailbox parameter: YES ***"
#elif (USE_MAILBOX_PARAMETER == NO)
#warning "*** M4 mailbox parameter: NO ***"
#else
#error "*** Specify if M4 mailbox parameter is required (YES/NO) ***"
#endif
#if (USE_MAILBOX_CALLBACK == YES)
#warning "*** M4 mailbox callback: YES ***"
#elif (USE_MAILBOX_CALLBACK == NO)
#warning "*** M4 mailbox callback: NO ***"
#else
#error "*** Specify if M4 mailbox callback is required (YES/NO) ***"
#endif
#elif (USE_M4_MAILBOX == NO)
#warning "*** M4 mailbox: NO ***"
#else
#error "*** Specify if M4 mailbox is required (YES/NO) ***"
#endif
#if (INITIALIZE_M0_IMAGE == YES)
#warning "*** M4 should download the M0 image: YES ***"
#elif (INITIALIZE_M0_IMAGE == NO)
#warning "*** M4 should download the M0 image: NO ***"
#else
#error "*** Specify if M4 should initialize the M0 image (YES/NO) ***"
#endif
/* check the build rules */
#if (USE_EXT_FLASH == YES)
#warning "*** Building with external flash support: YES ***"
#elif (USE_EXT_FLASH == NO)
#warning "*** Building with external flash support: NO ***"
#endif
#if (USE_EXT_STATIC_MEM == YES)
#warning "*** Building with external static memory support: YES ***"
#elif (USE_EXT_STATIC_MEM == NO)
#warning "*** Building with external static memory support: NO ***"
#endif
#if (USE_EXT_DYNAMIC_MEM == YES)
#warning "*** Building for external dynamic memory support: YES ***"
#elif (USE_EXT_DYNAMIC_MEM == NO)
#warning "*** Building for external dynamic memory support: NO ***"
#endif
#endif /* CORE_M4 */
/* configuration checks for M0 */
#ifdef CORE_M0
#if (USE_M0_MAILBOX == YES)
#warning "*** M0 mailbox: YES ***"
#if (USE_MAILBOX_PARAMETER == YES)
#warning "*** M0 mailbox parameter: YES ***"
#elif (USE_MAILBOX_PARAMETER == NO)
#warning "*** M0 mailbox parameter: NO ***"
#else
#error "*** Specify if M0 mailbox parameter is required (YES/NO) ***"
#endif
#if (USE_MAILBOX_CALLBACK == YES)
#warning "*** M0 mailbox callback: YES ***"
#elif (USE_MAILBOX_CALLBACK == NO)
#warning "*** M0 mailbox callback: NO ***"
#else
#error "*** Specify if M0 mailbox callback is required (YES/NO) ***"
#endif
#elif (USE_M0_MAILBOX == NO)
#warning "*** M0 mailbox: NO ***"
#else
#error "*** Specify if M0 mailbox is required (YES/NO) ***"
#endif
#endif /* CORE_M0 */
#warning "************ PLATFORM CONFIG ************"
#endif /* platform check */

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#include "LPC43xx.h"
#include "platform_config.h"
#include "scu.h"
#include "type.h"
#include "emc_LPC43xx.h"
#include "fpu_init.h"
/**********************************************************************
** Function prototypes
**********************************************************************/
void vIOInit(void);
void clockInit(void);
/* this function initializes the platform with system level settings */
void platformInit(void) {
SystemInit();
fpuInit();
clockInit();
vIOInit();
#if (USE_EXT_STATIC_MEM == YES) || (USE_EXT_DYNAMIC_MEM == YES)
EMC_Init();
#endif
#if (USE_EXT_FLASH == YES)
// relocate vector table to internal ram
// updates also VTOR
relocIrqTable();
#endif
}
/*----------------------------------------------------------------------------
Initialize board specific IO
*----------------------------------------------------------------------------*/
void vIOInit(void)
{
#if (PLATFORM == NXP_VALIDATION_BOARD)
// P9.2 : GPIO4_14: LD11 (LED)
scu_pinmux(0x9 ,2 , PDN_ENABLE, FUNC0);
LPC_GPIO4->DIR |= (1UL << 14);
#endif
#if (PLATFORM == HITEX_A2_BOARD)
// P9.3 : GPIO4_15
scu_pinmux(0x9 , 3 , PDN_ENABLE, FUNC0);
LPC_GPIO4->DIR |= (1UL << 15);
#endif
}
/*----------------------------------------------------------------------------
Initialize clocks
*----------------------------------------------------------------------------*/
void clockInit(void)
{
/* Set PL160M @ 10*12=120 MHz */
SetPL160M(SRC_XTAL, 10);
/* Run base M4 clock from PL160M, no division */
SetClock(BASE_M4_CLK, SRC_PL160M_0, DIV1);
/* Show base out clock on output */
SetClock(BASE_OUT_CLK, SRC_XTAL, DIV1);
// clock to UART 1
SetClock(BASE_UART1_CLK, SRC_PL160M_0, DIV1);
// clock to CAN1 > 15 MHz
// SetClock(BASE_VPB1_CLK, SRC_PL160M_0, DIV8);
}

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#ifndef __PLATFORM_CONFIG_H
#define __PLATFORM_CONFIG_H
#include "stdint.h"
/****************************************************/
/* supported platforms list */
/* DO NOT CHANGE THESE DEFINITIONS */
#define NXP_VALIDATION_BOARD (1)
#define HITEX_A2_BOARD (3)
/****************************************************/
/****************************************************/
/* used for the configuration checks */
/* DO NOT CHANGE THESE DEFINITIONS */
/****************************************************/
#define YES (1)
#define NO (2)
/****************************************************/
/* USER CONFIGURATION SECTION */
/****************************************************/
/* choose the platform you want to build against */
// #define PLATFORM NXP_VALIDATION_BOARD
#define PLATFORM HITEX_A2_BOARD
/* these definitions are being taken from the build rule */
#ifdef EXT_FLASH
#define USE_EXT_FLASH (YES)
#else
#define USE_EXT_FLASH (NO)
#endif
#ifdef EXT_STAT_MEM
#define USE_EXT_STATIC_MEM (YES)
#else
#define USE_EXT_STATIC_MEM (NO)
#endif
#ifdef EXT_DYN_MEM
#define USE_EXT_DYNAMIC_MEM (YES)
#else
#define USE_EXT_DYNAMIC_MEM (NO)
#endif
/* define if the M4 should download and start the M0 application */
/* set to YES if M4 should initialize M0 application */
/* set to NO if the debugger is downloading the M0 image, used for */
/* dual core debugging sessions */
#define INITIALIZE_M0_IMAGE (NO)
/* specify if need to prefill the M0 memory before download */
#define FILL_ROM_BEFORE_DOWNLOAD (NO)
#define FILL_RAM_BEFORE_DOWNLOAD (NO)
/* define if the M4 provides a mailbox system to the M0 */
/* M0 ---> M4 */
#define USE_M4_MAILBOX (NO)
/* configure which priority the mailbox interrupt should have on the M4 side */
/* cmsis definition, priority from 0 to 7 */
#define M4_MAILBOX_PRIORITY (0)
/* define if the M0 provides a mailbox system to the M4 */
/* M4 ---> M0 */
#define USE_M0_MAILBOX (NO)
/* configure which priority the mailbox interrupt should have on the M0 side */
/* cmsis definition, priority from 0 to 3 */
#define M0_MAILBOX_PRIORITY (0)
/* define if the system needs to exchange a parameter */
#define USE_MAILBOX_PARAMETER (NO)
/* define if the system needs to hook a callback, or just notify */
#define USE_MAILBOX_CALLBACK (NO)
/* memory map for the application */
/* !!! needs to be consistent with the scatter file !!! */
#ifdef EXT_FLASH
/************************************/
/* this is for the FLASH version */
/************************************/
/* 0x1C000000 M4 ROM 4Mbytes */
/* 0x1C3FFFFF */
/* 0x10000000 M4 RAM 96K */
/* 0x10017FFF */
#define M4_ROM_START 0x1C000000
#define M4_ROM_LEN 0x400000 /* 4 Mbytes */
#define M4_RAM_START 0x10000000 /* 96 Kbytes */
#define M4_RAM_LEN 0x18000
/* 0x10080000 M0 ROM 32K */
/* 0x10087FFF */
/* 0x10088000 M0 RAM 8K */
/* 0x10089FFF */
#define M0_ROM_START 0x10080000
#define M0_ROM_LEN 0x8000
#define M0_RAM_START 0x10088000
#define M0_RAM_LEN 0x2000
/* 0x20000000 M4 BUF 16K */
/* 0x20003FFF */
/* 0x20004000 M0 BUF 16K */
/* 0x20007FFF */
#define M4_BUF_START 0x20000000
#define M4_BUF_LEN 0x4000
#define M0_BUF_START 0x20004000
#define M0_BUF_LEN 0x4000
/* 0x20008000 M4 MBX 8K */
/* 0x20009FFF */
/* 0x2000A000 M0 MBX 8K */
/* 0x2000BFFF */
#define M4_MBX_START 0x20008000
#define M4_MBX_LEN 0x2000
#define M0_MBX_START 0x2000A000
#define M0_MBX_LEN 0x2000
#else
/*******************************/
/* this is for the ram version */
/*******************************/
/* 0x10000000 M4 ROM 64K */
/* 0x1000FFFF */
/* 0x10010000 M4 RAM 32K */
/* 0x10017FFF */
#define M4_ROM_START 0x10000000
#define M4_ROM_LEN 0x10000
#define M4_RAM_START 0x10010000
#define M4_RAM_LEN 0x8000
/* 0x10080000 M0 ROM 32K */
/* 0x10087FFF */
/* 0x10088000 M0 RAM 8K */
/* 0x10089FFF */
#define M0_ROM_START 0x10080000
#define M0_ROM_LEN 0x8000
#define M0_RAM_START 0x10088000
#define M0_RAM_LEN 0x2000
/* 0x20000000 M4 BUF 16K */
/* 0x20003FFF */
/* 0x20004000 M0 BUF 16K */
/* 0x20007FFF */
#define M4_BUF_START 0x20000000
#define M4_BUF_LEN 0x4000
#define M0_BUF_START 0x20004000
#define M0_BUF_LEN 0x4000
/* 0x20008000 M4 MBX 8K */
/* 0x20009FFF */
/* 0x2000A000 M0 MBX 8K */
/* 0x2000BFFF */
#define M4_MBX_START 0x20008000
#define M4_MBX_LEN 0x2000
#define M0_MBX_START 0x2000A000
#define M0_MBX_LEN 0x2000
#endif /* ifdef EXT_FLASH */
/****************************************************/
/* END OF USER CONFIGURATION */
/* DO NOT EDIT BELOW THIS LINE */
/****************************************************/
#define M4_IPC_TABLE M4_MBX_START
#define M0_IPC_TABLE M0_MBX_START
/* configure defines for local mailbox */
#if defined (CORE_M0) && (USE_M0_MAILBOX == YES)
#define PROVIDE_M0_LOCAL_MBX (1)
#endif
#if defined (CORE_M4) && (USE_M4_MAILBOX == YES)
#define PROVIDE_M4_LOCAL_MBX (1)
#endif
#if defined PROVIDE_M0_LOCAL_MBX || PROVIDE_M4_LOCAL_MBX
#define LOCAL_MAILBOX_ENABLED (1)
#endif
#if defined (CORE_M0) && (USE_M4_MAILBOX == YES)
#define PROVIDE_M0_REMOTE_MBX (1)
#endif
#if defined (CORE_M4) && (USE_M0_MAILBOX == YES)
#define PROVIDE_M4_REMOTE_MBX (1)
#endif
#if defined PROVIDE_M0_REMOTE_MBX || PROVIDE_M4_REMOTE_MBX
#define REMOTE_MAILBOX_ENABLED (1)
#endif
#if(USE_MAILBOX_PARAMETER == YES)
#define MBX_PARAM_DEFAULT ,0x0
#else
#define MBX_PARAM_DEFAULT
#endif
#define DUMMY_CALLBACK ,(mbxCallback_t) &dummyCallback
#if (USE_MAILBOX_CALLBACK == YES)
#define MBX_CALLBACK_DEFAULT DUMMY_CALLBACK
#else
#define MBX_CALLBACK_DEFAULT
#endif
/****************************************************/
/* platform wise initialization functions */
/****************************************************/
void platformInit(void);
#endif /* __PLATFORM_CONFIG_H */

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;/***********************************************************************
; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $
; *
; * Project: LPC43xx CMSIS Package
; *
; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __endVectors
Sign_Value EQU 0x5A5A5A5A
; this might be meaningful only for images which require a header
; IF :DEF:EXT_FLASH
;
;Signature_Size EQU 0x10
; DCD 0x000200DA
; DCD 0x00000000
; DCD 0x00000000
; DCD 0x00000000
; SPACE Signature_Size
; DCD __initial_sp
; DCD Reset_Handler ; 1 Reset Handler
; FILL 256 - 8 - 16
; ENDIF
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0_IRQHandler ; 17 M0
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD 0 ; 19 Reserved
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD 0 ; 66 Reserved
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
__endVectors
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IF :DEF:EXT_FLASH
; Extend the address bus, as the bootloader configured only [A13:0]
; *(uint32_t*)(0x40086320) = 0x000000F1;
; P6_8: A14 (function 1)
LDR R0, =0x40086320
LDR R1, =0x000000F1
STR R1, [R0,#0]
; *(uint32_t*)(0x4008631C) = 0x000000F1;
; P6_7: A15 (function 1)
LDR R0, =0x4008631C
LDR R1, =0x000000F1
STR R1, [R0,#0]
; *(uint32_t*)(0x400866C0) = 0x000000F2;
; PD_16: A16 (function 2)
LDR R0, =0x400866C0
LDR R1, =0x000000F2
STR R1, [R0,#0]
; *(uint32_t*)(0x400866BC) = 0x000000F2;
; PD_15: A17 (function 2)
LDR R0, =0x400866BC
LDR R1, =0x000000F2
STR R1, [R0,#0]
; *(uint32_t*)(0x40086700) = 0x000000F3;
; PE_0: A18 (function 3)
LDR R0, =0x40086700
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x40086704) = 0x000000F3;
; PE_1: A19 (function 3)
LDR R0, =0x40086704
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x40086708) = 0x000000F3;
; PE_2: A20 (function 3)
LDR R0, =0x40086708
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x4008670C) = 0x000000F3;
; PE_3: A21 (function 3)
LDR R0, =0x4008670C
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x40086710) = 0x000000F3;
; PE_4: A22 (function 3)
LDR R0, =0x40086710
LDR R1, =0x000000F3
STR R1, [R0,#0]
ENDIF
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
; FreeRTOS handler
vPortSVCHandler\
PROC
EXPORT vPortSVCHandler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
; FreeRTOS handler
xPortPendSVHandler\
PROC
EXPORT xPortPendSVHandler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
; FreeRTOS handler
xPortSysTickHandler\
PROC
EXPORT xPortSysTickHandler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0_IRQHandler
DMA_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WDT_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/*****************************************************************************
* config.h: Header file for NXP LPC43xx Family Microprocessors
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* History
* 2011.6.22 ver 1.00 Preliminary version, first Release
*
******************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
#define IRC_TRIM_VAL 0x34A /* IRC trim value for 12MHz output */
#define XTAL_FREQ (12000000UL) /* Frequency of external xtal */
#define EXT_FREQ (12000000UL) /* Frequency of external clock on EXT_TCK, ENET_RX_CLK or ENET_TX_CLK */
/*----------------------------------------------------------------------------
Retarget selection
*----------------------------------------------------------------------------*/
typedef enum {
RETARGET_USART0 = 0,
RETARGET_UART1 = 1,
RETARGET_USART2 = 2,
RETARGET_USART3 = 3
} RETARGET_Type;
#define RETARGET_UART_BUFSIZE 0x40
extern volatile uint32_t UART0Count;
extern volatile uint8_t UART0Buffer[RETARGET_UART_BUFSIZE];
extern volatile uint32_t UART1Count;
extern volatile uint8_t UART1Buffer[RETARGET_UART_BUFSIZE];
extern volatile uint32_t UART2Count;
extern volatile uint8_t UART2Buffer[RETARGET_UART_BUFSIZE];
extern volatile uint32_t UART3Count;
extern volatile uint8_t UART3Buffer[RETARGET_UART_BUFSIZE];
extern void RetargetInit(RETARGET_Type retarget, uint32_t baudrate);
/*----------------------------------------------------------------------------
Board selection
*----------------------------------------------------------------------------*/
//NXP LPC4300 validation board
//#define NXP_VALIDATION_BOARD
//Hitex LPC4350 evaluation board
//#define USE_HITEX_LPC4350_EVAL
#endif /* end __CONFIG_H */
/*****************************************************************************
** End Of File
******************************************************************************/

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/**************************************************************************//**
* @file core_cm4.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H__
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_CONTROL(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_IPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_APSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_xPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PSP(uint32_t topOfProcStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_MSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_MSP(uint32_t topOfMainStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PRIMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PRIMASK(uint32_t priMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_BASEPRI(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_BASEPRI(uint32_t basePri);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_FAULTMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_FAULTMASK(uint32_t faultMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H__ */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __no_operation
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
/* intrinsic void __ISB(void) (see intrinsics.h) */
/* intrinsic void __DSB(void) (see intrinsics.h) */
/* intrinsic void __DMB(void) (see intrinsics.h) */
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
/* intrinsic __SSAT (see intrinsics.h) */
/* intrinsic __USAT (see intrinsics.h) */
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H__ */

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/***********************************************************************
* $Id: dma.h 8242 2011-10-11 15:15:25Z nxp28536 $
*
* Project: LPC43xx Validation
*
* Description: DMA Test
*
* Copyright(C) 2010, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __DMA_H
#define __DMA_H
#define DMA_SIZE 0x1000
#define M2M 0x00
#define M2P 0x01
#define P2M 0x02
#define P2P 0x03
extern void DMA_IRQHandler (void);
extern uint32_t DMA_Init_Matrix( uint32_t u32SrcAddr );
typedef struct _LinkedList {
DWORD SRC;
DWORD DST;
DWORD LLI;
DWORD CTRL;
}LinkedList;
#endif /* end __DMA_H */
/****************************************************************************
** End Of File
****************************************************************************/

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/***********************************************************************
* $Id: emc_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC43xx.c
*
* Project: NXP LPC43xx Common
*
* Description: Initialisation of the external memory interface and
* configuration for the specific memories connected to
* the LPC43xx
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include "LPC43xx.h"
#include "system_LPC43xx.h"
#include "scu.h"
#include "config.h"
#include "platform_config.h"
#include "emc_LPC43xx.h"
/**********************************************************************
** Function prototypes
**********************************************************************/
#define DELAY_1usFreq (1000000) // 1MHz equivalent to 1usec
static uint32_t delayBase1us; // calculated depending on M4/EMI frequency
static void vDelay(uint32_t u32Delay); // delay function
/****************************************************************************************
* Call the required memory setup functions from here
*
*
****************************************************************************************/
void EMC_Init( void )
{
// The address/data pins for the memory interface are required for the static and for
// dynamic memories
EMC_Config_Pinmux();
// Initialise the control signals for static memories
#if (USE_EXT_STATIC_MEM == YES)
// Initialise the control signals for static memories
EMC_Config_Static();
// #if (USE_EXT_DYNAMIC_MEM == NO)
// LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
// LPC_EMC->CONFIG = 0;
// // Buffers for the static memories are enabled as well. If there is SDRAM as well,
// // then this is done after the initialisation for the dynamic memory interface.
// LPC_EMC->STATICCONFIG0 = 0x00080081;
// #endif
#endif
#if (USE_EXT_DYNAMIC_MEM == YES)
// The setup for dynamic memories (SDRAM)
EMC_Init_SRDRAM(SDRAM_BASE, PART_WIDTH, PART_SIZE, EXT_WIDTH, COL_ADDR_BITS);
#elif (USE_EXT_DYNAMIC_MEM == NO)
LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
LPC_EMC->CONFIG = 0;
#endif
// Buffers for the static memories can now be enabled as well. In a system with static and dynamic memory
// this should only been done after the SDRAM initialisation --> here
LPC_EMC->STATICCONFIG0 = 0x00080081;
}
/****************************************************************************************
* Set up the address/data pins for external memory interface in LP43xx
*
* Modify this function in case not all of the address/data pins are needed.
****************************************************************************************/
void EMC_Config_Pinmux(void)
{
// Disable the external memory controller before changing pin control configuration
LPC_EMC->CONTROL = 0x00000000;
// EMC_OUT (PUP_CLEAR | SLEWRATE_FAST | FILTER_DISABLE)
// EMC_IO (PUP_CLEAR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
// Data line configuration
scu_pinmux(0x1, 7, EMC_IO, FUNC3); // P1_7: D0
scu_pinmux(0x1, 8, EMC_IO, FUNC3); // P1_8: D1
scu_pinmux(0x1, 9, EMC_IO, FUNC3); // P1_9: D2
scu_pinmux(0x1, 10, EMC_IO, FUNC3); // P1_10: D3
scu_pinmux(0x1, 11, EMC_IO, FUNC3); // P1_11: D4
scu_pinmux(0x1, 12, EMC_IO, FUNC3); // P1_12: D5
scu_pinmux(0x1, 13, EMC_IO, FUNC3); // P1_13: D6
scu_pinmux(0x1, 14, EMC_IO, FUNC3); // P1_14: D7
scu_pinmux(0x5, 4, EMC_IO, FUNC2); // P5_4: D8
scu_pinmux(0x5, 5, EMC_IO, FUNC2); // P5_5: D9
scu_pinmux(0x5, 6, EMC_IO, FUNC2); // P5_6: D10
scu_pinmux(0x5, 7, EMC_IO, FUNC2); // P5_7: D11
scu_pinmux(0x5, 0, EMC_IO, FUNC2); // P5_0: D12
scu_pinmux(0x5, 1, EMC_IO, FUNC2); // P5_1: D13
scu_pinmux(0x5, 2, EMC_IO, FUNC2); // P5_2: D14
scu_pinmux(0x5, 3, EMC_IO, FUNC2); // P5_3: D15
scu_pinmux(0xD, 2, EMC_IO, FUNC2); // PD_2: D16
scu_pinmux(0xD, 3, EMC_IO, FUNC2); // PD_3: D17
scu_pinmux(0xD, 4, EMC_IO, FUNC2); // PD_4: D18
scu_pinmux(0xD, 5, EMC_IO, FUNC2); // PD_5: D19
scu_pinmux(0xD, 6, EMC_IO, FUNC2); // PD_6: D20
scu_pinmux(0xD, 7, EMC_IO, FUNC2); // PD_7: D21
scu_pinmux(0xD, 8, EMC_IO, FUNC2); // PD_8: D22
scu_pinmux(0xD, 9, EMC_IO, FUNC2); // PD_9: D23
scu_pinmux(0xE, 5, EMC_IO, FUNC3); // PE_5: D24
scu_pinmux(0xE, 6, EMC_IO, FUNC3); // PE_6: D25
scu_pinmux(0xE, 7, EMC_IO, FUNC3); // PE_7: D26
scu_pinmux(0xE, 8, EMC_IO, FUNC3); // PE_8: D27
scu_pinmux(0xE, 9, EMC_IO, FUNC3); // PE_9: D28
scu_pinmux(0xE, 10, EMC_IO, FUNC3); // PE_10: D29
scu_pinmux(0xE, 11, EMC_IO, FUNC3); // PE_11: D30
scu_pinmux(0xE, 12, EMC_IO, FUNC3); // PE_12: D31
// Address line configuration
scu_pinmux(0x2, 9, EMC_IO, FUNC3); // P2_9: A0
scu_pinmux(0x2, 10, EMC_IO, FUNC3); // P2_10: A1
scu_pinmux(0x2, 11, EMC_IO, FUNC3); // P2_11: A2
scu_pinmux(0x2, 12, EMC_IO, FUNC3); // P2_12: A3
scu_pinmux(0x2, 13, EMC_IO, FUNC3); // P2_13: A4
scu_pinmux(0x1, 0, EMC_IO, FUNC2); // P1_0: A5
scu_pinmux(0x1, 1, EMC_IO, FUNC2); // P1_1: A6
scu_pinmux(0x1, 2, EMC_IO, FUNC2); // P1_2: A7
scu_pinmux(0x2, 8, EMC_IO, FUNC3); // P2_8: A8
scu_pinmux(0x2, 7, EMC_IO, FUNC3); // P2_7: A9
scu_pinmux(0x2, 6, EMC_IO, FUNC2); // P2_6: A10
scu_pinmux(0x2, 2, EMC_IO, FUNC2); // P2_2: A11
scu_pinmux(0x2, 1, EMC_IO, FUNC2); // P2_0: A12
scu_pinmux(0x2, 0, EMC_IO, FUNC2); // P2_0: A13
scu_pinmux(0x6, 8, EMC_IO, FUNC1); // P6_8: A14
scu_pinmux(0x6, 7, EMC_IO, FUNC1); // P6_7: A15
scu_pinmux(0xD, 16, EMC_IO, FUNC2); // PD_16: A16
scu_pinmux(0xD, 15, EMC_IO, FUNC2); // PD_15: A17
scu_pinmux(0xE, 0, EMC_IO, FUNC3); // PE_0: A18
scu_pinmux(0xE, 1, EMC_IO, FUNC3); // PE_1: A19
scu_pinmux(0xE, 2, EMC_IO, FUNC3); // PE_2: A20
scu_pinmux(0xE, 3, EMC_IO, FUNC3); // PE_3: A21
scu_pinmux(0xE, 4, EMC_IO, FUNC3); // PE_4: A22
// Control signals for static memory
scu_pinmux(0x1, 6, EMC_IO, FUNC3); // P1_6: WE
scu_pinmux(0x1, 5, EMC_IO, FUNC3); // P1_5: CS0
scu_pinmux(0x1, 3, EMC_IO, FUNC3); // P1_6: OE
scu_pinmux(0x1, 4, EMC_IO, FUNC3); // P1_5: BLS0
scu_pinmux(0x6, 6, EMC_IO, FUNC1); // P1_6: BLS1
scu_pinmux(0xD, 12, EMC_IO, FUNC2); // PD_12: CS2
#if (USE_EXT_DYNAMIC_MEM == YES)
// Control signals for dynamic memory
scu_pinmux(0x6, 9, EMC_IO, FUNC3); // P6_9: DYCS0
scu_pinmux(0x6, 4, EMC_IO, FUNC3); // P6_4: CAS
scu_pinmux(0x6, 5, EMC_IO, FUNC3); // P6_5: RAS
scu_pinmux(0x6, 11, EMC_IO, FUNC3); // P6_11: CKEOUT0
scu_pinmux(0x6, 12, EMC_IO, FUNC3); // P6_12: DQMOUT0
scu_pinmux(0x6, 10, EMC_IO, FUNC3); // P6_10: DQMOUT1
LPC_SCU_CLK(0) = 0 + EMC_IO; // EMC_CLK0 signal on pin CLK0 (needed for SDRAM)
LPC_SCU_CLK(1) = 0 + EMC_IO;
LPC_SCU_CLK(2) = 0 + EMC_IO;
LPC_SCU_CLK(3) = 0 + EMC_IO;
#endif
}
/****************************************************************************************
* Configure CS0 for 70ns 16-bit flash memory on the Hitex board
* Configure CS2 for 55ns 16-bit SRAM on the Hitex board
*
****************************************************************************************/
void EMC_Config_Static(void)
{
// Configure CS0 for flash memory
// @120MHz there should be 8 or 9 waitstates for the 70ns flash, apparently it works with 7
LPC_EMC->STATICCONFIG0 = 0x00000081; // CS0: 16 bit = WE
LPC_EMC->STATICWAITOEN0 = 0; // CS0: WAITOEN = 0
#if (PLATFORM == HITEX_A2_BOARD)
LPC_EMC->STATICWAITRD0 = 7; // CS0: WAITRD = 7
// The Hitex board has external SRAM on CS2
// @120MHz there should be 7 waitstates for the 55ns SRAM, it should work with 6
LPC_EMC->STATICCONFIG0 = 0x00000081; // CS2: 16 bit = WE
LPC_EMC->STATICWAITOEN2 = 0; // CS2: WAITOEN = 0
LPC_EMC->STATICWAITRD2 = 7; // CS2: WAITRD = 6
#elif (PLATFORM == NXP_VALIDATION_BOARD)
LPC_EMC->STATICWAITRD0 = check 9; // CS0: WAITRD = 8
// to be added
LPC_EMC->STATICCONFIG0 = check 0x00000081; // CS2: 16 bit = WE
LPC_EMC->STATICWAITOEN2 = check 0; // CS2: WAITOEN = 0
LPC_EMC->STATICWAITRD2 = check 7; // CS2: WAITRD = 6
#endif
}
// Defines for EMC signal delay settings
#define EMC_B_ENABLE (1 << 19)
#define EMC_ENABLE (1 << 0)
#define EMC_CE_ENABLE (1 << 0)
#define EMC_CS_ENABLE (1 << 1)
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
#define EMC_INIT(i) ((i) << 7)
#define EMC_NORMAL (0)
#define EMC_MODE (1)
#define EMC_PRECHARGE_ALL (2)
#define EMC_NOP (3)
/****************************************************************************************
* Configure the delays for the SDRAM
*
* - on the Hitex board (IS42S16400D-7TL)
* - on the NXP evaluation board (MT48LC4M32B2)
* - on the NXP validation board (MT48LC4M32B2)
*
****************************************************************************************/
#if (PLATFORM == HITEX_A2_BOARD) || (PLATFORM == NXP_VALIDATION_BOARD)
// Defines for SDRAM devices
#define DOUT_DELAY 0
#define CLK0_DELAY 5
#define CLKE0_DELAY 5
#define RAS_DELAY 0
#define CAS_DELAY 0
#define WE_DELAY 0
#define DYCS0_DELAY 0
#define DQM0_DELAY 0
#define FBCLK0_DELAY 0
#define CCLK_DELAY 0
#define ADDR_DELAY 0
#define DIN_DELAY 0
#define DEN_DELAY 0
#endif
void initEmiDelays(void)
{
// eventually configure delays, defaults are zero
// CLK & CLKE0 delay
*(uint32_t*)(LPC_SCU_BASE + 0xD00) = ((CLK0_DELAY << 16) | (CLKE0_DELAY << 0) );
// EMCCTRLDELAY, address 0x4008 6D04
*(uint32_t*)(LPC_SCU_BASE + 0xD04) = ((WE_DELAY << 12)| (CAS_DELAY << 4) | (RAS_DELAY << 0) );
// DYCS0_DELAY, address 0x4008 6D08
*(uint32_t*)(LPC_SCU_BASE + 0xD08) = ((DYCS0_DELAY << 0));
// data out delay for D0 to D31 EMCDOUTDELAY
*(uint32_t*)(LPC_SCU_BASE + 0xD0C) = ((DOUT_DELAY << 28) | (DOUT_DELAY << 24) | (DOUT_DELAY << 20) | (DOUT_DELAY << 16)|(DQM0_DELAY << 12) | (DQM0_DELAY << 8) | (DQM0_DELAY << 4) | (DQM0_DELAY << 0)) ;
// EMCFBCLKDELAY, address 0x4008 6D10
*(uint32_t*)(LPC_SCU_BASE + 0xD10) = ((CCLK_DELAY << 16)|(FBCLK0_DELAY << 12) | (FBCLK0_DELAY << 8) | (FBCLK0_DELAY << 4) | (FBCLK0_DELAY << 0)) ;
// EMCADDRDELAY, address 0x4008 6D14, 0x4008 6D18, 0x4008 6D1C)
*(uint32_t*)(LPC_SCU_BASE + 0xD14) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
*(uint32_t*)(LPC_SCU_BASE + 0xD18) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
*(uint32_t*)(LPC_SCU_BASE + 0xD1C) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
// data in delay for D0 to D31 EMCDINDELAY
*(uint32_t*)(LPC_SCU_BASE + 0xD24) = ((DEN_DELAY << 28)|(DEN_DELAY << 24)|(DEN_DELAY << 20)|(DEN_DELAY << 16)|(DIN_DELAY << 12)|(DIN_DELAY << 8)|(DIN_DELAY << 4)|(DIN_DELAY << 0));
}
/****************************************************************************************
* Configure the EMI for the SDRAM
*
* - on the Hitex board (IS42S16400D-7TL)
* - on the NXP validation board (MT48LC4M32B2)
*
****************************************************************************************/
void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// calculate a 1 usec delay base
delayBase1us = M4Frequency / DELAY_1usFreq;
// eventually adjust the CCU delays for EMI (default to zero)
initEmiDelays();
// Initialize EMC to interface with SDRAM. The EMC needs to run for this.
LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller
LPC_EMC->CONFIG = 0;
#if (PLATFORM == HITEX_A2_BOARD)
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0.
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.
LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period
LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period
LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time
LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time
LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.
LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time
LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period
LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period
LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time
LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency
LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
vDelay(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation
vDelay(100);
LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// Write configuration data to SDRAM device
if(u32DataBus == 0) // 16-bit data bus, the EMC enforces a burst size 8
{
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
}
else // burst size 4 (which is not an option for 16-bit data bus anyway)
{
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
#endif // HITEX_BOARD
#if (PLATFORM == NXP_VALIDATION_BOARD)
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8);
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
LPC_EMC->DYNAMICRAS = 2;
LPC_EMC->DYNAMICSREX = 5;
LPC_EMC->DYNAMICAPR = 0;
LPC_EMC->DYNAMICDAL = 4;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 5;
LPC_EMC->DYNAMICRFC = 5;
LPC_EMC->DYNAMICXSR = 5;
LPC_EMC->DYNAMICRRD = 0;
LPC_EMC->DYNAMICMRD = 0;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
vDelay(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
vDelay(100);
LPC_EMC->DYNAMICREFRESH = 83;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// Write configuration data to SDRAM device
if(u32DataBus == 0) // burst size 8
{
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
}
else // burst size 4
{
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
#endif // Validation board
LPC_EMC->DYNAMICCONTROL = 0;
LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers
}
/**********************************************************************
** Function name:
**
** Description:
**
** Parameters:
**
** Returned value:
**********************************************************************/
static void vDelay(uint32_t u32Delay)
{
volatile uint32_t i;
for(i = 0; i < (u32Delay * delayBase1us); i++);
}

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//BF: take over the whole file
/***********************************************************************
* $Id: emc_LPC43xx.h 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC18xx_43xx.h
*
* Project: NXP LPC18xx/LPC43xx Common
*
* Description: Header file for emc_LPC18xx_43xx.c
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef EMC_LPC43XX_H_
#define EMC_LPC43XX_H_
enum {
PART_WIDTH_8 = 0,
PART_WIDTH_16 = 1,
PART_WIDTH_32 = 2
};
enum {
PART_SIZE_16 = 0,
PART_SIZE_64 = 1,
PART_SIZE_128 = 2,
PART_SIZE_256 = 3,
PART_SIZE_512 = 4
};
enum {
EXT_WIDTH_16 = 0,
EXT_WIDTH_32 = 1
};
#if (PLATFORM == HITEX_A2_BOARD) //defined USE_HITEX_A2
#define SDRAM_SIZE 0x00800000 // 8 MByte SDRAM IS42S16400D-7TL
#define SDRAM_BASE 0x28000000 // base address for DYCS0
// We have 16 data lines connected to the SDRAM
#define PART_WIDTH (PART_WIDTH_16) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.
#define PART_SIZE (PART_SIZE_64)
#define EXT_WIDTH (EXT_WIDTH_16) // external memory bus width
#define COL_ADDR_BITS (8) // for calculating how to write mode bits
#endif
#if (PLATFORM == NXP_VALIDATION_BOARD)
#define SDRAM_SIZE 0x01000000 // 16 MByte SDRAM MT48LC4M32
#define SDRAM_BASE 0x28000000 // base address for DYCS0
// We have 32 data lines connected to the SDRAM
#define PART_WIDTH (PART_WIDTH_32) // part width (possibly smaller than EXT_WIDTH, e.g. two 8-bit chips cascaded as 16-bit memory.
#define PART_SIZE (PART_SIZE_128)
#define EXT_WIDTH (EXT_WIDTH_32) // external memory bus width
#define COL_ADDR_BITS (8) // for calculating how to write mode bits
#endif
// Function prototypes
void EMC_Init( void );
void EMC_Config_Pinmux( void );
void EMC_Config_Static( void );
void initEmiDelays( void );
void EMC_Init_SRDRAM( uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits );
#endif /* EMC_LPC43XX_H_ */

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/***********************************************************************
* $Id: fpu_init.c
*
* Project: LPC43xx
*
* Description: fpu initialization routine
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#define LPC_CPACR 0xE000ED88
#define SCB_MVFR0 0xE000EF40
#define SCB_MVFR0_RESET 0x10110021
#define SCB_MVFR1 0xE000EF44
#define SCB_MVFR1_RESET 0x11000011
#include "stdint.h"
void fpuInit(void)
{
// from arm trm manual:
// ; CPACR is located at address 0xE000ED88
// LDR.W R0, =0xE000ED88
// ; Read CPACR
// LDR R1, [R0]
// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
// ORR R1, R1, #(0xF << 20)
// ; Write back the modified value to the CPACR
// STR R1, [R0]
volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
volatile uint32_t Cpacr;
volatile uint32_t Mvfr0;
volatile uint32_t Mvfr1;
char vfpPresent = 0;
Mvfr0 = *regMvfr0;
Mvfr1 = *regMvfr1;
vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
if(vfpPresent)
{
Cpacr = *regCpacr;
Cpacr |= (0xF << 20);
*regCpacr = Cpacr; // enable CP10 and CP11 for full access
}
}

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/***********************************************************************
* $Id: fpu_init.h
*
* Project: LPC43xx
*
* Description: fpu initialization routine header
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __FPU_INIT_H
#define __FPU_INIT_H
void fpuInit(void);
#endif /* __FPU_INIT_H */

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/***********************************************************************
* $Id: scu.c 8242 2011-10-11 15:15:25Z nxp28536 $
*
* Project: LPC43xx Common
*
* Description:
* This file contains code to configure the PINMUX
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#if defined CORE_M4
#include "LPC43xx.h" /* LPC43xx definitions */
#endif
#ifdef CORE_M0
#include "LPC43xx_M0.h" /* LPC43xx definitions */
#endif
#include "type.h"
#include "scu.h"
void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func)
{
volatile unsigned int * const scu_base=(unsigned int*)(LPC_SCU_BASE);
scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func;
} /* scu_pinmux */

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/***********************************************************************
* $Id: scu.h 8389 2011-10-19 13:53:14Z nxp28536 $
*
* Project: LPC43xx Common
*
* Description:
* Header file for PINMUX configuration
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SCU_H
#define __SCU_H
#define PORT_OFFSET 0x80
#define PIN_OFFSET 0x04
/* Pin modes */
//#define MD_PUP (0x0<<3)
//#define MD_BUK (0x1<<3)
//#define MD_PLN (0x2<<3)
//#define MD_PDN (0x3<<3)
//#define MD_EHS (0x1<<5)
//#define MD_EZI (0x1<<6)
//#define MD_ZI (0x1<<7)
//#define MD_EHD0 (0x1<<8)
//#define MD_EHD1 (0x1<<8)
/* Pin modes
* =========
* The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip
* pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the
* selection of the repeater mode.
* The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
* pull-up/pull-down. The default value is pull-up enabled.
*
* The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
* the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
* known state if it is configured as an input and is not driven externally. Repeater mode may
* typically be used to prevent a pin from floating (and potentially using significant power if it
* floats to an indeterminate state) if it is temporarily not driven.
*
* To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
* the pin configuration registers. By default, the input buffer is disabled.
* For pads that support both a digital and an analog function, the input buffer must be
* disabled before enabling the analog function
*
* All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
* off. By default, the glitch filter is on. The glitch filter should be disabled for
* clocking signals with frequencies higher than 30 MHz.
*
* Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
* between lower noise and low speed or higher noise and high speed . The typical
* frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for
* high-speed pins.
*/
/* these definitions allow to set or clear single configuration bits */
#define PDN_SET (1 << 3)
#define PDN_CLR (0)
#define PUP_SET (0)
#define PUP_CLR (1 << 4)
/* these definitions allow to configure the port in one specific mode */
/* within scu_pinmux() function */
#define PDN_ENABLE (0x3 << 3) /* pull down */
#define PUP_ENABLE (0x0 << 3) /* pull up */
#define REPEATER_ENABLE (0x1 << 3) /* repeater */
#define PLAIN_ENABLE (0x2 << 3) /* no pull up, no pull down (plain) */
#define SLEWRATE_SLOW (0)
#define SLEWRATE_FAST (1 << 5)
/* enable / disable the input buffer */
#define INBUF_ENABLE (1 << 6)
#define INBUF_DISABLE (0)
/* enable / disable the filter */
#define FILTER_ENABLE (0)
#define FILTER_DISABLE (1 << 7)
/* define the drive strenght */
#define DRIVE_8MA (0x1 << 8) // Drive strength of 8mA
#define DRIVE_14MA (0x1 << 9) // Drive strength of 14mA
#define DRIVE_20MA (0x3 << 8) // Drive strength of 20mA
// Configuration examples for external memory bus pins
#define EMC_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE)
#define EMC_IO (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
// Configuration examples
#define CLK_OUT (PUP_CLR | SLEWRATE_FAST | FILTER_DISABLE)
#define CLK_IN (PUP_CLR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
/* Pin functions */
#define FUNC0 0x0
#define FUNC1 0x1
#define FUNC2 0x2
#define FUNC3 0x3
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
extern void scu_pinmux(unsigned port, unsigned pin, unsigned mode, unsigned func);
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
#endif /* end __SCU_H */
/*****************************************************************************
** End Of File
******************************************************************************/

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;/***********************************************************************
; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $
; *
; * Project: LPC43xx CMSIS Package
; *
; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __endVectors
Sign_Value EQU 0x5A5A5A5A
; IF :DEF:EXT_FLASH
;
;Signature_Size EQU 0x10
; DCD 0x000200DA
; DCD 0x00000000
; DCD 0x00000000
; DCD 0x00000000
; SPACE Signature_Size
; DCD __initial_sp
; DCD Reset_Handler ; 1 Reset Handler
; FILL 256 - 8 - 16
; ENDIF
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0_IRQHandler ; 17 M0
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD 0 ; 19 Reserved
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD 0 ; 66 Reserved
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
__endVectors
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IF :DEF:EXT_FLASH
; Extend the address bus, as the bootloader configured only [A13:0]
; *(uint32_t*)(0x40086320) = 0x000000F1;
; P6_8: A14 (function 1)
LDR R0, =0x40086320
LDR R1, =0x000000F1
STR R1, [R0,#0]
; *(uint32_t*)(0x4008631C) = 0x000000F1;
; P6_7: A15 (function 1)
LDR R0, =0x4008631C
LDR R1, =0x000000F1
STR R1, [R0,#0]
; *(uint32_t*)(0x400866C0) = 0x000000F2;
; PD_16: A16 (function 2)
LDR R0, =0x400866C0
LDR R1, =0x000000F2
STR R1, [R0,#0]
; *(uint32_t*)(0x400866BC) = 0x000000F2;
; PD_15: A17 (function 2)
LDR R0, =0x400866BC
LDR R1, =0x000000F2
STR R1, [R0,#0]
; *(uint32_t*)(0x40086700) = 0x000000F3;
; PE_0: A18 (function 3)
LDR R0, =0x40086700
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x40086704) = 0x000000F3;
; PE_1: A19 (function 3)
LDR R0, =0x40086704
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x40086708) = 0x000000F3;
; PE_2: A20 (function 3)
LDR R0, =0x40086708
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x4008670C) = 0x000000F3;
; PE_3: A21 (function 3)
LDR R0, =0x4008670C
LDR R1, =0x000000F3
STR R1, [R0,#0]
; *(uint32_t*)(0x40086710) = 0x000000F3;
; PE_4: A22 (function 3)
LDR R0, =0x40086710
LDR R1, =0x000000F3
STR R1, [R0,#0]
; IMPORT _startup_configureFlash
; LDR R0, =_startup_configureFlash
; NOP
; NOP
; NOP
; BLX R0
ENDIF
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
; FreeRTOS handler
vPortSVCHandler\
PROC
EXPORT vPortSVCHandler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
; FreeRTOS handler
xPortPendSVHandler\
PROC
EXPORT xPortPendSVHandler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
; FreeRTOS handler
xPortSysTickHandler\
PROC
EXPORT xPortSysTickHandler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0_IRQHandler
DMA_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WDT_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

590
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/system_LPC43xx.c Normal file
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@ -0,0 +1,590 @@
/***********************************************************************
* $Id: system_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $
*
* Project: LPC43xx Common
*
* Description:
* CMSIS Cortex-M4 Device Peripheral Access Layer Source File
* for the NXP LPC43xx Device Series
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include <stdint.h>
#if defined CORE_M4
#include "LPC43xx.h" /* LPC18xx definitions */
#endif
#ifdef CORE_M0
#include "LPC43xx_M0.h" /* LPC18xx definitions */
#endif
#include "scu.h"
#include "type.h"
#include "config.h"
/*--------------------- Clock Configuration ----------------------------------*/
//#define OTP
#define FLASH_SETUP 0
#define FLASHCFG_Val 0x0000303A
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
#error "SCS: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
#error "CLKSRCSEL: Value out of range!"
#endif
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
#error "PLL0CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
#error "PLL1CFG: Invalid values of reserved bits!"
#endif
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
#endif
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
#error "USBCLKCFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
#error "PCLKSEL0: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
#error "PCLKSEL1: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
#error "PCONP: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
#error "CLKOUTCFG: Invalid values of reserved bits!"
#endif
/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
#error "FLASHCFG: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
uint32_t XtalFrequency = 0;
uint32_t PL160M_0Frequency = 0;
uint32_t PL160M_1Frequency = 0;
uint32_t PL160M_2Frequency = 0;
uint32_t PL550Frequency = 0;
uint32_t PL550FracFrequency = 0; //New in Falcon
uint32_t IDIVAFrequency = 0;
uint32_t IDIVBFrequency = 0;
uint32_t IDIVCFrequency = 0;
uint32_t IDIVDFrequency = 0;
uint32_t IDIVEFrequency = 0;
uint32_t USB1Frequency = 0;
uint32_t M4Frequency = 0;
uint32_t SPIFIFrequency = 0;
uint32_t SPIFrequency = 0;
uint32_t EnetRxFrequency = 0;
uint32_t EnetTxFrequency = 0;
uint32_t EXTFrequency = 0;
uint32_t VPB1Frequency = 0;
uint32_t VPB3Frequency = 0;
uint32_t LCDFrequency = 0;
uint32_t SCIFrequency = 0;
uint32_t VADCFrequency = 0;
uint32_t SDIOFrequency = 0;
uint32_t SSP0Frequency = 0;
uint32_t SSP1Frequency = 0;
uint32_t UART0Frequency = 0;
uint32_t UART1Frequency = 0;
uint32_t UART2Frequency = 0;
uint32_t UART3Frequency = 0;
uint32_t OUTFrequency = 0;
uint32_t AOTESTFrequency = 0;
uint32_t ISOFrequency = 0;
uint32_t BSRFrequency = 0;
uint32_t CLK_TESTFrequency = 0;
uint32_t APLLFrequency = 0;
uint32_t SPARE0Frequency = 0;
uint32_t SPARE1Frequency = 0;
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*
*/
void SystemInit(void)
{
#ifdef OTP
// Set IRC trim if OTP is not programmed.
if( *(uint32_t *)LPC_OTP_CTRL_BASE == 0x00FF ||
*(uint32_t *)(LPC_OTP_CTRL_BASE+4) == 0x0000)
{
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
}
#else
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
#endif
// Set all GPIO as input.
LPC_GPIO0->DIR = 0x0000;
LPC_GPIO1->DIR = 0x0000;
LPC_GPIO2->DIR = 0x0000;
LPC_GPIO3->DIR = 0x0000;
LPC_GPIO4->DIR = 0x0000;
LPC_GPIO5->DIR = 0x0000;
LPC_GPIO6->DIR = 0x0000;
LPC_GPIO7->DIR = 0x0000;
// M4 runs on IRC by default
M4Frequency = IRC_OSC;
XtalFrequency = XTAL_FREQ;
EXTFrequency = EXT_FREQ;
}
/**
* Set Clock
*
* @param target PLL, source clock, division
* @return none
*
* @brief Setup a clock
*/
void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div)
{
volatile uint32_t target_clk_adr;
volatile uint8_t auto_block=TRUE;
uint32_t src_freq;
EnableSourceClk(src_clk);
switch(div)
{
case(DIV1): // Divide by 1 == no division
break;
case(DIV2):
LPC_CGU->IDIVA_CTRL = (src_clk<<24) | (1<<2) | AUTO_BLOCK;
IDIVAFrequency = GetClockFrequency(src_clk)/2;
src_clk = SRC_IDIV_0; // Set new src_clk for target_clk
break;
case(DIV4):
LPC_CGU->IDIVB_CTRL = (src_clk<<24) | (3<<2) |AUTO_BLOCK;
IDIVBFrequency = GetClockFrequency(src_clk)/4;
src_clk = SRC_IDIV_1; // Set new src_clk for target_clk
break;
case(DIV8):
LPC_CGU->IDIVC_CTRL = (src_clk<<24) | (7<<2) |AUTO_BLOCK;
IDIVCFrequency = GetClockFrequency(src_clk)/8;
src_clk = SRC_IDIV_2; // Set new src_clk for target_clk
break;
case(DIV16):
LPC_CGU->IDIVD_CTRL = (src_clk<<24) | (15<<2) |AUTO_BLOCK;
IDIVDFrequency = GetClockFrequency(src_clk)/16;
src_clk = SRC_IDIV_3; // Set new src_clk for target_clk
break;
case(DIV256):
LPC_CGU->IDIVE_CTRL = (src_clk<<24) | (255<<2) |AUTO_BLOCK; // MAX 128? IDIV bit 2:9 = 7 bits = 127 max
IDIVEFrequency = GetClockFrequency(src_clk)/256;
src_clk = SRC_IDIV_4; // Set new src_clk for target_clk
break;
default:
break;
}
src_freq = GetClockFrequency(src_clk);
switch(target_clk)
{
case(BASE_OUT_CLK):
{
LPC_SCU->SFSCLK_0 = 1; // function 1; CGU clk out, diable pull down, disable pull-up
auto_block = FALSE;
break;
}
case(XTAL):
{
XtalFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
break;
}
case(ENET_RX):
{
EnetRxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
break;
}
case(ENET_TX):
{
EnetTxFrequency = (uint32_t) src_clk; // convert target clock directly to frequency
break;
}
case(BASE_USB1_CLK):
{
USB1Frequency = src_freq;
break;
}
case(BASE_M4_CLK):
{
M4Frequency = src_freq;
break;
}
case(BASE_SPIFI_CLK):
{
SPIFIFrequency = src_freq;
break;
}
case(BASE_SPI_CLK):
{
SPIFrequency = src_freq;
break;
}
case(BASE_PHY_RX_CLK):
{
EnetRxFrequency = src_freq;
break;
}
case(BASE_PHY_TX_CLK):
{
EnetTxFrequency = src_freq;
break;
}
case(BASE_VPB1_CLK):
{
VPB1Frequency = src_freq;
break;
}
case(BASE_VPB3_CLK):
{
VPB3Frequency = src_freq;
break;
}
case(BASE_LCD_CLK):
{
LCDFrequency = src_freq;
break;
}
case (BASE_VADC_CLK) :
{
VADCFrequency = src_freq;
break;
}
case(BASE_SDIO_CLK):
{
SDIOFrequency = src_freq;
break;
}
case(BASE_SSP0_CLK):
{
SSP0Frequency = src_freq;
break;
}
case(BASE_SSP1_CLK):
{
SSP1Frequency = src_freq;
break;
}
case(BASE_UART0_CLK):
{
UART0Frequency = src_freq;
break;
}
case(BASE_UART1_CLK):
{
UART1Frequency = src_freq;
break;
}
case(BASE_UART2_CLK):
{
UART2Frequency = src_freq;
break;
}
case(BASE_UART3_CLK):
{
UART3Frequency = src_freq;
break;
}
case(BASE_AOTEST_CLK):
{
AOTESTFrequency = src_freq;
break;
}
case(BASE_ISO_TCK):
{
ISOFrequency = src_freq;
break;
}
case(BASE_BSR_TCK):
{
BSRFrequency = src_freq;
break;
}
case(BASE_CLK_TEST):
{
CLK_TESTFrequency = src_freq;
break;
}
case(BASE_APLL_CLK): //New in Falcon
{
APLLFrequency = src_freq;
break;
}
case(BASE_SPARE0_CLK): //New in Falcon
{
SPARE0Frequency = src_freq;
break;
}
case(BASE_SPARE1_CLK): //New in Falcon
{
SPARE1Frequency = src_freq;
break;
}
default:
break;
}
if(target_clk<200)
{
target_clk_adr = (uint32_t) &LPC_CGU->IDIVA_CTRL + (target_clk-2)*4;
*(uint32_t *)target_clk_adr = (src_clk<<24) | (auto_block<<11);
}
}
/**
* Get Clock Frequency
*
* @param source clock
* @return frequency
*
* @brief returns the current frequency of a base clock
*/
uint32_t GetClockFrequency(CLKSRC_Type src_clk)
{
switch(src_clk)
{
case(SRC_OSC32K):
return RTC_CLK;
case(SRC_IRC):
return IRC_OSC;
case(SRC_ENET_RX_CLK):
return EnetRxFrequency;
case(SRC_ENET_TX_CLK):
return EnetTxFrequency;
case(SRC_EXT_TCK):
return EXTFrequency;
case(SRC_XTAL):
return XtalFrequency;
case(SRC_PL550M_0):
return PL550Frequency;
case(SRC_PL550M_FRAC): //New in Falcon
return PL550FracFrequency;
case(SRC_PL160M_0):
return PL160M_0Frequency;
case(SRC_PL160M_1):
return PL160M_1Frequency;
case(SRC_PL160M_2):
return PL160M_2Frequency;
case(SRC_IDIV_0):
return IDIVAFrequency;
case(SRC_IDIV_1):
return IDIVBFrequency;
case(SRC_IDIV_2):
return IDIVCFrequency;
case(SRC_IDIV_3):
return IDIVDFrequency;
case(SRC_IDIV_4):
return IDIVEFrequency;
default:
return 0;
}
}
/**
* Set PL160M
*
* @param source clock, desired frequency
* @return none
*
* @brief Setup the PL160M PLL
* If frequency equals 0 then disable PLL
* Integer mode only (fbsel=1, direct=0)
* Fclkout = M * Fclkin/N
* Fcc0 = 2 * P * Fclkout = 2 * P * M * Fclkin/N
* msel+1 = feedback-divider value M (1 to 2^15)
* nsel+1 = pre-divider value N (1 to 2^8)
* psel+1 = post-divider value P(x2) (1 to 2^5)
*/
void SetPL160M(CLKSRC_Type src_clk, uint32_t mult)
{
uint32_t msel=0, nsel=0, psel=0, pval=1;
// EnableSourceClk(src_clk);
if(mult==0)
{
LPC_CGU->PLL1_CTRL |= PD_ENABLE; // Power down PLL
DisableSourceClk(src_clk);
}
else
{
EnableSourceClk(src_clk);
switch(src_clk)
{
case(SRC_OSC32K):
PL160M_0Frequency = mult * RTC_CLK;
break;
case(SRC_IRC):
PL160M_0Frequency = mult * IRC_OSC;
break;
case(SRC_ENET_RX_CLK):
PL160M_0Frequency = mult * EnetRxFrequency;
break;
case(SRC_ENET_TX_CLK):
PL160M_0Frequency = mult * EnetTxFrequency;
break;
case(SRC_EXT_TCK):
PL160M_0Frequency = mult * EXTFrequency;
break;
case(SRC_XTAL):
PL160M_0Frequency = mult * XtalFrequency;
break;
default:
PL160M_0Frequency = mult * IRC_OSC;
break;
}
// CCO must be in range of 156 - 320 MHz
// Increase P if FCCO is too low.
msel = mult-1;
//psel is encoded such that 0=1, 1=2, 2=4, 3=8
while(2*(pval)*PL160M_0Frequency < 156000000) {
psel++;
pval*=2;
}
// if(2*(pval)*PL160M_0Frequency > 320000000) {
// THIS IS OUT OF RANGE!!!
// HOW DO WE ASSERT IN SAMPLE CODE?
// __breakpoint(0);
// }
LPC_CGU->PLL1_CTRL = (src_clk<<24) | (msel<<16) | (nsel<<12) | (psel<<8) | FBSEL;
while((LPC_CGU->PLL1_STAT&1) == 0x0); // Wait for PLL lock
}
}
/**
* Set PLL USB (PL550M)
*
* @param enable
* @return none
*
* @brief Setup the USB PLL to 480 MHz
* If enable equals 0 then disable PLL
* Only clock sources IRC and XTAL are valid
* Mode1a only: Normal operating mode without post- and pre-divider
* Fclkout = 2 * M * Fclkin
* msel+1 = feedback-divider value M (1 to 2^15)
*/
void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable)
{
if(!enable)
{
LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL
}
else
{
// Setup PLL550 to generate 480MHz from 12 MHz crystal
LPC_CGU->PLL0USB_CTRL |= PD_ENABLE; // Power down PLL
// P N
LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);
// SELP SELI SELR MDEC
LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);
LPC_CGU->PLL0USB_CTRL =(SRC_XTAL<<24) | (0x3<<2) | CLKEN;
// Set the USB0 clock source to PLL550 (480MHz)
LPC_CGU->BASE_USB0_CLK = (0<<0) | (1<<11) | (SRC_PL550M_0<<24);
while((LPC_CGU->PLL0USB_STAT&1) == 0x0); // Wait for PLL lock
}
PL550Frequency = 480000000UL;
}
/**
* Enable source clock pheripheral
*
* @param clock source
* @return none
*
* @brief Enable clock specific peripherals
*/
void EnableSourceClk(CLKSRC_Type src_clk)
{
uint32_t i=0;
if(src_clk == SRC_OSC32K)
{
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset
LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k
}
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC3); // enet_rx_clk on PC_0 func 3
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC0); // enet_tx_clk on P1_19 func 0
if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1))
{
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M
for(i=0;i<0xFFFF;i++);
}
}
/**
* Disable source clock pheripheral
*
* @param clock source
* @return none
*
* @brief Disable clock specific peripherals
*/
void DisableSourceClk(CLKSRC_Type src_clk)
{
uint32_t i=0;
if(src_clk == SRC_OSC32K)
{
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k
LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode
}
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC0); // nc on PC_0 func 0
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC2); // nc on P1_19 func 2
if(src_clk == SRC_XTAL)
{
LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M
for(i=0;i<0xFFFF;i++);
}
}

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/***********************************************************************
* $Id: system_LPC43xx.h 8242 2011-10-11 15:15:25Z nxp28536 $
*
* Project: LPC43xx Common
*
* Description:
* CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the NXP LPC43xx Device Series
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SYSTEM_LPC18xx_H
#define __SYSTEM_LPC18xx_H
#include <stdint.h>
#include "scu.h"
#ifdef __cplusplus
extern "C" {
#endif
#define BUTTON0 !((LPC_GPIO3->PIN>>6)&1) // P6.10
#define BUTTON1 !((LPC_GPIO2->PIN>>0)&1) // P4.0
/*----------------------------------------------------------------------------
Clock Variable definitions
DO NOT SET MANUALLY, SET WITH SetClock AND SetPL160M
*----------------------------------------------------------------------------*/
extern uint32_t XtalFrequency;
extern uint32_t PL160M_0Frequency;
extern uint32_t PL160M_1Frequency;
extern uint32_t PL160M_2Frequency;
extern uint32_t PL550Frequency;
extern uint32_t PL550FracFrequency; //New in Falcon
extern uint32_t IDIVAFrequency;
extern uint32_t IDIVBFrequency;
extern uint32_t IDIVCFrequency;
extern uint32_t IDIVDFrequency;
extern uint32_t IDIVEFrequency;
extern uint32_t M0Frequency;
extern uint32_t USB1Frequency;
extern uint32_t M4Frequency;
extern uint32_t SPIFIFrequency;
extern uint32_t SPIFrequency;
extern uint32_t EnetRxFrequency;
extern uint32_t EnetTxFrequency;
extern uint32_t EXTFrequency;
extern uint32_t VPB1Frequency;
extern uint32_t VPB3Frequency;
extern uint32_t LCDFrequency;
extern uint32_t SCIFrequency;
extern uint32_t SDIOFrequency;
extern uint32_t SSP0Frequency;
extern uint32_t SSP1Frequency;
extern uint32_t UART0Frequency;
extern uint32_t UART1Frequency;
extern uint32_t UART2Frequency;
extern uint32_t UART3Frequency;
extern uint32_t OUTFrequency;
extern uint32_t AOTESTFrequency;
extern uint32_t ISOFrequency;
extern uint32_t BSRFrequency;
extern uint32_t CLK_TESTFrequency;
extern uint32_t APLLFrequency;
extern uint32_t SPARE0Frequency;
extern uint32_t SPARE1Frequency;
typedef enum CLKDIV
{
DIV1 = 1,
DIV2 = 2,
DIV4 = 4,
DIV8 = 8,
DIV16 = 16,
DIV256 = 256,
} CLKDIV_Type;
typedef enum CLKSRC
{
SRC_OSC32K = 0,
SRC_IRC = 1,
SRC_ENET_RX_CLK = 2,
SRC_ENET_TX_CLK = 3,
SRC_EXT_TCK = 4,
RESERVED = 5, // Do NOT use
SRC_XTAL = 6,
SRC_PL550M_0 = 7,
SRC_PL550M_FRAC = 8, //New in Falcon
SRC_PL160M_0 = 9,
SRC_PL160M_1 = 10,
SRC_PL160M_2 = 11,
SRC_IDIV_0 = 12,
SRC_IDIV_1 = 13,
SRC_IDIV_2 = 14,
SRC_IDIV_3 = 15,
SRC_IDIV_4 = 16,
NOT_DEFINED = 0xFFFFFFF, // Force a signed int enum, so every possible frequency can be entered
} CLKSRC_Type;
typedef enum CLKBASE
{
PL550M = 0, //PL550Frac is new, should be added???
PL160M = 1,
IDIVA_4 = 2,
IDIVB_16 = 3,
IDIVC_16 = 4,
IDIVD_16 = 5,
IDIVE_256 = 6,
BASE_SAFE_CLK = 7,
BASE_USB0_CLK = 8,
BASE_M0_CLK = 9,
BASE_USB1_CLK = 10,
BASE_M4_CLK = 11,
BASE_SPIFI_CLK = 12,
BASE_SPI_CLK = 13,
BASE_PHY_RX_CLK = 14,
BASE_PHY_TX_CLK = 15,
BASE_VPB1_CLK = 16,
BASE_VPB3_CLK = 17,
BASE_LCD_CLK = 18,
BASE_VADC_CLK = 19, //New
BASE_SDIO_CLK = 20,
BASE_SSP0_CLK = 21,
BASE_SSP1_CLK = 22,
BASE_UART0_CLK = 23,
BASE_UART1_CLK = 24,
BASE_UART2_CLK = 25,
BASE_UART3_CLK = 26,
BASE_OUT_CLK = 27,
BASE_AOTEST_CLK = 28,
BASE_ISO_TCK = 29,
BASE_BSR_TCK = 30,
BASE_CLK_TEST = 31,
BASE_APLL_CLK = 32, //New in Falcon
BASE_SPARE0_CLK = 33, //New in Falcon
BASE_SPARE1_CLK = 34, //New in Falcon
XTAL = 253,
ENET_RX = 254,
ENET_TX = 255,
}CLKBASE_Type;
// PL550M
#define MODE1A (0x3<<2) // Normal operating mode without post-divider and without pre-divider
#define MODE1B (0x2<<2) // Normal operating mode with post-divider and without pre-divider
#define MODE1C (0x1<<2) // Normal operating mode without post-divider and with pre-divider
#define MODE1D (0x0<<2) // Normal operating mode with post-divider and with pre-divider.
#define BYPASSOFF (0<<1)
#define CLKEN (1<<4)
// PL160M
#define FBSEL (1<<6)
#define MSEL_FBDIV(n) (n<<16) // MSEL = feedback-divider value 2*M (1 to 2^15)
#define NSEL_PREDIV(n) (n<<12) // NSEL = pre-divider value N (1 to 2^8)
#define PSEL_POSTDIV(n) (n<<8) // PSEL = post-divider value P*2 (1 to 2^5)
// Generic clock properties
#define AUTO_BLOCK (1<<11)
#define PD_ENABLE (1<<0)
extern void SystemInit(void);
extern void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div);
extern void SetPL160M(CLKSRC_Type src_clk, uint32_t mult);
extern void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable);
extern void EnableSourceClk(CLKSRC_Type src_clk);
extern void DisableSourceClk(CLKSRC_Type src_clk);
extern void IOInit(void);
extern uint32_t GetClockFrequency(CLKSRC_Type src_clk);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC43xx_H */

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/***********************************************************************
* $Id: type.h 8242 2011-10-11 15:15:25Z nxp28536 $
*
* Project: LPC43xx Common
*
* Description:
* Type definition Header file for NXP LPC4300 Family
* Microprocessors
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __TYPE_H__
#define __TYPE_H__
#ifndef NULL
#define NULL ((void *)0)
#endif
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#define ABS(value) (value<0 ? -value : value)
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned int BOOL;
typedef union _BITS
{
unsigned char value;
struct _bits
{
unsigned char bit0:1;
unsigned char bit1:1;
unsigned char bit2:1;
unsigned char bit3:1;
unsigned char bit4:1;
unsigned char bit5:1;
unsigned char bit6:1;
unsigned char bit7:1;
}bits;
}BITS;
#endif /* __TYPE_H__ */