mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-12 00:57:44 -04:00
Style: remove tabs = spaces
This commit is contained in:
Alfred Gedeon
alfred gedeon
parent
be3a40d780
commit
050a87fe15
1 changed files with 817 additions and 777 deletions
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@ -22,7 +22,6 @@
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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@ -40,7 +39,7 @@
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/* Portasm includes. */
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#include "portasm.h"
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#if( configENABLE_TRUSTZONE == 1 )
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#if ( configENABLE_TRUSTZONE == 1 )
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/* Secure components includes. */
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#include "secure_context.h"
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#include "secure_init.h"
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@ -63,7 +62,7 @@
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* 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
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* configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
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*/
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#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
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#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
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#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
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#endif
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/*-----------------------------------------------------------*/
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@ -71,10 +70,10 @@
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/**
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* @brief Constants required to manipulate the NVIC.
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*/
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#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
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#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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@ -86,7 +85,8 @@
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/* Ensure the SysTick is clocked at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#else
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/* The way the SysTick is clocked is not modified in case it is not the
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/* The way the SysTick is clocked is not modified in case it is not the
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* same a the core. */
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#define portNVIC_SYSTICK_CLK_BIT ( 0 )
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#endif
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@ -95,7 +95,7 @@
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/**
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* @brief Constants required to manipulate the SCB.
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*/
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#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
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#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
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#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
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/*-----------------------------------------------------------*/
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@ -118,24 +118,24 @@
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/**
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* @brief Constants required to manipulate the MPU.
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*/
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#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
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#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
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#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
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#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
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#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
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#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
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#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
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#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
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#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
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#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
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#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
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#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
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#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
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#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
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#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
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#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
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#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
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#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
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#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
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#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
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#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
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#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
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#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
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#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
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#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
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#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
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@ -205,8 +205,9 @@
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*/
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#define portINITIAL_XPSR ( 0x01000000 )
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#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
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/**
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#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
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/**
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* @brief Initial EXC_RETURN value.
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*
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* FF FF FF FD
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@ -222,7 +223,8 @@
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*/
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#define portINITIAL_EXC_RETURN ( 0xfffffffd )
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#else
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/**
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/**
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* @brief Initial EXC_RETURN value.
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*
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* FF FF FF BC
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@ -285,15 +287,17 @@
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*/
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static void prvTaskExitError( void );
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#if( configENABLE_MPU == 1 )
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/**
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#if ( configENABLE_MPU == 1 )
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/**
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* @brief Setup the Memory Protection Unit (MPU).
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*/
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static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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#endif /* configENABLE_MPU */
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#if( configENABLE_FPU == 1 )
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/**
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#if ( configENABLE_FPU == 1 )
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/**
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* @brief Setup the Floating Point Unit (FPU).
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*/
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static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
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@ -338,45 +342,47 @@ void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
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/**
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* @brief C part of SVC handler.
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*/
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portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
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portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
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/*-----------------------------------------------------------*/
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/**
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* @brief Each task maintains its own interrupt status in the critical nesting
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* variable.
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*/
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static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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#if( configENABLE_TRUSTZONE == 1 )
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/**
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#if ( configENABLE_TRUSTZONE == 1 )
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/**
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* @brief Saved as part of the task context to indicate which context the
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* task is using on the secure side.
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*/
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portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
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PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
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#endif /* configENABLE_TRUSTZONE */
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#if( configUSE_TICKLESS_IDLE == 1 )
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/**
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#if ( configUSE_TICKLESS_IDLE == 1 )
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/**
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* @brief The number of SysTick increments that make up one tick period.
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*/
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static uint32_t ulTimerCountsForOneTick = 0;
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PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
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/**
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/**
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* @brief The maximum number of tick periods that can be suppressed is
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* limited by the 24 bit resolution of the SysTick timer.
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*/
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static uint32_t xMaximumPossibleSuppressedTicks = 0;
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PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
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/**
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/**
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* @brief Compensate for the CPU cycles that pass while the SysTick is
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* stopped (low power functionality only).
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*/
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static uint32_t ulStoppedTimerCompensation = 0;
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PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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#if( configUSE_TICKLESS_IDLE == 1 )
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__attribute__(( weak )) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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#if ( configUSE_TICKLESS_IDLE == 1 )
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__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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{
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uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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TickType_t xModifiableIdleTime;
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@ -397,6 +403,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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* tick periods. -1 is used because this code will execute part way
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* through one of the tick periods. */
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ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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if( ulReloadValue > ulStoppedTimerCompensation )
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{
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ulReloadValue -= ulStoppedTimerCompensation;
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@ -404,9 +411,9 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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/* Enter a critical section but don't use the taskENTER_CRITICAL()
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* method as that will mask interrupts that should exit sleep mode. */
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__asm volatile( "cpsid i" ::: "memory" );
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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__asm volatile ( "cpsid i" ::: "memory" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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/* If a context switch is pending or a task is waiting for the scheduler
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* to be un-suspended then abandon the low power entry. */
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@ -425,7 +432,7 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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/* Re-enable interrupts - see comments above the cpsid instruction()
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* above. */
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__asm volatile( "cpsie i" ::: "memory" );
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__asm volatile ( "cpsie i" ::: "memory" );
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}
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else
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{
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@ -447,28 +454,30 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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* so a copy is taken. */
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xModifiableIdleTime = xExpectedIdleTime;
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configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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if( xModifiableIdleTime > 0 )
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{
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__asm volatile( "dsb" ::: "memory" );
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__asm volatile( "wfi" );
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__asm volatile( "isb" );
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__asm volatile ( "dsb" ::: "memory" );
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__asm volatile ( "wfi" );
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__asm volatile ( "isb" );
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}
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configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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/* Re-enable interrupts to allow the interrupt that brought the MCU
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* out of sleep mode to execute immediately. See comments above
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* the cpsid instruction above. */
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__asm volatile( "cpsie i" ::: "memory" );
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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__asm volatile ( "cpsie i" ::: "memory" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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/* Disable interrupts again because the clock is about to be stopped
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* and interrupts that execute while the clock is stopped will
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* increase any slippage between the time maintained by the RTOS and
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* calendar time. */
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__asm volatile( "cpsid i" ::: "memory" );
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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__asm volatile ( "cpsid i" ::: "memory" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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/* Disable the SysTick clock without reading the
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* portNVIC_SYSTICK_CTRL_REG register to ensure the
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@ -535,16 +544,16 @@ static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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/* Exit with interrupts enabled. */
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__asm volatile( "cpsie i" ::: "memory" );
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__asm volatile ( "cpsie i" ::: "memory" );
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}
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}
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#endif /* configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
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__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
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{
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/* Calculate the constants required to configure the tick interrupt. */
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#if( configUSE_TICKLESS_IDLE == 1 )
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#if ( configUSE_TICKLESS_IDLE == 1 )
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{
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ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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@ -557,14 +566,14 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNC
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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}
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/*-----------------------------------------------------------*/
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static void prvTaskExitError( void )
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{
|
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volatile uint32_t ulDummy = 0UL;
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volatile uint32_t ulDummy = 0UL;
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|
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/* A function that implements a task must not exit or attempt to return to
|
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* its caller as there is nothing to return to. If a task wants to exit it
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@ -587,10 +596,11 @@ volatile uint32_t ulDummy = 0UL;
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}
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/*-----------------------------------------------------------*/
|
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|
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#if( configENABLE_MPU == 1 )
|
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#if ( configENABLE_MPU == 1 )
|
||||
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
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{
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#if defined( __ARMCC_VERSION )
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|
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/* Declaration when these variable are defined in code instead of being
|
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* exported from linker scripts. */
|
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extern uint32_t * __privileged_functions_start__;
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|
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@ -601,7 +611,7 @@ volatile uint32_t ulDummy = 0UL;
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extern uint32_t * __unprivileged_flash_end__;
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||||
extern uint32_t * __privileged_sram_start__;
|
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extern uint32_t * __privileged_sram_end__;
|
||||
#else
|
||||
#else /* if defined( __ARMCC_VERSION ) */
|
||||
/* Declaration when these variable are exported from linker scripts. */
|
||||
extern uint32_t __privileged_functions_start__[];
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extern uint32_t __privileged_functions_end__[];
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|
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@ -672,10 +682,10 @@ volatile uint32_t ulDummy = 0UL;
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#endif /* configENABLE_MPU */
|
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/*-----------------------------------------------------------*/
|
||||
|
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#if( configENABLE_FPU == 1 )
|
||||
#if ( configENABLE_FPU == 1 )
|
||||
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
|
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{
|
||||
#if( configENABLE_TRUSTZONE == 1 )
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#if ( configENABLE_TRUSTZONE == 1 )
|
||||
{
|
||||
/* Enable non-secure access to the FPU. */
|
||||
SecureInit_EnableNSFPUAccess();
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|
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@ -704,8 +714,8 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */
|
|||
|
||||
/* Barriers are normally not required but do ensure the code is
|
||||
* completely within the specified behaviour for the architecture. */
|
||||
__asm volatile( "dsb" ::: "memory" );
|
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__asm volatile( "isb" );
|
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__asm volatile ( "dsb" ::: "memory" );
|
||||
__asm volatile ( "isb" );
|
||||
}
|
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/*-----------------------------------------------------------*/
|
||||
|
||||
|
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@ -716,8 +726,8 @@ void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
|
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|
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/* Barriers are normally not required but do ensure the code is
|
||||
* completely within the specified behaviour for the architecture. */
|
||||
__asm volatile( "dsb" ::: "memory" );
|
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__asm volatile( "isb" );
|
||||
__asm volatile ( "dsb" ::: "memory" );
|
||||
__asm volatile ( "isb" );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
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@ -735,7 +745,7 @@ void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
|
|||
|
||||
void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulPreviousMask;
|
||||
uint32_t ulPreviousMask;
|
||||
|
||||
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
{
|
||||
|
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@ -750,10 +760,11 @@ uint32_t ulPreviousMask;
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
|
||||
void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
|
||||
{
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
#if defined( __ARMCC_VERSION )
|
||||
|
||||
/* Declaration when these variable are defined in code instead of being
|
||||
* exported from linker scripts. */
|
||||
extern uint32_t * __syscalls_flash_start__;
|
||||
|
|
@ -763,33 +774,33 @@ void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION
|
|||
extern uint32_t __syscalls_flash_start__[];
|
||||
extern uint32_t __syscalls_flash_end__[];
|
||||
#endif /* defined( __ARMCC_VERSION ) */
|
||||
#endif /* configENABLE_MPU */
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
uint32_t ulPC;
|
||||
uint32_t ulPC;
|
||||
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
uint32_t ulR0;
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
uint32_t ulControl, ulIsTaskPrivileged;
|
||||
#endif /* configENABLE_MPU */
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
uint8_t ucSVCNumber;
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
uint8_t ucSVCNumber;
|
||||
|
||||
/* Register are stored on the stack in the following order - R0, R1, R2, R3,
|
||||
* R12, LR, PC, xPSR. */
|
||||
ulPC = pulCallerStackAddress[ 6 ];
|
||||
ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
|
||||
ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
|
||||
|
||||
switch( ucSVCNumber )
|
||||
{
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
case portSVC_ALLOCATE_SECURE_CONTEXT:
|
||||
{
|
||||
|
||||
/* R0 contains the stack size passed as parameter to the
|
||||
* vPortAllocateSecureContext function. */
|
||||
ulR0 = pulCallerStackAddress[ 0 ];
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Read the CONTROL register value. */
|
||||
__asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
|
||||
|
|
@ -801,7 +812,7 @@ uint8_t ucSVCNumber;
|
|||
/* Allocate and load a context for the secure task. */
|
||||
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
|
||||
}
|
||||
#else
|
||||
#else /* if ( configENABLE_MPU == 1 ) */
|
||||
{
|
||||
/* Allocate and load a context for the secure task. */
|
||||
xSecureContext = SecureContext_AllocateContext( ulR0 );
|
||||
|
|
@ -810,23 +821,19 @@ uint8_t ucSVCNumber;
|
|||
|
||||
configASSERT( xSecureContext != NULL );
|
||||
SecureContext_LoadContext( xSecureContext );
|
||||
}
|
||||
break;
|
||||
|
||||
case portSVC_FREE_SECURE_CONTEXT:
|
||||
{
|
||||
/* R0 contains the secure context handle to be freed. */
|
||||
ulR0 = pulCallerStackAddress[ 0 ];
|
||||
|
||||
/* Free the secure context. */
|
||||
SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
|
||||
}
|
||||
break;
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
|
||||
case portSVC_START_SCHEDULER:
|
||||
{
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
{
|
||||
/* De-prioritize the non-secure exceptions so that the
|
||||
* non-secure pendSV runs at the lowest priority. */
|
||||
|
|
@ -837,7 +844,7 @@ uint8_t ucSVCNumber;
|
|||
}
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
|
||||
#if( configENABLE_FPU == 1 )
|
||||
#if ( configENABLE_FPU == 1 )
|
||||
{
|
||||
/* Setup the Floating Point Unit (FPU). */
|
||||
prvSetupFPU();
|
||||
|
|
@ -847,41 +854,44 @@ uint8_t ucSVCNumber;
|
|||
/* Setup the context of the first task so that the first task starts
|
||||
* executing. */
|
||||
vRestoreContextOfFirstTask();
|
||||
}
|
||||
break;
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
case portSVC_RAISE_PRIVILEGE:
|
||||
{
|
||||
|
||||
/* Only raise the privilege, if the svc was raised from any of
|
||||
* the system calls. */
|
||||
if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
|
||||
ulPC <= ( uint32_t ) __syscalls_flash_end__ )
|
||||
if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
|
||||
( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
|
||||
{
|
||||
vRaisePrivilege();
|
||||
}
|
||||
}
|
||||
break;
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
default:
|
||||
{
|
||||
/* Incorrect SVC call. */
|
||||
configASSERT( pdFALSE );
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
StackType_t * pxEndOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters,
|
||||
BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
|
||||
#else
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
StackType_t * pxEndOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters ) /* PRIVILEGED_FUNCTION */
|
||||
#endif /* configENABLE_MPU */
|
||||
{
|
||||
/* Simulate the stack frame as it would be created by a context switch
|
||||
* interrupt. */
|
||||
#if( portPRELOAD_REGISTERS == 0 )
|
||||
#if ( portPRELOAD_REGISTERS == 0 )
|
||||
{
|
||||
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
|
||||
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
||||
|
|
@ -894,9 +904,10 @@ uint8_t ucSVCNumber;
|
|||
pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
|
||||
*pxTopOfStack = portINITIAL_EXC_RETURN;
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
pxTopOfStack--;
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
|
||||
|
|
@ -911,7 +922,7 @@ uint8_t ucSVCNumber;
|
|||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
|
||||
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
{
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
|
||||
|
|
@ -955,9 +966,10 @@ uint8_t ucSVCNumber;
|
|||
pxTopOfStack--;
|
||||
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
pxTopOfStack--;
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
|
||||
|
|
@ -972,7 +984,7 @@ uint8_t ucSVCNumber;
|
|||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
|
||||
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
{
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
|
||||
|
|
@ -988,10 +1000,10 @@ uint8_t ucSVCNumber;
|
|||
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
|
||||
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
||||
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
|
||||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
prvSetupMPU();
|
||||
|
|
@ -1030,11 +1042,24 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( configENABLE_MPU == 1 )
|
||||
void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
|
||||
const struct xMEMORY_REGION * const xRegions,
|
||||
StackType_t * pxBottomOfStack,
|
||||
uint32_t ulStackDepth )
|
||||
{
|
||||
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
|
||||
int32_t lIndex = 0;
|
||||
#if defined( __ARMCC_VERSION )
|
||||
/* Declaration when these variable are defined in code instead of being
|
||||
* exported from linker scripts. */
|
||||
extern uint32_t * __privileged_sram_start__;
|
||||
extern uint32_t * __privileged_sram_end__;
|
||||
#else
|
||||
/* Declaration when these variable are exported from linker scripts. */
|
||||
extern uint32_t __privileged_sram_start__[];
|
||||
extern uint32_t __privileged_sram_end__[];
|
||||
#endif /* defined( __ARMCC_VERSION ) */
|
||||
|
||||
/* Setup MAIR0. */
|
||||
xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
|
||||
|
|
@ -1046,9 +1071,23 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
* the stack region has already been configured. */
|
||||
if( ulStackDepth > 0 )
|
||||
{
|
||||
/* Define the region that allows access to the stack. */
|
||||
ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
|
||||
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
|
||||
ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
|
||||
|
||||
/* If the stack is within the privileged SRAM, do not protect it
|
||||
* using a separate MPU region. This is needed because privileged
|
||||
* SRAM is already protected using an MPU region and ARMv8-M does
|
||||
* not allow overlapping MPU regions. */
|
||||
if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ &&
|
||||
ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
|
||||
xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Define the region that allows access to the stack. */
|
||||
ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
|
||||
ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
|
||||
|
||||
xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
|
||||
|
|
@ -1060,6 +1099,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
( portMPU_RLAR_ATTR_INDEX0 ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
}
|
||||
}
|
||||
|
||||
/* User supplied configurable regions. */
|
||||
for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
|
||||
|
|
@ -1127,13 +1167,13 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
|
||||
BaseType_t xPortIsInsideInterrupt( void )
|
||||
{
|
||||
uint32_t ulCurrentInterrupt;
|
||||
BaseType_t xReturn;
|
||||
uint32_t ulCurrentInterrupt;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* Obtain the number of the currently executing interrupt. Interrupt Program
|
||||
* Status Register (IPSR) holds the exception number of the currently-executing
|
||||
* exception or zero for Thread mode.*/
|
||||
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
||||
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
|
||||
|
||||
if( ulCurrentInterrupt == 0 )
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue