mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 10:08:33 -04:00
This commit is contained in:
parent
946da76519
commit
05023971cb
389 changed files with 11479 additions and 464 deletions
297
Demo/CORTEX_LM3S316_IAR/hw_include/startup.c
Normal file
297
Demo/CORTEX_LM3S316_IAR/hw_include/startup.c
Normal file
|
@ -0,0 +1,297 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// startup.c - Boot code for Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's Stellaris Family of microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 635 of the Stellaris Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Enable the IAR extensions for this source file.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#pragma language=extended
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Forward declaration of the default fault handlers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void ResetISR(void);
|
||||
static void NmiSR(void);
|
||||
static void FaultISR(void);
|
||||
static void IntDefaultHandler(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External declaration for the interrupt handler used by the application.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void xPortPendSVHandler(void);
|
||||
extern void xPortSysTickHandler(void);
|
||||
extern void vUART_ISR( void );
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The entry point for the application.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void main(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Reserve space for the system stack.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef STACK_SIZE
|
||||
#define STACK_SIZE 50
|
||||
#endif
|
||||
static unsigned long pulStack[STACK_SIZE] = {
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb,
|
||||
0xbbbbbbbb };
|
||||
//*****************************************************************************
|
||||
//
|
||||
// A union that describes the entries of the vector table. The union is needed
|
||||
// since the first entry is the stack pointer and the remainder are function
|
||||
// pointers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef union
|
||||
{
|
||||
void (*pfnHandler)(void);
|
||||
unsigned long ulPtr;
|
||||
}
|
||||
uVectorEntry;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
// must be placed on this to ensure that it ends up at physical address
|
||||
// 0x0000.0000.
|
||||
//
|
||||
//*****************************************************************************
|
||||
__root const uVectorEntry g_pfnVectors[] @ "INTVEC" =
|
||||
{
|
||||
{ .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },
|
||||
// The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NmiSR, // The NMI handler
|
||||
FaultISR, // The hard fault handler
|
||||
IntDefaultHandler, // The MPU fault handler
|
||||
IntDefaultHandler, // The bus fault handler
|
||||
IntDefaultHandler, // The usage fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
IntDefaultHandler, // SVCall handler
|
||||
IntDefaultHandler, // Debug monitor handler
|
||||
0, // Reserved
|
||||
xPortPendSVHandler, // The PendSV handler
|
||||
xPortSysTickHandler, // The SysTick handler
|
||||
IntDefaultHandler, // GPIO Port A
|
||||
IntDefaultHandler, // GPIO Port B
|
||||
IntDefaultHandler, // GPIO Port C
|
||||
IntDefaultHandler, // GPIO Port D
|
||||
IntDefaultHandler, // GPIO Port E
|
||||
vUART_ISR, // UART0 Rx and Tx
|
||||
IntDefaultHandler, // UART1 Rx and Tx
|
||||
IntDefaultHandler, // SSI Rx and Tx
|
||||
IntDefaultHandler, // I2C Master and Slave
|
||||
IntDefaultHandler, // PWM Fault
|
||||
IntDefaultHandler, // PWM Generator 0
|
||||
IntDefaultHandler, // PWM Generator 1
|
||||
IntDefaultHandler, // PWM Generator 2
|
||||
0, // Reserved
|
||||
IntDefaultHandler, // ADC Sequence 0
|
||||
IntDefaultHandler, // ADC Sequence 1
|
||||
IntDefaultHandler, // ADC Sequence 2
|
||||
IntDefaultHandler, // ADC Sequence 3
|
||||
IntDefaultHandler, // Watchdog timer
|
||||
IntDefaultHandler, // Timer 0 subtimer A
|
||||
IntDefaultHandler, // Timer 0 subtimer B
|
||||
IntDefaultHandler, // Timer 1 subtimer A
|
||||
IntDefaultHandler, // Timer 1 subtimer B
|
||||
IntDefaultHandler, // Timer 2 subtimer A
|
||||
IntDefaultHandler, // Timer 2 subtimer B
|
||||
IntDefaultHandler, // Analog Comparator 0
|
||||
IntDefaultHandler, // Analog Comparator 1
|
||||
IntDefaultHandler, // Analog Comparator 2
|
||||
IntDefaultHandler, // System Control (PLL, OSC, BO)
|
||||
IntDefaultHandler // FLASH Control
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are constructs created by the linker, indicating where the
|
||||
// the "data" and "bss" segments reside in memory. The initializers for the
|
||||
// for the "data" segment resides immediately following the "text" segment.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#pragma segment="DATA_ID"
|
||||
#pragma segment="DATA_I"
|
||||
#pragma segment="DATA_Z"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is the code that gets called when the processor first starts execution
|
||||
// following a reset event. Only the absolutely necessary set is performed,
|
||||
// after which the application supplied entry() routine is called. Any fancy
|
||||
// actions (such as making decisions based on the reset cause register, and
|
||||
// resetting the bits in that register) are left solely in the hands of the
|
||||
// application.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
ResetISR(void)
|
||||
{
|
||||
unsigned long *pulSrc, *pulDest, *pulEnd;
|
||||
|
||||
//
|
||||
// Copy the data segment initializers from flash to SRAM.
|
||||
//
|
||||
pulSrc = __segment_begin("DATA_ID");
|
||||
pulDest = __segment_begin("DATA_I");
|
||||
pulEnd = __segment_end("DATA_I");
|
||||
while(pulDest < pulEnd)
|
||||
{
|
||||
*pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
//
|
||||
// Zero fill the bss segment.
|
||||
//
|
||||
pulDest = __segment_begin("DATA_Z");
|
||||
pulEnd = __segment_end("DATA_Z");
|
||||
while(pulDest < pulEnd)
|
||||
{
|
||||
*pulDest++ = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// Call the application's entry point.
|
||||
//
|
||||
main();
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is the code that gets called when the processor receives a NMI. This
|
||||
// simply enters an infinite loop, preserving the system state for examination
|
||||
// by a debugger.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static void
|
||||
NmiSR(void)
|
||||
{
|
||||
//
|
||||
// Enter an infinite loop.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is the code that gets called when the processor receives a fault
|
||||
// interrupt. This simply enters an infinite loop, preserving the system state
|
||||
// for examination by a debugger.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static void
|
||||
FaultISR(void)
|
||||
{
|
||||
//
|
||||
// Enter an infinite loop.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is the code that gets called when the processor receives an unexpected
|
||||
// interrupt. This simply enters an infinite loop, preserving the system state
|
||||
// for examination by a debugger.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static void
|
||||
IntDefaultHandler(void)
|
||||
{
|
||||
//
|
||||
// Go into an infinite loop.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
Loading…
Add table
Add a link
Reference in a new issue