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revert :: mostly go back to the default port definitions from RISCV

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This commit is contained in:
Shaba Abhiram 2020-04-20 17:56:22 -07:00
parent 49d03aedb2
commit 021e86659d
3 changed files with 641 additions and 608 deletions
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189
portable/GCC/RISC-V/port.c
View file

@ -2,22 +2,23 @@
* FreeRTOS Kernel V10.3.1 * FreeRTOS Kernel V10.3.1
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a copy of * Permission is hereby granted, free of charge, to any person obtaining a copy
* this software and associated documentation files (the "Software"), to deal in * of this software and associated documentation files (the "Software"), to deal
* the Software without restriction, including without limitation the rights to * in the Software without restriction, including without limitation the rights
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* the Software, and to permit persons to whom the Software is furnished to do so, * copies of the Software, and to permit persons to whom the Software is
* subject to the following conditions: * furnished to do so, subject to the following conditions:
* *
* The above copyright notice and this permission notice shall be included in all * The above copyright notice and this permission notice shall be included in
* copies or substantial portions of the Software. * all copies or substantial portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
* *
* http://www.FreeRTOS.org * http://www.FreeRTOS.org
* http://aws.amazon.com/freertos * http://aws.amazon.com/freertos
@ -31,8 +32,8 @@
/* Scheduler includes. */ /* Scheduler includes. */
#include "FreeRTOS.h" #include "FreeRTOS.h"
#include "task.h"
#include "portmacro.h" #include "portmacro.h"
#include "task.h"
/* Standard includes. */ /* Standard includes. */
#include "string.h" #include "string.h"
@ -58,22 +59,6 @@ debugger. */
#define portTASK_RETURN_ADDRESS prvTaskExitError #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif #endif
/* A variable is used to keep track of the critical section nesting. This
variable has to be stored as part of the task context and must be initialised to
a non zero value to ensure interrupts don't inadvertently become unmasked before
the scheduler starts. As it is stored as part of the task context it will
automatically be set to 0 when the first task is started. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* As of version 1.10, these addresses reflect the configuration of the
* emulated SoC of the Spike RISC-V emulator with respect to the
* Machine Timer Registers mtime and mtimecmp
*/
#define CLINT_BASE 0x2000000
volatile uint64_t* mtime = (uint64_t*)(CLINT_BASE + 0xbff8);
volatile uint64_t* timecmp = (uint64_t*)(CLINT_BASE + 0x4000);
/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS /* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
to use a statically allocated array as the interrupt stack. Alternative leave to use a statically allocated array as the interrupt stack. Alternative leave
configISR_STACK_SIZE_WORDS undefined and update the linker script so that a configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
@ -82,8 +67,11 @@ of the stack used by main. Using the linker script method will repurpose the
stack that was used by main before the scheduler was started for use as the stack that was used by main before the scheduler was started for use as the
interrupt stack after the scheduler has started. */ interrupt stack after the scheduler has started. */
#ifdef configISR_STACK_SIZE_WORDS #ifdef configISR_STACK_SIZE_WORDS
static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; static __attribute__((aligned(16)))
const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); StackType_t xISRStack[configISR_STACK_SIZE_WORDS] = {0};
const StackType_t xISRStackTop =
(StackType_t) &
(xISRStack[configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK]);
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
the task stacks, and so will legitimately appear in many positions within the task stacks, and so will legitimately appear in many positions within
@ -100,69 +88,15 @@ interrupt stack after the scheduler has started. */
* generate the tick interrupt. * generate the tick interrupt.
*/ */
void vPortSetupTimerInterrupt(void) __attribute__((weak)); void vPortSetupTimerInterrupt(void) __attribute__((weak));
/*
* Setup the timer to generate the tick interrupts.
*/
void vPortSetupTimer(void);
void vPortSysTickHandler(void);
/*
* Set the next interval for the timer
*/
static void prvSetNextTimerInterrupt(void);
/*
* Used to catch tasks that attempt to return from their implementing function.
*/
static void prvTaskExitError(void);
/*-----------------------------------------------------------*/
void prvTaskExitError(void)
{
/* A function that implements a task must not exit or attempt to return to
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT(uxCriticalNesting == ~0UL);
portDISABLE_INTERRUPTS();
for (;;)
;
}
/* Sets the next timer interrupt
* Reads current timer register and adds tickrate
* Does nothing if a Clint was not found in the hardware configuration string
* Using previous timer compare may fail if interrupts were disabled for a long
* time, which is likely for the very first interrupt. When that happens,
* compare timer + tickrate may already be behind current timer and prevent
* correctly programming the 2nd interrupt
*/
static void prvSetNextTimerInterrupt(void)
{
if (mtime && timecmp)
*timecmp = *mtime + (configTICK_CLOCK_HZ / configTICK_RATE_HZ);
}
/*-----------------------------------------------------------*/
/* Sets and enable the timer interrupt */
void vPortSetupTimer(void)
{
/* reuse existing routine */
prvSetNextTimerInterrupt();
/* Enable timer interupt */
__asm volatile("csrs mie,%0" ::"r"(0x80));
}
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Used to program the machine timer compare register. */ /* Used to program the machine timer compare register. */
uint64_t ullNextTime = 0ULL; uint64_t ullNextTime = 0ULL;
const uint64_t *pullNextTime = &ullNextTime; const uint64_t *pullNextTime = &ullNextTime;
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ const size_t uxTimerIncrementsForOneTick = (size_t)(
(configCPU_CLOCK_HZ) /
(configTICK_RATE_HZ)); /* Assumes increment won't go over 32-bits. */
uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t *pullMachineTimerCompareRegister = NULL; volatile uint64_t *pullMachineTimerCompareRegister = NULL;
@ -174,13 +108,17 @@ task stack, not the ISR stack). */
#warning This path not tested, or even compiled yet. #warning This path not tested, or even compiled yet.
static const uint8_t ucExpectedStackBytes[] = { static const uint8_t ucExpectedStackBytes[] = {
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE};
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) #define portCHECK_ISR_STACK() \
configASSERT((memcmp((void *)xISRStack, (void *)ucExpectedStackBytes, \
sizeof(ucExpectedStackBytes)) == 0))
#else #else
/* Define the function away. */ /* Define the function away. */
#define portCHECK_ISR_STACK() #define portCHECK_ISR_STACK()
@ -193,12 +131,17 @@ task stack, not the ISR stack). */
void vPortSetupTimerInterrupt(void) void vPortSetupTimerInterrupt(void)
{ {
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */ volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(
volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS ); (configMTIME_BASE_ADDRESS) +
4UL); /* 8-byte typer so high 32-bit word is 4 bytes up. */
volatile uint32_t *const pulTimeLow =
(volatile uint32_t *const)(configMTIME_BASE_ADDRESS);
volatile uint32_t ulHartId; volatile uint32_t ulHartId;
__asm volatile("csrr %0, mhartid" : "=r"(ulHartId)); __asm volatile("csrr %0, mhartid" : "=r"(ulHartId));
pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); pullMachineTimerCompareRegister =
(volatile uint64_t *)(ullMachineTimerCompareRegisterBase +
(ulHartId * sizeof(uint64_t)));
do do
{ {
@ -216,7 +159,8 @@ task stack, not the ISR stack). */
ullNextTime += (uint64_t)uxTimerIncrementsForOneTick; ullNextTime += (uint64_t)uxTimerIncrementsForOneTick;
} }
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 \
) */
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler(void) BaseType_t xPortStartScheduler(void)
@ -239,7 +183,8 @@ extern void xPortStartFirstTask( void );
#ifdef configISR_STACK_SIZE_WORDS #ifdef configISR_STACK_SIZE_WORDS
{ {
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); memset((void *)xISRStack, portISR_STACK_FILL_BYTE,
sizeof(xISRStack));
} }
#endif /* configISR_STACK_SIZE_WORDS */ #endif /* configISR_STACK_SIZE_WORDS */
} }
@ -252,9 +197,9 @@ extern void xPortStartFirstTask( void );
#if ((configMTIME_BASE_ADDRESS != 0) && (configMTIMECMP_BASE_ADDRESS != 0)) #if ((configMTIME_BASE_ADDRESS != 0) && (configMTIMECMP_BASE_ADDRESS != 0))
{ {
/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11 /* Enable mtime and external interrupts. 1<<7 for timer interrupt,
for external interrupt. _RB_ What happens here when mtime is not present as 1<<11 for external interrupt. _RB_ What happens here when mtime is not
with pulpino? */ present as with pulpino? */
__asm volatile("csrs mie, %0" ::"r"(0x880)); __asm volatile("csrs mie, %0" ::"r"(0x880));
} }
#else #else
@ -262,7 +207,8 @@ extern void xPortStartFirstTask( void );
/* Enable external interrupts. */ /* Enable external interrupts. */
__asm volatile("csrs mie, %0" ::"r"(0x800)); __asm volatile("csrs mie, %0" ::"r"(0x800));
} }
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS \
!= 0 ) */
xPortStartFirstTask(); xPortStartFirstTask();
@ -275,37 +221,6 @@ extern void xPortStartFirstTask( void );
void vPortEndScheduler(void) void vPortEndScheduler(void)
{ {
/* Not implemented. */ /* Not implemented. */
for( ;; ); for (;;)
} ;
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack,
TaskFunction_t pxCode, void *pvParameters)
{
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
register int *tp asm("x3");
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE)pxCode; /* Start address */
pxTopOfStack -= 22;
*pxTopOfStack = (portSTACK_TYPE)pvParameters; /* Register a0 */
pxTopOfStack -= 6;
*pxTopOfStack = (portSTACK_TYPE)tp; /* Register thread pointer */
pxTopOfStack -= 3;
*pxTopOfStack = (portSTACK_TYPE)prvTaskExitError; /* Register ra */
return pxTopOfStack;
}
void vPortSysTickHandler(void)
{
prvSetNextTimerInterrupt();
/* Increment the RTOS tick. */
if (xTaskIncrementTick() != pdFALSE)
{
vTaskSwitchContext();
}
} }

680
portable/GCC/RISC-V/portASM.S
View file

@ -1,325 +1,441 @@
/* /*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. * FreeRTOS Kernel V10.3.1
All rights reserved * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. * Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
This file is part of the FreeRTOS distribution and was contributed * the Software without restriction, including without limitation the rights to
to the project by Technolution B.V. (www.technolution.nl, * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
freertos-riscv@technolution.eu) under the terms of the FreeRTOS * the Software, and to permit persons to whom the Software is furnished to do so,
contributors license. * subject to the following conditions:
*
FreeRTOS is free software; you can redistribute it and/or modify it under * The above copyright notice and this permission notice shall be included in all
the terms of the GNU General Public License (version 2) as published by the * copies or substantial portions of the Software.
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*************************************************************************** * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
>>! NOTE: The modification to the GPL is included to allow you to !<< * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
>>! distribute a combined work that includes FreeRTOS without being !<< * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
>>! obliged to provide the source code for proprietary components !<< * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>>! outside of the FreeRTOS kernel. !<< * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*************************************************************************** *
* http://www.FreeRTOS.org
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY * http://aws.amazon.com/freertos
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS *
FOR A PARTICULAR PURPOSE. Full license text is available on the following * 1 tab == 4 spaces!
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry''s de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/ */
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
*
* + The code that is common to all RISC-V chips is implemented in
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
* portASM.S file because the same file is used no matter which RISC-V chip is
* in use.
*
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
* RISC-V chip that both includes a standard CLINT and does not add to the
* base set of RISC-V registers. There are additional
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
* that do not include a standard CLINT or do add to the base set of RISC-V
* registers.
*
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
* header file ensure the path to the correct header file is in the assembler's
* include path.
*
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
* that include a standard CLINT and do not add to the base set of RISC-V
* registers.
*
*/
#if __riscv_xlen == 64 #if __riscv_xlen == 64
# define STORE sd #define portWORD_SIZE 8
# define LOAD ld #define store_x sd
# define REGBYTES 8 #define load_x ld
#elif __riscv_xlen == 32
#define store_x sw
#define load_x lw
#define portWORD_SIZE 4
#else #else
# define STORE sw #error Assembler did not define __riscv_xlen
# define LOAD lw
# define REGBYTES 4
#endif #endif
/* Enable interrupts when returning from the handler */ #include "freertos_risc_v_chip_specific_extensions.h"
#define MSTATUS_PRV1 0x1880
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
definitions. */
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifdef portasmHAS_CLINT
#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#define portasmHAS_MTIME portasmHAS_CLINT
#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
#endif
#ifndef portasmHAS_MTIME
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef portasmHANDLE_INTERRUPT
#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef portasmHAS_SIFIVE_CLINT
#define portasmHAS_SIFIVE_CLINT 0
#endif
/* Only the standard core registers are stored by default. Any additional
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
at the top of this file. */
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
.global xPortStartFirstTask .global xPortStartFirstTask
.global portSAVE_CONTEXT .global freertos_risc_v_trap_handler
.global portRESTORE_CONTEXT .global pxPortInitialiseStack
.global TIMER_CMP_INT .extern pxCurrentTCB
.global vPortYield .extern ulPortTrapHandler
.global vTaskIncrementTick .extern vTaskSwitchContext
.global xExitStack .extern xTaskIncrementTick
.extern Timer_IRQHandler
.extern pullMachineTimerCompareRegister
.extern pullNextTime
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
.extern xISRStackTop
.extern portasmHANDLE_INTERRUPT
#define portCONTEXT_SIZE ( 30 * REGBYTES )
/*-----------------------------------------------------------*/
.align 8
.func
xPortStartFirstTask:
/* If there is a clint then interrupts can branch directly to the FreeRTOS
trap handler. Otherwise the interrupt controller will need to be configured
outside of this file. */
la t0, freertos_risc_v_trap_handler
csrw mtvec, t0
LOAD sp, pxCurrentTCB /* Load pxCurrentTCB. */
LOAD sp, 0( sp ) /* Read sp from first TCB member. */
LOAD x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
// portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
LOAD t0, 29 * REGBYTES( sp ) /* mstatus */
addi t0, t0, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
LOAD x5, 2 * REGBYTES( sp ) /* t0 */
LOAD x6, 3 * REGBYTES( sp ) /* t1 */
LOAD x7, 4 * REGBYTES( sp ) /* t2 */
LOAD x8, 5 * REGBYTES( sp ) /* s0/fp */
LOAD x9, 6 * REGBYTES( sp ) /* s1 */
LOAD x10, 7 * REGBYTES( sp ) /* a0 */
LOAD x11, 8 * REGBYTES( sp ) /* a1 */
LOAD x12, 9 * REGBYTES( sp ) /* a2 */
LOAD x13, 10 * REGBYTES( sp ) /* a3 */
LOAD x14, 11 * REGBYTES( sp ) /* a4 */
LOAD x15, 12 * REGBYTES( sp ) /* a5 */
LOAD x16, 13 * REGBYTES( sp ) /* a6 */
LOAD x17, 14 * REGBYTES( sp ) /* a7 */
LOAD x18, 15 * REGBYTES( sp ) /* s2 */
LOAD x19, 16 * REGBYTES( sp ) /* s3 */
LOAD x20, 17 * REGBYTES( sp ) /* s4 */
LOAD x21, 18 * REGBYTES( sp ) /* s5 */
LOAD x22, 19 * REGBYTES( sp ) /* s6 */
LOAD x23, 20 * REGBYTES( sp ) /* s7 */
LOAD x24, 21 * REGBYTES( sp ) /* s8 */
LOAD x25, 22 * REGBYTES( sp ) /* s9 */
LOAD x26, 23 * REGBYTES( sp ) /* s10 */
LOAD x27, 24 * REGBYTES( sp ) /* s11 */
LOAD x28, 25 * REGBYTES( sp ) /* t3 */
LOAD x29, 26 * REGBYTES( sp ) /* t4 */
LOAD x30, 27 * REGBYTES( sp ) /* t5 */
LOAD x31, 28 * REGBYTES( sp ) /* t6 */
addi sp, sp, portCONTEXT_SIZE
ret
.endfunc
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
.align 8 .align 8
.func .func
freertos_risc_v_trap_handler: freertos_risc_v_trap_handler:
addi sp, sp, -portCONTEXT_SIZE addi sp, sp, -portCONTEXT_SIZE
STORE x1, 1 * REGBYTES( sp ) store_x x1, 1 * portWORD_SIZE( sp )
STORE x5, 2 * REGBYTES( sp ) store_x x5, 2 * portWORD_SIZE( sp )
STORE x6, 3 * REGBYTES( sp ) store_x x6, 3 * portWORD_SIZE( sp )
STORE x7, 4 * REGBYTES( sp ) store_x x7, 4 * portWORD_SIZE( sp )
STORE x8, 5 * REGBYTES( sp ) store_x x8, 5 * portWORD_SIZE( sp )
STORE x9, 6 * REGBYTES( sp ) store_x x9, 6 * portWORD_SIZE( sp )
STORE x10, 7 * REGBYTES( sp ) store_x x10, 7 * portWORD_SIZE( sp )
STORE x11, 8 * REGBYTES( sp ) store_x x11, 8 * portWORD_SIZE( sp )
STORE x12, 9 * REGBYTES( sp ) store_x x12, 9 * portWORD_SIZE( sp )
STORE x13, 10 * REGBYTES( sp ) store_x x13, 10 * portWORD_SIZE( sp )
STORE x14, 11 * REGBYTES( sp ) store_x x14, 11 * portWORD_SIZE( sp )
STORE x15, 12 * REGBYTES( sp ) store_x x15, 12 * portWORD_SIZE( sp )
STORE x16, 13 * REGBYTES( sp ) store_x x16, 13 * portWORD_SIZE( sp )
STORE x17, 14 * REGBYTES( sp ) store_x x17, 14 * portWORD_SIZE( sp )
STORE x18, 15 * REGBYTES( sp ) store_x x18, 15 * portWORD_SIZE( sp )
STORE x19, 16 * REGBYTES( sp ) store_x x19, 16 * portWORD_SIZE( sp )
STORE x20, 17 * REGBYTES( sp ) store_x x20, 17 * portWORD_SIZE( sp )
STORE x21, 18 * REGBYTES( sp ) store_x x21, 18 * portWORD_SIZE( sp )
STORE x22, 19 * REGBYTES( sp ) store_x x22, 19 * portWORD_SIZE( sp )
STORE x23, 20 * REGBYTES( sp ) store_x x23, 20 * portWORD_SIZE( sp )
STORE x24, 21 * REGBYTES( sp ) store_x x24, 21 * portWORD_SIZE( sp )
STORE x25, 22 * REGBYTES( sp ) store_x x25, 22 * portWORD_SIZE( sp )
STORE x26, 23 * REGBYTES( sp ) store_x x26, 23 * portWORD_SIZE( sp )
STORE x27, 24 * REGBYTES( sp ) store_x x27, 24 * portWORD_SIZE( sp )
STORE x28, 25 * REGBYTES( sp ) store_x x28, 25 * portWORD_SIZE( sp )
STORE x29, 26 * REGBYTES( sp ) store_x x29, 26 * portWORD_SIZE( sp )
STORE x30, 27 * REGBYTES( sp ) store_x x30, 27 * portWORD_SIZE( sp )
STORE x31, 28 * REGBYTES( sp ) store_x x31, 28 * portWORD_SIZE( sp )
csrr t0, mstatus /* Required for MPIE bit. */ csrr t0, mstatus /* Required for MPIE bit. */
STORE t0, 29 * REGBYTES( sp ) store_x t0, 29 * portWORD_SIZE( sp )
// portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */ load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
STORE sp, 0( t0 ) /* Write sp to first TCB member. */ store_x sp, 0( t0 ) /* Write sp to first TCB member. */
csrr a0, mcause csrr a0, mcause
csrr a1, mepc csrr a1, mepc
test_if_asynchronous:
srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
/* Macro for saving task context */ handle_asynchronous:
.macro portSAVE_CONTEXT
.global pxCurrentTCB
/* make room in stack */
addi sp, sp, -REGBYTES * 32
/* Save Context */ #if( portasmHAS_MTIME != 0 )
STORE x1, 0x0(sp)
STORE x2, 1 * REGBYTES(sp)
STORE x3, 2 * REGBYTES(sp)
STORE x4, 3 * REGBYTES(sp)
STORE x5, 4 * REGBYTES(sp)
STORE x6, 5 * REGBYTES(sp)
STORE x7, 6 * REGBYTES(sp)
STORE x8, 7 * REGBYTES(sp)
STORE x9, 8 * REGBYTES(sp)
STORE x10, 9 * REGBYTES(sp)
STORE x11, 10 * REGBYTES(sp)
STORE x12, 11 * REGBYTES(sp)
STORE x13, 12 * REGBYTES(sp)
STORE x14, 13 * REGBYTES(sp)
STORE x15, 14 * REGBYTES(sp)
STORE x16, 15 * REGBYTES(sp)
STORE x17, 16 * REGBYTES(sp)
STORE x18, 17 * REGBYTES(sp)
STORE x19, 18 * REGBYTES(sp)
STORE x20, 19 * REGBYTES(sp)
STORE x21, 20 * REGBYTES(sp)
STORE x22, 21 * REGBYTES(sp)
STORE x23, 22 * REGBYTES(sp)
STORE x24, 23 * REGBYTES(sp)
STORE x25, 24 * REGBYTES(sp)
STORE x26, 25 * REGBYTES(sp)
STORE x27, 26 * REGBYTES(sp)
STORE x28, 27 * REGBYTES(sp)
STORE x29, 28 * REGBYTES(sp)
STORE x30, 29 * REGBYTES(sp)
STORE x31, 30 * REGBYTES(sp)
/* Store current stackpointer in task control block (TCB) */ test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
LOAD t0, pxCurrentTCB //pointer
STORE sp, 0x0(t0)
.endm
/* Saves current error program counter (EPC) as task program counter */ addi t0, x0, 1
.macro portSAVE_EPC
csrr t0, mepc
STORE t0, 31 * REGBYTES(sp)
.endm
/* Saves current return adress (RA) as task program counter */ slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
.macro portSAVE_RA addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
STORE ra, 31 * REGBYTES(sp) bne a0, t1, test_if_external_interrupt
.endm
/* Macro for restoring task context */ load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
.macro portRESTORE_CONTEXT load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
.global pxCurrentTCB #if( __riscv_xlen == 32 )
/* Load stack pointer from the current TCB */
LOAD sp, pxCurrentTCB
LOAD sp, 0x0(sp)
/* Load task program counter */ /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
LOAD t0, 31 * REGBYTES(sp) li t4, -1
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
sw t4, 0(t1) /* Store new low word of ullNextTime. */
sw t6, 4(t1) /* Store new high word of ullNextTime. */
#endif /* __riscv_xlen == 32 */
#if( __riscv_xlen == 64 )
/* Update the 64-bit mtimer compare match value. */
ld t2, 0(t1) /* Load ullNextTime into t2. */
sd t2, 0(t0) /* Store ullNextTime into compare register. */
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
sd t4, 0(t1) /* Store ullNextTime. */
#endif /* __riscv_xlen == 64 */
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
jal xTaskIncrementTick
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
jal vTaskSwitchContext
j processed_source
test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
#endif /* portasmHAS_MTIME */
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
j processed_source
handle_synchronous:
addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
store_x a1, 0( sp ) /* Save updated exception return address. */
test_if_environment_call:
li t0, 11 /* 11 == environment call. */
bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
jal vTaskSwitchContext
j processed_source
is_exception:
csrr t0, mcause /* For viewing in the debugger only. */
csrr t1, mepc /* For viewing in the debugger only */
csrr t2, mstatus
j is_exception /* No other exceptions handled yet. */
as_yet_unhandled:
csrr t0, mcause /* For viewing in the debugger only. */
j as_yet_unhandled
processed_source:
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
/* Load mret with the address of the next instruction in the task to run next. */
load_x t0, 0( sp )
csrw mepc, t0 csrw mepc, t0
/* Run in machine mode */ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
li t0, MSTATUS_PRV1
csrs mstatus, t0
/* Restore registers, /* Load mstatus with the interrupt enable bits used by the task. */
Skip global pointer because that does not change */ load_x t0, 29 * portWORD_SIZE( sp )
LOAD x1, 0x0(sp) csrw mstatus, t0 /* Required for MPIE bit. */
LOAD x4, 3 * REGBYTES(sp)
LOAD x5, 4 * REGBYTES(sp) load_x x1, 1 * portWORD_SIZE( sp )
LOAD x6, 5 * REGBYTES(sp) load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
LOAD x7, 6 * REGBYTES(sp) load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
LOAD x8, 7 * REGBYTES(sp) load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
LOAD x9, 8 * REGBYTES(sp) load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
LOAD x10, 9 * REGBYTES(sp) load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
LOAD x11, 10 * REGBYTES(sp) load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
LOAD x12, 11 * REGBYTES(sp) load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
LOAD x13, 12 * REGBYTES(sp) load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
LOAD x14, 13 * REGBYTES(sp) load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
LOAD x15, 14 * REGBYTES(sp) load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
LOAD x16, 15 * REGBYTES(sp) load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
LOAD x17, 16 * REGBYTES(sp) load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
LOAD x18, 17 * REGBYTES(sp) load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
LOAD x19, 18 * REGBYTES(sp) load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
LOAD x20, 19 * REGBYTES(sp) load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
LOAD x21, 20 * REGBYTES(sp) load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
LOAD x22, 21 * REGBYTES(sp) load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
LOAD x23, 22 * REGBYTES(sp) load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
LOAD x24, 23 * REGBYTES(sp) load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
LOAD x25, 24 * REGBYTES(sp) load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
LOAD x26, 25 * REGBYTES(sp) load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
LOAD x27, 26 * REGBYTES(sp) load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
LOAD x28, 27 * REGBYTES(sp) load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
LOAD x29, 28 * REGBYTES(sp) load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
LOAD x30, 29 * REGBYTES(sp) load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
LOAD x31, 30 * REGBYTES(sp) load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
addi sp, sp, portCONTEXT_SIZE
addi sp, sp, REGBYTES * 32
mret mret
.endm .endfunc
/*-----------------------------------------------------------*/
/* Macro for restoring task context */ .align 16
TIMER_CMP_INT: .func
portSAVE_CONTEXT xPortStartFirstTask:
portSAVE_EPC
jal vPortSysTickHandler
portRESTORE_CONTEXT
#if( portasmHAS_SIFIVE_CLINT != 0 )
/* If there is a clint then interrupts can branch directly to the FreeRTOS
trap handler. Otherwise the interrupt controller will need to be configured
outside of this file. */
la t0, freertos_risc_v_trap_handler
csrw mtvec, t0
#endif /* portasmHAS_CLILNT */
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( sp ) /* Read sp from first TCB member. */
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
load_x t0, 29 * portWORD_SIZE( sp ) /* mstatus */
addi t0, t0, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
addi sp, sp, portCONTEXT_SIZE
ret
.endfunc
/*-----------------------------------------------------------*/
vPortYield:
/* /*
* This routine can be called from outside of interrupt handler. This means * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
* interrupts may be enabled at this point. This is probably okay for registers and * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
* stack. However, "mepc" will be overwritten by the interrupt handler if a timer * for the function is as per the other ports:
* interrupt happens during the yield. To avoid this, prevent interrupts before starting. * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
* The write to mstatus in the restore context routine will enable interrupts after the *
* mret. A more fine-grain lock may be possible. * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
*
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
*
* Register ABI Name Description Saver
* x0 zero Hard-wired zero -
* x1 ra Return address Caller
* x2 sp Stack pointer Callee
* x3 gp Global pointer -
* x4 tp Thread pointer -
* x5-7 t0-2 Temporaries Caller
* x8 s0/fp Saved register/Frame pointer Callee
* x9 s1 Saved register Callee
* x10-11 a0-1 Function Arguments/return values Caller
* x12-17 a2-7 Function arguments Caller
* x18-27 s2-11 Saved registers Callee
* x28-31 t3-6 Temporaries Caller
*
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
* where the global and thread pointers are currently assumed to be constant so
* are not saved:
*
* mstatus
* x31
* x30
* x29
* x28
* x27
* x26
* x25
* x24
* x23
* x22
* x21
* x20
* x19
* x18
* x17
* x16
* x15
* x14
* x13
* x12
* x11
* pvParameters
* x9
* x8
* x7
* x6
* x5
* portTASK_RETURN_ADDRESS
* [chip specific registers go here]
* pxCode
*/ */
csrci mstatus, 8 .align 8
.func
pxPortInitialiseStack:
portSAVE_CONTEXT csrr t0, mstatus /* Obtain current mstatus value. */
portSAVE_RA addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
jal vTaskSwitchContext slli t1, t1, 4
portRESTORE_CONTEXT or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
addi a0, a0, -portWORD_SIZE
store_x t0, 0(a0) /* mstatus onto the stack. */
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
beq t0, x0, 1f /* No more chip specific registers to save. */
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
j chip_specific_stack_frame /* Until no more chip specific registers. */
1:
addi a0, a0, -portWORD_SIZE
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
ret
.endfunc
/*-----------------------------------------------------------*/

66
portable/GCC/RISC-V/portmacro.h
View file

@ -2,22 +2,23 @@
* FreeRTOS Kernel V10.3.1 * FreeRTOS Kernel V10.3.1
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a copy of * Permission is hereby granted, free of charge, to any person obtaining a copy
* this software and associated documentation files (the "Software"), to deal in * of this software and associated documentation files (the "Software"), to deal
* the Software without restriction, including without limitation the rights to * in the Software without restriction, including without limitation the rights
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* the Software, and to permit persons to whom the Software is furnished to do so, * copies of the Software, and to permit persons to whom the Software is
* subject to the following conditions: * furnished to do so, subject to the following conditions:
* *
* The above copyright notice and this permission notice shall be included in all * The above copyright notice and this permission notice shall be included in
* copies or substantial portions of the Software. * all copies or substantial portions of the Software.
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
* *
* http://www.FreeRTOS.org * http://www.FreeRTOS.org
* http://aws.amazon.com/freertos * http://aws.amazon.com/freertos
@ -25,12 +26,12 @@
* 1 tab == 4 spaces! * 1 tab == 4 spaces!
*/ */
#ifndef PORTMACRO_H #ifndef PORTMACRO_H
#define PORTMACRO_H #define PORTMACRO_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C"
{
#endif #endif
/*----------------------------------------------------------- /*-----------------------------------------------------------
@ -59,7 +60,6 @@ extern "C" {
#error Assembler did not define __riscv_xlen #error Assembler did not define __riscv_xlen
#endif #endif
typedef portSTACK_TYPE StackType_t; typedef portSTACK_TYPE StackType_t;
typedef portBASE_TYPE BaseType_t; typedef portBASE_TYPE BaseType_t;
typedef portUBASE_TYPE UBaseType_t; typedef portUBASE_TYPE UBaseType_t;
@ -88,22 +88,22 @@ not need to be guarded with a critical section. */
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Scheduler utilities. */ /* Scheduler utilities. */
extern void vTaskSwitchContext(void); extern void vTaskSwitchContext(void);
#define portYIELD() __asm volatile("ecall"); #define portYIELD() __asm volatile("ecall");
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext() #define portEND_SWITCHING_ISR(xSwitchRequired) \
if (xSwitchRequired) vTaskSwitchContext()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x) #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Critical section management. */ /* Critical section management. */
#define portCRITICAL_NESTING_IN_TCB 1 #define portCRITICAL_NESTING_IN_TCB 1
extern void vTaskEnterCritical(void); extern void vTaskEnterCritical(void);
extern void vTaskExitCritical(void); extern void vTaskExitCritical(void);
#define portSET_INTERRUPT_MASK_FROM_ISR() 0 #define portSET_INTERRUPT_MASK_FROM_ISR() 0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue #define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) \
(void)uxSavedStatusValue
#define portDISABLE_INTERRUPTS() __asm volatile("csrc mstatus, 8") #define portDISABLE_INTERRUPTS() __asm volatile("csrc mstatus, 8")
#define portENABLE_INTERRUPTS() __asm volatile("csrs mstatus, 8") #define portENABLE_INTERRUPTS() __asm volatile("csrs mstatus, 8")
#define portENTER_CRITICAL() vTaskEnterCritical() #define portENTER_CRITICAL() vTaskEnterCritical()
@ -124,23 +124,27 @@ extern void vTaskExitCritical( void );
#endif #endif
/* Store/clear the ready priorities in a bit map. */ /* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) #define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) \
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) (uxReadyPriorities) |= (1UL << (uxPriority))
#define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities) \
(uxReadyPriorities) &= ~(1UL << (uxPriority))
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) ) #define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) \
uxTopPriority = (31UL - __builtin_clz(uxReadyPriorities))
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are /* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */ (which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) \
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) void vFunction(void *pvParameters)
#define portTASK_FUNCTION(vFunction, pvParameters) \
void vFunction(void *pvParameters)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -155,12 +159,12 @@ not necessary for to use this port. They are defined so the common demo files
#define portMEMORY_BARRIER() __asm volatile("" ::: "memory") #define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the /* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
backward compatibility derive the newer definitions from the old if the old backward compatibility derive the newer definitions from the old if the old
definition is found. */ definition is found. */
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) #if defined(configCLINT_BASE_ADDRESS) && !defined(configMTIME_BASE_ADDRESS) && \
(configCLINT_BASE_ADDRESS == 0)
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
addresses to 0. */ addresses to 0. */
@ -172,15 +176,13 @@ definition is found. */
from the CLINT address. */ from the CLINT address. */
#define configMTIME_BASE_ADDRESS ((configCLINT_BASE_ADDRESS) + 0xBFF8UL) #define configMTIME_BASE_ADDRESS ((configCLINT_BASE_ADDRESS) + 0xBFF8UL)
#define configMTIMECMP_BASE_ADDRESS ((configCLINT_BASE_ADDRESS) + 0x4000UL) #define configMTIMECMP_BASE_ADDRESS ((configCLINT_BASE_ADDRESS) + 0x4000UL)
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) #elif !defined(configMTIME_BASE_ADDRESS) || \
!defined(configMTIMECMP_BASE_ADDRESS)
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */