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Normalize line endings and whitespace in source files
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Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
368
portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
vendored
368
portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
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@ -1,185 +1,183 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* Xtensa interrupt handling data and assembly routines.
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* Also see xtensa_intr.c and xtensa_vectors.S.
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*/
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#include <xtensa/hal.h>
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#include <xtensa/config/core.h>
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#include "xtensa_context.h"
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#if XCHAL_HAVE_INTERRUPTS
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/*
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-------------------------------------------------------------------------------
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INTENABLE virtualization information.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_intdata
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.align 8
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_xt_intdata:
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.global _xt_intenable
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.type _xt_intenable,@object
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.size _xt_intenable,4
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.global _xt_vpri_mask
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.type _xt_vpri_mask,@object
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.size _xt_vpri_mask,4
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_xt_intenable: .word 0 /* Virtual INTENABLE */
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_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
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/*
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-------------------------------------------------------------------------------
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Table of C-callable interrupt handlers for each interrupt. Note that not all
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slots can be filled, because interrupts at level > EXCM_LEVEL will not be
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dispatched to a C handler by default.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_interrupt_table
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.align 8
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_xt_interrupt_table:
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.set i, 0
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.rept XCHAL_NUM_INTERRUPTS
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.word xt_unhandled_interrupt /* handler address */
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.word i /* handler arg (default: intnum) */
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.set i, i+1
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.endr
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#endif /* XCHAL_HAVE_INTERRUPTS */
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#if XCHAL_HAVE_EXCEPTIONS
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/*
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-------------------------------------------------------------------------------
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Table of C-callable exception handlers for each exception. Note that not all
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slots will be active, because some exceptions (e.g. coprocessor exceptions)
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are always handled by the OS and cannot be hooked by user handlers.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_exception_table
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.align 4
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_xt_exception_table:
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.rept XCHAL_EXCCAUSE_NUM
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.word xt_unhandled_exception /* handler address */
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.endr
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#endif
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/*
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-------------------------------------------------------------------------------
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unsigned int xt_ints_on ( unsigned int mask )
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Enables a set of interrupts. Does not simply set INTENABLE directly, but
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computes it as a function of the current virtual priority.
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Can be called from interrupt handlers.
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-------------------------------------------------------------------------------
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*/
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.text
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.align 4
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.global xt_ints_on
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.type xt_ints_on,@function
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xt_ints_on:
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ENTRY0
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#if XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xt_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xt_intenable */
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l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
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or a5, a3, a2 /* a5 = _xt_intenable | mask */
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s32i a5, a4, 0 /* _xt_intenable |= mask */
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and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* Return zero */
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#endif
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RET0
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.size xt_ints_on, . - xt_ints_on
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/*
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-------------------------------------------------------------------------------
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unsigned int xt_ints_off ( unsigned int mask )
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Disables a set of interrupts. Does not simply set INTENABLE directly,
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but computes it as a function of the current virtual priority.
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Can be called from interrupt handlers.
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-------------------------------------------------------------------------------
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*/
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.text
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.align 4
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.global xt_ints_off
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.type xt_ints_off,@function
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xt_ints_off:
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ENTRY0
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#if XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xt_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xt_intenable */
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l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
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or a5, a3, a2 /* a5 = _xt_intenable | mask */
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xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
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s32i a5, a4, 0 /* _xt_intenable &= ~mask */
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and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* return zero */
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#endif
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RET0
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.size xt_ints_off, . - xt_ints_off
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* Xtensa interrupt handling data and assembly routines.
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* Also see xtensa_intr.c and xtensa_vectors.S.
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*/
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#include <xtensa/hal.h>
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#include <xtensa/config/core.h>
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#include "xtensa_context.h"
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#if XCHAL_HAVE_INTERRUPTS
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/*
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-------------------------------------------------------------------------------
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INTENABLE virtualization information.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_intdata
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.align 8
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_xt_intdata:
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.global _xt_intenable
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.type _xt_intenable,@object
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.size _xt_intenable,4
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.global _xt_vpri_mask
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.type _xt_vpri_mask,@object
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.size _xt_vpri_mask,4
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_xt_intenable: .word 0 /* Virtual INTENABLE */
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_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
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/*
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-------------------------------------------------------------------------------
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Table of C-callable interrupt handlers for each interrupt. Note that not all
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slots can be filled, because interrupts at level > EXCM_LEVEL will not be
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dispatched to a C handler by default.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_interrupt_table
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.align 8
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_xt_interrupt_table:
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.set i, 0
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.rept XCHAL_NUM_INTERRUPTS
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.word xt_unhandled_interrupt /* handler address */
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.word i /* handler arg (default: intnum) */
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.set i, i+1
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.endr
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#endif /* XCHAL_HAVE_INTERRUPTS */
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#if XCHAL_HAVE_EXCEPTIONS
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/*
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-------------------------------------------------------------------------------
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Table of C-callable exception handlers for each exception. Note that not all
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slots will be active, because some exceptions (e.g. coprocessor exceptions)
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are always handled by the OS and cannot be hooked by user handlers.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_exception_table
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.align 4
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_xt_exception_table:
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.rept XCHAL_EXCCAUSE_NUM
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.word xt_unhandled_exception /* handler address */
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.endr
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#endif
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/*
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-------------------------------------------------------------------------------
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unsigned int xt_ints_on ( unsigned int mask )
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Enables a set of interrupts. Does not simply set INTENABLE directly, but
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computes it as a function of the current virtual priority.
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Can be called from interrupt handlers.
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-------------------------------------------------------------------------------
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*/
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.text
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.align 4
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.global xt_ints_on
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.type xt_ints_on,@function
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xt_ints_on:
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ENTRY0
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#if XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xt_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xt_intenable */
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l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
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or a5, a3, a2 /* a5 = _xt_intenable | mask */
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s32i a5, a4, 0 /* _xt_intenable |= mask */
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and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* Return zero */
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#endif
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RET0
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.size xt_ints_on, . - xt_ints_on
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/*
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-------------------------------------------------------------------------------
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unsigned int xt_ints_off ( unsigned int mask )
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Disables a set of interrupts. Does not simply set INTENABLE directly,
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but computes it as a function of the current virtual priority.
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Can be called from interrupt handlers.
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-------------------------------------------------------------------------------
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*/
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.text
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.align 4
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.global xt_ints_off
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.type xt_ints_off,@function
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xt_ints_off:
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ENTRY0
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#if XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xt_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xt_intenable */
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l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
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or a5, a3, a2 /* a5 = _xt_intenable | mask */
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xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
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s32i a5, a4, 0 /* _xt_intenable &= ~mask */
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and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* return zero */
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#endif
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RET0
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.size xt_ints_off, . - xt_ints_off
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