mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -32,231 +32,231 @@ the code is included in C files but excluded by the preprocessor in assembly
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files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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#include "FreeRTOSConfig.h"
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EXTERN pxCurrentTCB
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EXTERN vTaskSwitchContext
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EXTERN vPortSVCHandler_C
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EXTERN pxCurrentTCB
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EXTERN vTaskSwitchContext
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EXTERN vPortSVCHandler_C
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PUBLIC xIsPrivileged
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PUBLIC vResetPrivilege
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PUBLIC vRestoreContextOfFirstTask
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PUBLIC vRaisePrivilege
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PUBLIC vStartFirstTask
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PUBLIC ulSetInterruptMask
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PUBLIC vClearInterruptMask
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PUBLIC PendSV_Handler
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PUBLIC SVC_Handler
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PUBLIC xIsPrivileged
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PUBLIC vResetPrivilege
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PUBLIC vRestoreContextOfFirstTask
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PUBLIC vRaisePrivilege
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PUBLIC vStartFirstTask
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PUBLIC ulSetInterruptMask
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PUBLIC vClearInterruptMask
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PUBLIC PendSV_Handler
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PUBLIC SVC_Handler
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/*-----------------------------------------------------------*/
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/*---------------- Unprivileged Functions -------------------*/
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/*-----------------------------------------------------------*/
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SECTION .text:CODE:NOROOT(2)
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THUMB
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SECTION .text:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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xIsPrivileged:
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mrs r0, control /* r0 = CONTROL. */
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tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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ite ne
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movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
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bx lr /* Return. */
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mrs r0, control /* r0 = CONTROL. */
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tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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ite ne
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movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vResetPrivilege:
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mrs r0, control /* r0 = CONTROL. */
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orr r0, r0, #1 /* r0 = r0 | 1. */
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msr control, r0 /* CONTROL = r0. */
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bx lr /* Return to the caller. */
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mrs r0, control /* r0 = CONTROL. */
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orr r0, r0, #1 /* r0 = r0 | 1. */
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msr control, r0 /* CONTROL = r0. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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/*----------------- Privileged Functions --------------------*/
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/*-----------------------------------------------------------*/
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SECTION privileged_functions:CODE:NOROOT(2)
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THUMB
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SECTION privileged_functions:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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vRestoreContextOfFirstTask:
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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#if ( configENABLE_MPU == 1 )
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r3, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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movs r3, #4 /* r3 = 4. */
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str r3, [r2] /* Program RNR = 4. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
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stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r3, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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movs r3, #4 /* r3 = 4. */
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str r3, [r2] /* Program RNR = 4. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
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stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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#if ( configENABLE_MPU == 1 )
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ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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msr psplim, r1 /* Set this task's PSPLIM value. */
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msr control, r2 /* Set this task's CONTROL value. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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mov r0, #0
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msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
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bx r3 /* Finally, branch to EXC_RETURN. */
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ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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msr psplim, r1 /* Set this task's PSPLIM value. */
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msr control, r2 /* Set this task's CONTROL value. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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mov r0, #0
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msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
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bx r3 /* Finally, branch to EXC_RETURN. */
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#else /* configENABLE_MPU */
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ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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msr psplim, r1 /* Set this task's PSPLIM value. */
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movs r1, #2 /* r1 = 2. */
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msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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mov r0, #0
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msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
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bx r2 /* Finally, branch to EXC_RETURN. */
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ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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msr psplim, r1 /* Set this task's PSPLIM value. */
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movs r1, #2 /* r1 = 2. */
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msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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mov r0, #0
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msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
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bx r2 /* Finally, branch to EXC_RETURN. */
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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vRaisePrivilege:
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mrs r0, control /* Read the CONTROL register. */
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bic r0, r0, #1 /* Clear the bit 0. */
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msr control, r0 /* Write back the new CONTROL value. */
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bx lr /* Return to the caller. */
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mrs r0, control /* Read the CONTROL register. */
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bic r0, r0, #1 /* Clear the bit 0. */
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msr control, r0 /* Write back the new CONTROL value. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vStartFirstTask:
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ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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msr msp, r0 /* Set the MSP back to the start of the stack. */
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cpsie i /* Globally enable interrupts. */
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cpsie f
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dsb
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isb
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svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
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ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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msr msp, r0 /* Set the MSP back to the start of the stack. */
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cpsie i /* Globally enable interrupts. */
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cpsie f
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dsb
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isb
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svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
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/*-----------------------------------------------------------*/
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ulSetInterruptMask:
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mrs r0, basepri /* r0 = basepri. Return original basepri value. */
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mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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dsb
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isb
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bx lr /* Return. */
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mrs r0, basepri /* r0 = basepri. Return original basepri value. */
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mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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dsb
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isb
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vClearInterruptMask:
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msr basepri, r0 /* basepri = ulMask. */
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dsb
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isb
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bx lr /* Return. */
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msr basepri, r0 /* basepri = ulMask. */
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dsb
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isb
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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PendSV_Handler:
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mrs r0, psp /* Read PSP in r0. */
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mrs r0, psp /* Read PSP in r0. */
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#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
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tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
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it eq
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vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
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tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
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it eq
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vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
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#endif /* configENABLE_FPU || configENABLE_MVE */
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#if ( configENABLE_MPU == 1 )
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mrs r1, psplim /* r1 = PSPLIM. */
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mrs r2, control /* r2 = CONTROL. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
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mrs r1, psplim /* r1 = PSPLIM. */
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mrs r2, control /* r2 = CONTROL. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
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#else /* configENABLE_MPU */
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mrs r2, psplim /* r2 = PSPLIM. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
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#endif /* configENABLE_MPU */
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r2] /* Read pxCurrentTCB. */
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str r0, [r1] /* Save the new top of stack in TCB. */
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r2] /* Read pxCurrentTCB. */
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str r0, [r1] /* Save the new top of stack in TCB. */
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mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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dsb
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isb
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bl vTaskSwitchContext
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mov r0, #0 /* r0 = 0. */
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msr basepri, r0 /* Enable interrupts. */
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mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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dsb
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isb
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bl vTaskSwitchContext
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mov r0, #0 /* r0 = 0. */
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msr basepri, r0 /* Enable interrupts. */
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
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#if ( configENABLE_MPU == 1 )
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r3, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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movs r3, #4 /* r3 = 4. */
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str r3, [r2] /* Program RNR = 4. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
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stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r3, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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movs r3, #4 /* r3 = 4. */
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str r3, [r2] /* Program RNR = 4. */
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adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
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stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
|
||||
str r4, [r2] /* Enable MPU. */
|
||||
dsb /* Force memory writes before continuing. */
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
|
||||
ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
|
||||
#else /* configENABLE_MPU */
|
||||
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
|
||||
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
|
||||
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
|
||||
it eq
|
||||
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
|
||||
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
|
||||
it eq
|
||||
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
|
||||
#endif /* configENABLE_FPU || configENABLE_MVE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
|
||||
msr control, r2 /* Restore the CONTROL register value for the task. */
|
||||
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
|
||||
msr control, r2 /* Restore the CONTROL register value for the task. */
|
||||
#else /* configENABLE_MPU */
|
||||
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
|
||||
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
|
||||
#endif /* configENABLE_MPU */
|
||||
msr psp, r0 /* Remember the new top of stack for the task. */
|
||||
bx r3
|
||||
msr psp, r0 /* Remember the new top of stack for the task. */
|
||||
bx r3
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SVC_Handler:
|
||||
tst lr, #4
|
||||
ite eq
|
||||
mrseq r0, msp
|
||||
mrsne r0, psp
|
||||
b vPortSVCHandler_C
|
||||
tst lr, #4
|
||||
ite eq
|
||||
mrseq r0, msp
|
||||
mrsne r0, psp
|
||||
b vPortSVCHandler_C
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
END
|
||||
END
|
||||
|
|
|
|||
|
|
@ -155,9 +155,9 @@
|
|||
* 8-bit values encoded as follows:
|
||||
* Bit[7:4] - 0000 - Device Memory
|
||||
* Bit[3:2] - 00 --> Device-nGnRnE
|
||||
* 01 --> Device-nGnRE
|
||||
* 10 --> Device-nGRE
|
||||
* 11 --> Device-GRE
|
||||
* 01 --> Device-nGnRE
|
||||
* 10 --> Device-nGRE
|
||||
* 11 --> Device-GRE
|
||||
* Bit[1:0] - 00, Reserved.
|
||||
*/
|
||||
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue