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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -1,132 +1,132 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#include <FreeRTOSConfig.h>
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RSEG CODE:CODE(2)
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thumb
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EXTERN vPortYieldFromISR
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EXTERN pxCurrentTCB
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EXTERN vTaskSwitchContext
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PUBLIC vSetMSP
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PUBLIC xPortPendSVHandler
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PUBLIC vPortSVCHandler
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PUBLIC vPortStartFirstTask
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PUBLIC ulSetInterruptMaskFromISR
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PUBLIC vClearInterruptMaskFromISR
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/*-----------------------------------------------------------*/
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vSetMSP
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msr msp, r0
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bx lr
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/*-----------------------------------------------------------*/
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xPortPendSVHandler:
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mrs r0, psp
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ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [r3]
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subs r0, r0, #32 /* Make space for the remaining low registers. */
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str r0, [r2] /* Save the new top of stack. */
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stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
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mov r4, r8 /* Store the high registers. */
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mov r5, r9
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mov r6, r10
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mov r7, r11
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stmia r0!, {r4-r7}
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push {r3, r14}
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cpsid i
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bl vTaskSwitchContext
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cpsie i
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pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
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ldr r1, [r2]
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, r0, #16 /* Move to the high registers. */
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ldmia r0!, {r4-r7} /* Pop the high registers. */
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mov r8, r4
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mov r9, r5
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mov r10, r6
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mov r11, r7
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msr psp, r0 /* Remember the new top of stack for the task. */
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subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */
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ldmia r0!, {r4-r7} /* Pop low registers. */
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bx r3
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/*-----------------------------------------------------------*/
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vPortSVCHandler;
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/* This function is no longer used, but retained for backward
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compatibility. */
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bx lr
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/*-----------------------------------------------------------*/
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vPortStartFirstTask
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/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
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table offset register that can be used to locate the initial stack value.
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Not all M0 parts have the application vector table at address 0. */
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ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
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ldr r1, [r3]
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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movs r0, #2 /* Switch to the psp stack. */
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msr CONTROL, r0
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isb
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pop {r0-r5} /* Pop the registers that are saved automatically. */
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mov lr, r5 /* lr is now in r5. */
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pop {r3} /* The return address is now in r3. */
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pop {r2} /* Pop and discard the XPSR. */
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cpsie i /* The first task has its context and interrupts can be enabled. */
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bx r3 /* Jump to the user defined task code. */
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/*-----------------------------------------------------------*/
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ulSetInterruptMaskFromISR
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mrs r0, PRIMASK
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cpsid i
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bx lr
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/*-----------------------------------------------------------*/
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vClearInterruptMaskFromISR
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msr PRIMASK, r0
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bx lr
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END
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#include <FreeRTOSConfig.h>
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RSEG CODE:CODE(2)
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thumb
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EXTERN vPortYieldFromISR
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EXTERN pxCurrentTCB
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EXTERN vTaskSwitchContext
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PUBLIC vSetMSP
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PUBLIC xPortPendSVHandler
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PUBLIC vPortSVCHandler
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PUBLIC vPortStartFirstTask
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PUBLIC ulSetInterruptMaskFromISR
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PUBLIC vClearInterruptMaskFromISR
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/*-----------------------------------------------------------*/
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vSetMSP
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msr msp, r0
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bx lr
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/*-----------------------------------------------------------*/
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xPortPendSVHandler:
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mrs r0, psp
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ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [r3]
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subs r0, r0, #32 /* Make space for the remaining low registers. */
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str r0, [r2] /* Save the new top of stack. */
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stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
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mov r4, r8 /* Store the high registers. */
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mov r5, r9
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mov r6, r10
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mov r7, r11
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stmia r0!, {r4-r7}
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push {r3, r14}
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cpsid i
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bl vTaskSwitchContext
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cpsie i
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pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
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ldr r1, [r2]
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, r0, #16 /* Move to the high registers. */
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ldmia r0!, {r4-r7} /* Pop the high registers. */
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mov r8, r4
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mov r9, r5
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mov r10, r6
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mov r11, r7
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msr psp, r0 /* Remember the new top of stack for the task. */
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subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */
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ldmia r0!, {r4-r7} /* Pop low registers. */
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bx r3
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/*-----------------------------------------------------------*/
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vPortSVCHandler;
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/* This function is no longer used, but retained for backward
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compatibility. */
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bx lr
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/*-----------------------------------------------------------*/
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vPortStartFirstTask
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/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
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table offset register that can be used to locate the initial stack value.
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Not all M0 parts have the application vector table at address 0. */
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ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
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ldr r1, [r3]
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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movs r0, #2 /* Switch to the psp stack. */
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msr CONTROL, r0
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isb
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pop {r0-r5} /* Pop the registers that are saved automatically. */
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mov lr, r5 /* lr is now in r5. */
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pop {r3} /* The return address is now in r3. */
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pop {r2} /* Pop and discard the XPSR. */
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cpsie i /* The first task has its context and interrupts can be enabled. */
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bx r3 /* Jump to the user defined task code. */
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/*-----------------------------------------------------------*/
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ulSetInterruptMaskFromISR
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mrs r0, PRIMASK
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cpsid i
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bx lr
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/*-----------------------------------------------------------*/
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vClearInterruptMaskFromISR
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msr PRIMASK, r0
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bx lr
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END
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