mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -1,46 +1,45 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
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* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* When switching out a task, if the task tag contains a buffer address then
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save the flop context into the buffer. */
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#define traceTASK_SWITCHED_OUT() \
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if( pxCurrentTCB->pxTaskTag != NULL ) \
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{ \
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extern void vPortSaveFPURegisters( void * ); \
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vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
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}
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/* When switching in a task, if the task tag contains a buffer address then
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load the flop context from the buffer. */
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#define traceTASK_SWITCHED_IN() \
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if( pxCurrentTCB->pxTaskTag != NULL ) \
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{ \
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extern void vPortRestoreFPURegisters( void * ); \
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vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
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}
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
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* the Software without restriction, including without limitation the rights to
|
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* When switching out a task, if the task tag contains a buffer address then
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save the flop context into the buffer. */
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#define traceTASK_SWITCHED_OUT() \
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if( pxCurrentTCB->pxTaskTag != NULL ) \
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{ \
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extern void vPortSaveFPURegisters( void * ); \
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vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
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}
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/* When switching in a task, if the task tag contains a buffer address then
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load the flop context from the buffer. */
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#define traceTASK_SWITCHED_IN() \
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if( pxCurrentTCB->pxTaskTag != NULL ) \
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{ \
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extern void vPortRestoreFPURegisters( void * ); \
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vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
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}
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@ -1,261 +1,261 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
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*
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||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the PPC440 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Library includes. */
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#include "xtime_l.h"
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#include "xintc.h"
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#include "xintc_i.h"
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/*-----------------------------------------------------------*/
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/* Definitions to set the initial MSR of each task. */
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#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
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#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
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#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
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#if configUSE_FPU == 1
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#define portAPU_PRESENT ( 1UL << 25UL )
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#define portFCM_FPU_PRESENT ( 1UL << 13UL )
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#else
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#define portAPU_PRESENT ( 0UL )
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#define portFCM_FPU_PRESENT ( 0UL )
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#endif
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#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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extern const unsigned _SDA_BASE_;
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extern const unsigned _SDA2_BASE_;
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/*-----------------------------------------------------------*/
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/*
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* Setup the system timer to generate the tick interrupt.
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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* The handler for the tick interrupt - defined in portasm.s.
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*/
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extern void vPortTickISR( void );
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/*
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* The handler for the yield function - defined in portasm.s.
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*/
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extern void vPortYield( void );
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/*
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* Function to start the scheduler running by starting the highest
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* priority task that has thus far been created.
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*/
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extern void vPortStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/* Structure used to hold the state of the interrupt controller. */
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static XIntc xInterruptController;
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if the task had been
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* interrupted.
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*
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* See the header file portable.h.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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/* Place a known value at the bottom of the stack for debugging. */
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*pxTopOfStack = 0xDEADBEEF;
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pxTopOfStack--;
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/* EABI stack frame. */
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pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
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/* Parameters in R13. */
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*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
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pxTopOfStack -= 10;
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/* Parameters in R3. */
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*pxTopOfStack = ( StackType_t ) pvParameters;
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pxTopOfStack--;
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/* Parameters in R2. */
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*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
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pxTopOfStack--;
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/* R1 is the stack pointer so is omitted. */
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*pxTopOfStack = 0x10000001UL;; /* R0. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* USPRG0. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* CR. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* XER. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* CTR. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL;/* Backchain. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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prvSetupTimerInterrupt();
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XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
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vPortStartFirstTask();
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/* Should not get here as the tasks are now running! */
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return pdFALSE;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented. */
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for( ;; );
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}
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/*-----------------------------------------------------------*/
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/*
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* Hardware initialisation to generate the RTOS tick.
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*/
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static void prvSetupTimerInterrupt( void )
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{
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const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
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XTime_DECClearInterrupt();
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XTime_FITClearInterrupt();
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XTime_WDTClearInterrupt();
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XTime_WDTDisableInterrupt();
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XTime_FITDisableInterrupt();
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XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
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XTime_DECEnableAutoReload();
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XTime_DECSetInterval( ulInterval );
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XTime_DECEnableInterrupt();
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}
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/*-----------------------------------------------------------*/
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void vPortISRHandler( void *pvNullDoNotUse )
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{
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uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
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BaseType_t xInterruptNumber;
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XIntc_Config *pxInterruptController;
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XIntc_VectorTableEntry *pxTable;
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/* Just to remove compiler warning. */
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( void ) pvNullDoNotUse;
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/* Get the configuration by using the device ID - in this case it is
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assumed that only one interrupt controller is being used. */
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pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
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/* Which interrupts are pending? */
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ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
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for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
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{
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if( ulInterruptStatus & 0x01UL )
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{
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/* Clear the pending interrupt. */
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XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
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/* Call the registered handler. */
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pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
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pxTable->Handler( pxTable->CallBackRef );
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}
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/* Check the next interrupt. */
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ulInterruptMask <<= 0x01UL;
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ulInterruptStatus >>= 0x01UL;
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/* Have we serviced all interrupts? */
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if( ulInterruptStatus == 0UL )
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{
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break;
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}
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}
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}
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/*-----------------------------------------------------------*/
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void vPortSetupInterruptController( void )
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{
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extern void vPortISRWrapper( void );
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/* Perform all library calls necessary to initialise the exception table
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and interrupt controller. This assumes only one interrupt controller is in
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use. */
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XExc_mDisableExceptions( XEXC_NON_CRITICAL );
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XExc_Init();
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/* The library functions save the context - we then jump to a wrapper to
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save the stack into the TCB. The wrapper then calls the handler defined
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above. */
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XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
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XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
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XIntc_Start( &xInterruptController, XIN_REAL_MODE );
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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{
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BaseType_t xReturn = pdFAIL;
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/* This function is defined here so the scope of xInterruptController can
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remain within this file. */
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if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
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{
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XIntc_Enable( &xInterruptController, ucInterruptID );
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xReturn = pdPASS;
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}
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return xReturn;
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}
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
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*
|
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* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
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* https://github.com/FreeRTOS
|
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*
|
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*/
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|
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/*-----------------------------------------------------------
|
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* Implementation of functions defined in portable.h for the PPC440 port.
|
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*----------------------------------------------------------*/
|
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|
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|
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/* Scheduler includes. */
|
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#include "FreeRTOS.h"
|
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#include "task.h"
|
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|
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/* Library includes. */
|
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#include "xtime_l.h"
|
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#include "xintc.h"
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#include "xintc_i.h"
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|
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/*-----------------------------------------------------------*/
|
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|
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/* Definitions to set the initial MSR of each task. */
|
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#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
|
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#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
|
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#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
|
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|
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#if configUSE_FPU == 1
|
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#define portAPU_PRESENT ( 1UL << 25UL )
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#define portFCM_FPU_PRESENT ( 1UL << 13UL )
|
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#else
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#define portAPU_PRESENT ( 0UL )
|
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#define portFCM_FPU_PRESENT ( 0UL )
|
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#endif
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|
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#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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|
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|
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extern const unsigned _SDA_BASE_;
|
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extern const unsigned _SDA2_BASE_;
|
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|
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/*-----------------------------------------------------------*/
|
||||
|
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/*
|
||||
* Setup the system timer to generate the tick interrupt.
|
||||
*/
|
||||
static void prvSetupTimerInterrupt( void );
|
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|
||||
/*
|
||||
* The handler for the tick interrupt - defined in portasm.s.
|
||||
*/
|
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extern void vPortTickISR( void );
|
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|
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/*
|
||||
* The handler for the yield function - defined in portasm.s.
|
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*/
|
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extern void vPortYield( void );
|
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|
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/*
|
||||
* Function to start the scheduler running by starting the highest
|
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* priority task that has thus far been created.
|
||||
*/
|
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extern void vPortStartFirstTask( void );
|
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|
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/*-----------------------------------------------------------*/
|
||||
|
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/* Structure used to hold the state of the interrupt controller. */
|
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static XIntc xInterruptController;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Initialise the stack of a task to look exactly as if the task had been
|
||||
* interrupted.
|
||||
*
|
||||
* See the header file portable.h.
|
||||
*/
|
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
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{
|
||||
/* Place a known value at the bottom of the stack for debugging. */
|
||||
*pxTopOfStack = 0xDEADBEEF;
|
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pxTopOfStack--;
|
||||
|
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/* EABI stack frame. */
|
||||
pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
|
||||
|
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/* Parameters in R13. */
|
||||
*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
|
||||
pxTopOfStack -= 10;
|
||||
|
||||
/* Parameters in R3. */
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters;
|
||||
pxTopOfStack--;
|
||||
|
||||
/* Parameters in R2. */
|
||||
*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
|
||||
pxTopOfStack--;
|
||||
|
||||
/* R1 is the stack pointer so is omitted. */
|
||||
|
||||
*pxTopOfStack = 0x10000001UL;; /* R0. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = 0x00000000UL; /* USPRG0. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = 0x00000000UL; /* CR. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = 0x00000000UL; /* XER. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = 0x00000000UL; /* CTR. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = 0x00000000UL;/* Backchain. */
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
prvSetupTimerInterrupt();
|
||||
XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should not get here as the tasks are now running! */
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* Not implemented. */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Hardware initialisation to generate the RTOS tick.
|
||||
*/
|
||||
static void prvSetupTimerInterrupt( void )
|
||||
{
|
||||
const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
|
||||
|
||||
XTime_DECClearInterrupt();
|
||||
XTime_FITClearInterrupt();
|
||||
XTime_WDTClearInterrupt();
|
||||
XTime_WDTDisableInterrupt();
|
||||
XTime_FITDisableInterrupt();
|
||||
|
||||
XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
|
||||
|
||||
XTime_DECEnableAutoReload();
|
||||
XTime_DECSetInterval( ulInterval );
|
||||
XTime_DECEnableInterrupt();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortISRHandler( void *pvNullDoNotUse )
|
||||
{
|
||||
uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
|
||||
BaseType_t xInterruptNumber;
|
||||
XIntc_Config *pxInterruptController;
|
||||
XIntc_VectorTableEntry *pxTable;
|
||||
|
||||
/* Just to remove compiler warning. */
|
||||
( void ) pvNullDoNotUse;
|
||||
|
||||
/* Get the configuration by using the device ID - in this case it is
|
||||
assumed that only one interrupt controller is being used. */
|
||||
pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
|
||||
|
||||
/* Which interrupts are pending? */
|
||||
ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
|
||||
|
||||
for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
|
||||
{
|
||||
if( ulInterruptStatus & 0x01UL )
|
||||
{
|
||||
/* Clear the pending interrupt. */
|
||||
XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
|
||||
|
||||
/* Call the registered handler. */
|
||||
pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
|
||||
pxTable->Handler( pxTable->CallBackRef );
|
||||
}
|
||||
|
||||
/* Check the next interrupt. */
|
||||
ulInterruptMask <<= 0x01UL;
|
||||
ulInterruptStatus >>= 0x01UL;
|
||||
|
||||
/* Have we serviced all interrupts? */
|
||||
if( ulInterruptStatus == 0UL )
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortSetupInterruptController( void )
|
||||
{
|
||||
extern void vPortISRWrapper( void );
|
||||
|
||||
/* Perform all library calls necessary to initialise the exception table
|
||||
and interrupt controller. This assumes only one interrupt controller is in
|
||||
use. */
|
||||
XExc_mDisableExceptions( XEXC_NON_CRITICAL );
|
||||
XExc_Init();
|
||||
|
||||
/* The library functions save the context - we then jump to a wrapper to
|
||||
save the stack into the TCB. The wrapper then calls the handler defined
|
||||
above. */
|
||||
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
|
||||
XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
|
||||
XIntc_Start( &xInterruptController, XIN_REAL_MODE );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
|
||||
{
|
||||
BaseType_t xReturn = pdFAIL;
|
||||
|
||||
/* This function is defined here so the scope of xInterruptController can
|
||||
remain within this file. */
|
||||
|
||||
if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
|
||||
{
|
||||
XIntc_Enable( &xInterruptController, ucInterruptID );
|
||||
xReturn = pdPASS;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,383 +1,381 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
.extern pxCurrentTCB
|
||||
.extern vTaskSwitchContext
|
||||
.extern xTaskIncrementTick
|
||||
.extern vPortISRHandler
|
||||
|
||||
.global vPortStartFirstTask
|
||||
.global vPortYield
|
||||
.global vPortTickISR
|
||||
.global vPortISRWrapper
|
||||
.global vPortSaveFPURegisters
|
||||
.global vPortRestoreFPURegisters
|
||||
|
||||
.set BChainField, 0
|
||||
.set NextLRField, BChainField + 4
|
||||
.set MSRField, NextLRField + 4
|
||||
.set PCField, MSRField + 4
|
||||
.set LRField, PCField + 4
|
||||
.set CTRField, LRField + 4
|
||||
.set XERField, CTRField + 4
|
||||
.set CRField, XERField + 4
|
||||
.set USPRG0Field, CRField + 4
|
||||
.set r0Field, USPRG0Field + 4
|
||||
.set r2Field, r0Field + 4
|
||||
.set r3r31Field, r2Field + 4
|
||||
.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
|
||||
|
||||
|
||||
.macro portSAVE_STACK_POINTER_AND_LR
|
||||
|
||||
/* Get the address of the TCB. */
|
||||
xor R0, R0, R0
|
||||
addis R2, R0, pxCurrentTCB@ha
|
||||
lwz R2, pxCurrentTCB@l( R2 )
|
||||
|
||||
/* Store the stack pointer into the TCB */
|
||||
stw SP, 0( R2 )
|
||||
|
||||
/* Save the link register */
|
||||
stwu R1, -24( R1 )
|
||||
mflr R0
|
||||
stw R31, 20( R1 )
|
||||
stw R0, 28( R1 )
|
||||
mr R31, r1
|
||||
|
||||
.endm
|
||||
|
||||
.macro portRESTORE_STACK_POINTER_AND_LR
|
||||
|
||||
/* Restore the link register */
|
||||
lwz R11, 0( R1 )
|
||||
lwz R0, 4( R11 )
|
||||
mtlr R0
|
||||
lwz R31, -4( R11 )
|
||||
mr R1, R11
|
||||
|
||||
/* Get the address of the TCB. */
|
||||
xor R0, R0, R0
|
||||
addis SP, R0, pxCurrentTCB@ha
|
||||
lwz SP, pxCurrentTCB@l( R1 )
|
||||
|
||||
/* Get the task stack pointer from the TCB. */
|
||||
lwz SP, 0( SP )
|
||||
|
||||
.endm
|
||||
|
||||
|
||||
vPortStartFirstTask:
|
||||
|
||||
/* Get the address of the TCB. */
|
||||
xor R0, R0, R0
|
||||
addis SP, R0, pxCurrentTCB@ha
|
||||
lwz SP, pxCurrentTCB@l( SP )
|
||||
|
||||
/* Get the task stack pointer from the TCB. */
|
||||
lwz SP, 0( SP )
|
||||
|
||||
/* Restore MSR register to SRR1. */
|
||||
lwz R0, MSRField(R1)
|
||||
mtsrr1 R0
|
||||
|
||||
/* Restore current PC location to SRR0. */
|
||||
lwz R0, PCField(R1)
|
||||
mtsrr0 R0
|
||||
|
||||
/* Save USPRG0 register */
|
||||
lwz R0, USPRG0Field(R1)
|
||||
mtspr 0x100,R0
|
||||
|
||||
/* Restore Condition register */
|
||||
lwz R0, CRField(R1)
|
||||
mtcr R0
|
||||
|
||||
/* Restore Fixed Point Exception register */
|
||||
lwz R0, XERField(R1)
|
||||
mtxer R0
|
||||
|
||||
/* Restore Counter register */
|
||||
lwz R0, CTRField(R1)
|
||||
mtctr R0
|
||||
|
||||
/* Restore Link register */
|
||||
lwz R0, LRField(R1)
|
||||
mtlr R0
|
||||
|
||||
/* Restore remaining GPR registers. */
|
||||
lmw R3,r3r31Field(R1)
|
||||
|
||||
/* Restore r0 and r2. */
|
||||
lwz R0, r0Field(R1)
|
||||
lwz R2, r2Field(R1)
|
||||
|
||||
/* Remove frame from stack */
|
||||
addi R1,R1,IFrameSize
|
||||
|
||||
/* Return into the first task */
|
||||
rfi
|
||||
|
||||
|
||||
|
||||
vPortYield:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl vTaskSwitchContext
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
vPortTickISR:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl xTaskIncrementTick
|
||||
|
||||
#if configUSE_PREEMPTION == 1
|
||||
bl vTaskSwitchContext
|
||||
#endif
|
||||
|
||||
/* Clear the interrupt */
|
||||
lis R0, 2048
|
||||
mttsr R0
|
||||
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
vPortISRWrapper:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl vPortISRHandler
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
#if configUSE_FPU == 1
|
||||
|
||||
vPortSaveFPURegisters:
|
||||
|
||||
/* Enable APU and mark FPU as present. */
|
||||
mfmsr r0
|
||||
xor r30, r30, r30
|
||||
oris r30, r30, 512
|
||||
ori r30, r30, 8192
|
||||
or r0, r0, r30
|
||||
mtmsr r0
|
||||
|
||||
#ifdef USE_DP_FPU
|
||||
|
||||
/* Buffer address is in r3. Save each flop register into an offset from
|
||||
this buffer address. */
|
||||
stfd f0, 0(r3)
|
||||
stfd f1, 8(r3)
|
||||
stfd f2, 16(r3)
|
||||
stfd f3, 24(r3)
|
||||
stfd f4, 32(r3)
|
||||
stfd f5, 40(r3)
|
||||
stfd f6, 48(r3)
|
||||
stfd f7, 56(r3)
|
||||
stfd f8, 64(r3)
|
||||
stfd f9, 72(r3)
|
||||
stfd f10, 80(r3)
|
||||
stfd f11, 88(r3)
|
||||
stfd f12, 96(r3)
|
||||
stfd f13, 104(r3)
|
||||
stfd f14, 112(r3)
|
||||
stfd f15, 120(r3)
|
||||
stfd f16, 128(r3)
|
||||
stfd f17, 136(r3)
|
||||
stfd f18, 144(r3)
|
||||
stfd f19, 152(r3)
|
||||
stfd f20, 160(r3)
|
||||
stfd f21, 168(r3)
|
||||
stfd f22, 176(r3)
|
||||
stfd f23, 184(r3)
|
||||
stfd f24, 192(r3)
|
||||
stfd f25, 200(r3)
|
||||
stfd f26, 208(r3)
|
||||
stfd f27, 216(r3)
|
||||
stfd f28, 224(r3)
|
||||
stfd f29, 232(r3)
|
||||
stfd f30, 240(r3)
|
||||
stfd f31, 248(r3)
|
||||
|
||||
/* Also save the FPSCR. */
|
||||
mffs f31
|
||||
stfs f31, 256(r3)
|
||||
|
||||
#else
|
||||
|
||||
/* Buffer address is in r3. Save each flop register into an offset from
|
||||
this buffer address. */
|
||||
stfs f0, 0(r3)
|
||||
stfs f1, 4(r3)
|
||||
stfs f2, 8(r3)
|
||||
stfs f3, 12(r3)
|
||||
stfs f4, 16(r3)
|
||||
stfs f5, 20(r3)
|
||||
stfs f6, 24(r3)
|
||||
stfs f7, 28(r3)
|
||||
stfs f8, 32(r3)
|
||||
stfs f9, 36(r3)
|
||||
stfs f10, 40(r3)
|
||||
stfs f11, 44(r3)
|
||||
stfs f12, 48(r3)
|
||||
stfs f13, 52(r3)
|
||||
stfs f14, 56(r3)
|
||||
stfs f15, 60(r3)
|
||||
stfs f16, 64(r3)
|
||||
stfs f17, 68(r3)
|
||||
stfs f18, 72(r3)
|
||||
stfs f19, 76(r3)
|
||||
stfs f20, 80(r3)
|
||||
stfs f21, 84(r3)
|
||||
stfs f22, 88(r3)
|
||||
stfs f23, 92(r3)
|
||||
stfs f24, 96(r3)
|
||||
stfs f25, 100(r3)
|
||||
stfs f26, 104(r3)
|
||||
stfs f27, 108(r3)
|
||||
stfs f28, 112(r3)
|
||||
stfs f29, 116(r3)
|
||||
stfs f30, 120(r3)
|
||||
stfs f31, 124(r3)
|
||||
|
||||
/* Also save the FPSCR. */
|
||||
mffs f31
|
||||
stfs f31, 128(r3)
|
||||
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
#endif /* configUSE_FPU. */
|
||||
|
||||
|
||||
#if configUSE_FPU == 1
|
||||
|
||||
vPortRestoreFPURegisters:
|
||||
|
||||
/* Enable APU and mark FPU as present. */
|
||||
mfmsr r0
|
||||
xor r30, r30, r30
|
||||
oris r30, r30, 512
|
||||
ori r30, r30, 8192
|
||||
or r0, r0, r30
|
||||
mtmsr r0
|
||||
|
||||
#ifdef USE_DP_FPU
|
||||
|
||||
/* Buffer address is in r3. Restore each flop register from an offset
|
||||
into this buffer.
|
||||
|
||||
First the FPSCR. */
|
||||
lfs f31, 256(r3)
|
||||
mtfsf f31, 7
|
||||
|
||||
lfd f0, 0(r3)
|
||||
lfd f1, 8(r3)
|
||||
lfd f2, 16(r3)
|
||||
lfd f3, 24(r3)
|
||||
lfd f4, 32(r3)
|
||||
lfd f5, 40(r3)
|
||||
lfd f6, 48(r3)
|
||||
lfd f7, 56(r3)
|
||||
lfd f8, 64(r3)
|
||||
lfd f9, 72(r3)
|
||||
lfd f10, 80(r3)
|
||||
lfd f11, 88(r3)
|
||||
lfd f12, 96(r3)
|
||||
lfd f13, 104(r3)
|
||||
lfd f14, 112(r3)
|
||||
lfd f15, 120(r3)
|
||||
lfd f16, 128(r3)
|
||||
lfd f17, 136(r3)
|
||||
lfd f18, 144(r3)
|
||||
lfd f19, 152(r3)
|
||||
lfd f20, 160(r3)
|
||||
lfd f21, 168(r3)
|
||||
lfd f22, 176(r3)
|
||||
lfd f23, 184(r3)
|
||||
lfd f24, 192(r3)
|
||||
lfd f25, 200(r3)
|
||||
lfd f26, 208(r3)
|
||||
lfd f27, 216(r3)
|
||||
lfd f28, 224(r3)
|
||||
lfd f29, 232(r3)
|
||||
lfd f30, 240(r3)
|
||||
lfd f31, 248(r3)
|
||||
|
||||
#else
|
||||
|
||||
/* Buffer address is in r3. Restore each flop register from an offset
|
||||
into this buffer.
|
||||
|
||||
First the FPSCR. */
|
||||
lfs f31, 128(r3)
|
||||
mtfsf f31, 7
|
||||
|
||||
lfs f0, 0(r3)
|
||||
lfs f1, 4(r3)
|
||||
lfs f2, 8(r3)
|
||||
lfs f3, 12(r3)
|
||||
lfs f4, 16(r3)
|
||||
lfs f5, 20(r3)
|
||||
lfs f6, 24(r3)
|
||||
lfs f7, 28(r3)
|
||||
lfs f8, 32(r3)
|
||||
lfs f9, 36(r3)
|
||||
lfs f10, 40(r3)
|
||||
lfs f11, 44(r3)
|
||||
lfs f12, 48(r3)
|
||||
lfs f13, 52(r3)
|
||||
lfs f14, 56(r3)
|
||||
lfs f15, 60(r3)
|
||||
lfs f16, 64(r3)
|
||||
lfs f17, 68(r3)
|
||||
lfs f18, 72(r3)
|
||||
lfs f19, 76(r3)
|
||||
lfs f20, 80(r3)
|
||||
lfs f21, 84(r3)
|
||||
lfs f22, 88(r3)
|
||||
lfs f23, 92(r3)
|
||||
lfs f24, 96(r3)
|
||||
lfs f25, 100(r3)
|
||||
lfs f26, 104(r3)
|
||||
lfs f27, 108(r3)
|
||||
lfs f28, 112(r3)
|
||||
lfs f29, 116(r3)
|
||||
lfs f30, 120(r3)
|
||||
lfs f31, 124(r3)
|
||||
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
#endif /* configUSE_FPU. */
|
||||
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
.extern pxCurrentTCB
|
||||
.extern vTaskSwitchContext
|
||||
.extern xTaskIncrementTick
|
||||
.extern vPortISRHandler
|
||||
|
||||
.global vPortStartFirstTask
|
||||
.global vPortYield
|
||||
.global vPortTickISR
|
||||
.global vPortISRWrapper
|
||||
.global vPortSaveFPURegisters
|
||||
.global vPortRestoreFPURegisters
|
||||
|
||||
.set BChainField, 0
|
||||
.set NextLRField, BChainField + 4
|
||||
.set MSRField, NextLRField + 4
|
||||
.set PCField, MSRField + 4
|
||||
.set LRField, PCField + 4
|
||||
.set CTRField, LRField + 4
|
||||
.set XERField, CTRField + 4
|
||||
.set CRField, XERField + 4
|
||||
.set USPRG0Field, CRField + 4
|
||||
.set r0Field, USPRG0Field + 4
|
||||
.set r2Field, r0Field + 4
|
||||
.set r3r31Field, r2Field + 4
|
||||
.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
|
||||
|
||||
|
||||
.macro portSAVE_STACK_POINTER_AND_LR
|
||||
|
||||
/* Get the address of the TCB. */
|
||||
xor R0, R0, R0
|
||||
addis R2, R0, pxCurrentTCB@ha
|
||||
lwz R2, pxCurrentTCB@l( R2 )
|
||||
|
||||
/* Store the stack pointer into the TCB */
|
||||
stw SP, 0( R2 )
|
||||
|
||||
/* Save the link register */
|
||||
stwu R1, -24( R1 )
|
||||
mflr R0
|
||||
stw R31, 20( R1 )
|
||||
stw R0, 28( R1 )
|
||||
mr R31, r1
|
||||
|
||||
.endm
|
||||
|
||||
.macro portRESTORE_STACK_POINTER_AND_LR
|
||||
|
||||
/* Restore the link register */
|
||||
lwz R11, 0( R1 )
|
||||
lwz R0, 4( R11 )
|
||||
mtlr R0
|
||||
lwz R31, -4( R11 )
|
||||
mr R1, R11
|
||||
|
||||
/* Get the address of the TCB. */
|
||||
xor R0, R0, R0
|
||||
addis SP, R0, pxCurrentTCB@ha
|
||||
lwz SP, pxCurrentTCB@l( R1 )
|
||||
|
||||
/* Get the task stack pointer from the TCB. */
|
||||
lwz SP, 0( SP )
|
||||
|
||||
.endm
|
||||
|
||||
|
||||
vPortStartFirstTask:
|
||||
|
||||
/* Get the address of the TCB. */
|
||||
xor R0, R0, R0
|
||||
addis SP, R0, pxCurrentTCB@ha
|
||||
lwz SP, pxCurrentTCB@l( SP )
|
||||
|
||||
/* Get the task stack pointer from the TCB. */
|
||||
lwz SP, 0( SP )
|
||||
|
||||
/* Restore MSR register to SRR1. */
|
||||
lwz R0, MSRField(R1)
|
||||
mtsrr1 R0
|
||||
|
||||
/* Restore current PC location to SRR0. */
|
||||
lwz R0, PCField(R1)
|
||||
mtsrr0 R0
|
||||
|
||||
/* Save USPRG0 register */
|
||||
lwz R0, USPRG0Field(R1)
|
||||
mtspr 0x100,R0
|
||||
|
||||
/* Restore Condition register */
|
||||
lwz R0, CRField(R1)
|
||||
mtcr R0
|
||||
|
||||
/* Restore Fixed Point Exception register */
|
||||
lwz R0, XERField(R1)
|
||||
mtxer R0
|
||||
|
||||
/* Restore Counter register */
|
||||
lwz R0, CTRField(R1)
|
||||
mtctr R0
|
||||
|
||||
/* Restore Link register */
|
||||
lwz R0, LRField(R1)
|
||||
mtlr R0
|
||||
|
||||
/* Restore remaining GPR registers. */
|
||||
lmw R3,r3r31Field(R1)
|
||||
|
||||
/* Restore r0 and r2. */
|
||||
lwz R0, r0Field(R1)
|
||||
lwz R2, r2Field(R1)
|
||||
|
||||
/* Remove frame from stack */
|
||||
addi R1,R1,IFrameSize
|
||||
|
||||
/* Return into the first task */
|
||||
rfi
|
||||
|
||||
|
||||
|
||||
vPortYield:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl vTaskSwitchContext
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
vPortTickISR:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl xTaskIncrementTick
|
||||
|
||||
#if configUSE_PREEMPTION == 1
|
||||
bl vTaskSwitchContext
|
||||
#endif
|
||||
|
||||
/* Clear the interrupt */
|
||||
lis R0, 2048
|
||||
mttsr R0
|
||||
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
vPortISRWrapper:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl vPortISRHandler
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
#if configUSE_FPU == 1
|
||||
|
||||
vPortSaveFPURegisters:
|
||||
|
||||
/* Enable APU and mark FPU as present. */
|
||||
mfmsr r0
|
||||
xor r30, r30, r30
|
||||
oris r30, r30, 512
|
||||
ori r30, r30, 8192
|
||||
or r0, r0, r30
|
||||
mtmsr r0
|
||||
|
||||
#ifdef USE_DP_FPU
|
||||
|
||||
/* Buffer address is in r3. Save each flop register into an offset from
|
||||
this buffer address. */
|
||||
stfd f0, 0(r3)
|
||||
stfd f1, 8(r3)
|
||||
stfd f2, 16(r3)
|
||||
stfd f3, 24(r3)
|
||||
stfd f4, 32(r3)
|
||||
stfd f5, 40(r3)
|
||||
stfd f6, 48(r3)
|
||||
stfd f7, 56(r3)
|
||||
stfd f8, 64(r3)
|
||||
stfd f9, 72(r3)
|
||||
stfd f10, 80(r3)
|
||||
stfd f11, 88(r3)
|
||||
stfd f12, 96(r3)
|
||||
stfd f13, 104(r3)
|
||||
stfd f14, 112(r3)
|
||||
stfd f15, 120(r3)
|
||||
stfd f16, 128(r3)
|
||||
stfd f17, 136(r3)
|
||||
stfd f18, 144(r3)
|
||||
stfd f19, 152(r3)
|
||||
stfd f20, 160(r3)
|
||||
stfd f21, 168(r3)
|
||||
stfd f22, 176(r3)
|
||||
stfd f23, 184(r3)
|
||||
stfd f24, 192(r3)
|
||||
stfd f25, 200(r3)
|
||||
stfd f26, 208(r3)
|
||||
stfd f27, 216(r3)
|
||||
stfd f28, 224(r3)
|
||||
stfd f29, 232(r3)
|
||||
stfd f30, 240(r3)
|
||||
stfd f31, 248(r3)
|
||||
|
||||
/* Also save the FPSCR. */
|
||||
mffs f31
|
||||
stfs f31, 256(r3)
|
||||
|
||||
#else
|
||||
|
||||
/* Buffer address is in r3. Save each flop register into an offset from
|
||||
this buffer address. */
|
||||
stfs f0, 0(r3)
|
||||
stfs f1, 4(r3)
|
||||
stfs f2, 8(r3)
|
||||
stfs f3, 12(r3)
|
||||
stfs f4, 16(r3)
|
||||
stfs f5, 20(r3)
|
||||
stfs f6, 24(r3)
|
||||
stfs f7, 28(r3)
|
||||
stfs f8, 32(r3)
|
||||
stfs f9, 36(r3)
|
||||
stfs f10, 40(r3)
|
||||
stfs f11, 44(r3)
|
||||
stfs f12, 48(r3)
|
||||
stfs f13, 52(r3)
|
||||
stfs f14, 56(r3)
|
||||
stfs f15, 60(r3)
|
||||
stfs f16, 64(r3)
|
||||
stfs f17, 68(r3)
|
||||
stfs f18, 72(r3)
|
||||
stfs f19, 76(r3)
|
||||
stfs f20, 80(r3)
|
||||
stfs f21, 84(r3)
|
||||
stfs f22, 88(r3)
|
||||
stfs f23, 92(r3)
|
||||
stfs f24, 96(r3)
|
||||
stfs f25, 100(r3)
|
||||
stfs f26, 104(r3)
|
||||
stfs f27, 108(r3)
|
||||
stfs f28, 112(r3)
|
||||
stfs f29, 116(r3)
|
||||
stfs f30, 120(r3)
|
||||
stfs f31, 124(r3)
|
||||
|
||||
/* Also save the FPSCR. */
|
||||
mffs f31
|
||||
stfs f31, 128(r3)
|
||||
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
#endif /* configUSE_FPU. */
|
||||
|
||||
|
||||
#if configUSE_FPU == 1
|
||||
|
||||
vPortRestoreFPURegisters:
|
||||
|
||||
/* Enable APU and mark FPU as present. */
|
||||
mfmsr r0
|
||||
xor r30, r30, r30
|
||||
oris r30, r30, 512
|
||||
ori r30, r30, 8192
|
||||
or r0, r0, r30
|
||||
mtmsr r0
|
||||
|
||||
#ifdef USE_DP_FPU
|
||||
|
||||
/* Buffer address is in r3. Restore each flop register from an offset
|
||||
into this buffer.
|
||||
|
||||
First the FPSCR. */
|
||||
lfs f31, 256(r3)
|
||||
mtfsf f31, 7
|
||||
|
||||
lfd f0, 0(r3)
|
||||
lfd f1, 8(r3)
|
||||
lfd f2, 16(r3)
|
||||
lfd f3, 24(r3)
|
||||
lfd f4, 32(r3)
|
||||
lfd f5, 40(r3)
|
||||
lfd f6, 48(r3)
|
||||
lfd f7, 56(r3)
|
||||
lfd f8, 64(r3)
|
||||
lfd f9, 72(r3)
|
||||
lfd f10, 80(r3)
|
||||
lfd f11, 88(r3)
|
||||
lfd f12, 96(r3)
|
||||
lfd f13, 104(r3)
|
||||
lfd f14, 112(r3)
|
||||
lfd f15, 120(r3)
|
||||
lfd f16, 128(r3)
|
||||
lfd f17, 136(r3)
|
||||
lfd f18, 144(r3)
|
||||
lfd f19, 152(r3)
|
||||
lfd f20, 160(r3)
|
||||
lfd f21, 168(r3)
|
||||
lfd f22, 176(r3)
|
||||
lfd f23, 184(r3)
|
||||
lfd f24, 192(r3)
|
||||
lfd f25, 200(r3)
|
||||
lfd f26, 208(r3)
|
||||
lfd f27, 216(r3)
|
||||
lfd f28, 224(r3)
|
||||
lfd f29, 232(r3)
|
||||
lfd f30, 240(r3)
|
||||
lfd f31, 248(r3)
|
||||
|
||||
#else
|
||||
|
||||
/* Buffer address is in r3. Restore each flop register from an offset
|
||||
into this buffer.
|
||||
|
||||
First the FPSCR. */
|
||||
lfs f31, 128(r3)
|
||||
mtfsf f31, 7
|
||||
|
||||
lfs f0, 0(r3)
|
||||
lfs f1, 4(r3)
|
||||
lfs f2, 8(r3)
|
||||
lfs f3, 12(r3)
|
||||
lfs f4, 16(r3)
|
||||
lfs f5, 20(r3)
|
||||
lfs f6, 24(r3)
|
||||
lfs f7, 28(r3)
|
||||
lfs f8, 32(r3)
|
||||
lfs f9, 36(r3)
|
||||
lfs f10, 40(r3)
|
||||
lfs f11, 44(r3)
|
||||
lfs f12, 48(r3)
|
||||
lfs f13, 52(r3)
|
||||
lfs f14, 56(r3)
|
||||
lfs f15, 60(r3)
|
||||
lfs f16, 64(r3)
|
||||
lfs f17, 68(r3)
|
||||
lfs f18, 72(r3)
|
||||
lfs f19, 76(r3)
|
||||
lfs f20, 80(r3)
|
||||
lfs f21, 84(r3)
|
||||
lfs f22, 88(r3)
|
||||
lfs f23, 92(r3)
|
||||
lfs f24, 96(r3)
|
||||
lfs f25, 100(r3)
|
||||
lfs f26, 104(r3)
|
||||
lfs f27, 108(r3)
|
||||
lfs f28, 112(r3)
|
||||
lfs f29, 116(r3)
|
||||
lfs f30, 120(r3)
|
||||
lfs f31, 124(r3)
|
||||
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
#endif /* configUSE_FPU. */
|
||||
|
|
|
|||
|
|
@ -1,119 +1,118 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#include "xexception_l.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This port uses the critical nesting count from the TCB rather than
|
||||
maintaining a separate value and then saving this value in the task stack. */
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
|
||||
/* Interrupt control macros. */
|
||||
#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
|
||||
#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section macros. */
|
||||
void vTaskEnterCritical( void );
|
||||
void vTaskExitCritical( void );
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
void vPortYield( void );
|
||||
#define portYIELD() asm volatile ( "SC \n\t NOP" )
|
||||
#define portYIELD_FROM_ISR() vTaskSwitchContext()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
|
||||
/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
|
||||
#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
/* Port specific interrupt handling functions. */
|
||||
void vPortSetupInterruptController( void );
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#include "xexception_l.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This port uses the critical nesting count from the TCB rather than
|
||||
maintaining a separate value and then saving this value in the task stack. */
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
|
||||
/* Interrupt control macros. */
|
||||
#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL );
|
||||
#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section macros. */
|
||||
void vTaskEnterCritical( void );
|
||||
void vTaskExitCritical( void );
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
void vPortYield( void );
|
||||
#define portYIELD() asm volatile ( "SC \n\t NOP" )
|
||||
#define portYIELD_FROM_ISR() vTaskSwitchContext()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
|
||||
/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
|
||||
#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
/* Port specific interrupt handling functions. */
|
||||
void vPortSetupInterruptController( void );
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue