mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 10:08:33 -04:00
Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -1,383 +1,381 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
|
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* the Software without restriction, including without limitation the rights to
|
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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||||
*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#include "FreeRTOSConfig.h"
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern xTaskIncrementTick
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.extern vPortISRHandler
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.global vPortStartFirstTask
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.global vPortYield
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.global vPortTickISR
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.global vPortISRWrapper
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.global vPortSaveFPURegisters
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.global vPortRestoreFPURegisters
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.set BChainField, 0
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.set NextLRField, BChainField + 4
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.set MSRField, NextLRField + 4
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.set PCField, MSRField + 4
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.set LRField, PCField + 4
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.set CTRField, LRField + 4
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.set XERField, CTRField + 4
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.set CRField, XERField + 4
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.set USPRG0Field, CRField + 4
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.set r0Field, USPRG0Field + 4
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.set r2Field, r0Field + 4
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.set r3r31Field, r2Field + 4
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.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
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.macro portSAVE_STACK_POINTER_AND_LR
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/* Get the address of the TCB. */
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xor R0, R0, R0
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addis R2, R0, pxCurrentTCB@ha
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lwz R2, pxCurrentTCB@l( R2 )
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/* Store the stack pointer into the TCB */
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stw SP, 0( R2 )
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/* Save the link register */
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stwu R1, -24( R1 )
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mflr R0
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stw R31, 20( R1 )
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stw R0, 28( R1 )
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mr R31, r1
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.endm
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.macro portRESTORE_STACK_POINTER_AND_LR
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/* Restore the link register */
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lwz R11, 0( R1 )
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lwz R0, 4( R11 )
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mtlr R0
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lwz R31, -4( R11 )
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mr R1, R11
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/* Get the address of the TCB. */
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xor R0, R0, R0
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addis SP, R0, pxCurrentTCB@ha
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lwz SP, pxCurrentTCB@l( R1 )
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/* Get the task stack pointer from the TCB. */
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lwz SP, 0( SP )
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.endm
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vPortStartFirstTask:
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/* Get the address of the TCB. */
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xor R0, R0, R0
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addis SP, R0, pxCurrentTCB@ha
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lwz SP, pxCurrentTCB@l( SP )
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/* Get the task stack pointer from the TCB. */
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lwz SP, 0( SP )
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/* Restore MSR register to SRR1. */
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lwz R0, MSRField(R1)
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mtsrr1 R0
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/* Restore current PC location to SRR0. */
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lwz R0, PCField(R1)
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mtsrr0 R0
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/* Save USPRG0 register */
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lwz R0, USPRG0Field(R1)
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mtspr 0x100,R0
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/* Restore Condition register */
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lwz R0, CRField(R1)
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mtcr R0
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/* Restore Fixed Point Exception register */
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lwz R0, XERField(R1)
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mtxer R0
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/* Restore Counter register */
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lwz R0, CTRField(R1)
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mtctr R0
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/* Restore Link register */
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lwz R0, LRField(R1)
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mtlr R0
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/* Restore remaining GPR registers. */
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lmw R3,r3r31Field(R1)
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/* Restore r0 and r2. */
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lwz R0, r0Field(R1)
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lwz R2, r2Field(R1)
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/* Remove frame from stack */
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addi R1,R1,IFrameSize
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/* Return into the first task */
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rfi
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vPortYield:
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portSAVE_STACK_POINTER_AND_LR
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bl vTaskSwitchContext
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portRESTORE_STACK_POINTER_AND_LR
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blr
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vPortTickISR:
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portSAVE_STACK_POINTER_AND_LR
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bl xTaskIncrementTick
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#if configUSE_PREEMPTION == 1
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bl vTaskSwitchContext
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#endif
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/* Clear the interrupt */
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lis R0, 2048
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mttsr R0
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portRESTORE_STACK_POINTER_AND_LR
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blr
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vPortISRWrapper:
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portSAVE_STACK_POINTER_AND_LR
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bl vPortISRHandler
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portRESTORE_STACK_POINTER_AND_LR
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blr
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#if configUSE_FPU == 1
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vPortSaveFPURegisters:
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/* Enable APU and mark FPU as present. */
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mfmsr r0
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xor r30, r30, r30
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oris r30, r30, 512
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ori r30, r30, 8192
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or r0, r0, r30
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mtmsr r0
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#ifdef USE_DP_FPU
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/* Buffer address is in r3. Save each flop register into an offset from
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this buffer address. */
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stfd f0, 0(r3)
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stfd f1, 8(r3)
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stfd f2, 16(r3)
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stfd f3, 24(r3)
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stfd f4, 32(r3)
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stfd f5, 40(r3)
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stfd f6, 48(r3)
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stfd f7, 56(r3)
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stfd f8, 64(r3)
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stfd f9, 72(r3)
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stfd f10, 80(r3)
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stfd f11, 88(r3)
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stfd f12, 96(r3)
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stfd f13, 104(r3)
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stfd f14, 112(r3)
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stfd f15, 120(r3)
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stfd f16, 128(r3)
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stfd f17, 136(r3)
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stfd f18, 144(r3)
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stfd f19, 152(r3)
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stfd f20, 160(r3)
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stfd f21, 168(r3)
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stfd f22, 176(r3)
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stfd f23, 184(r3)
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stfd f24, 192(r3)
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stfd f25, 200(r3)
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stfd f26, 208(r3)
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stfd f27, 216(r3)
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stfd f28, 224(r3)
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stfd f29, 232(r3)
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stfd f30, 240(r3)
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stfd f31, 248(r3)
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/* Also save the FPSCR. */
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mffs f31
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stfs f31, 256(r3)
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#else
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/* Buffer address is in r3. Save each flop register into an offset from
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this buffer address. */
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stfs f0, 0(r3)
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stfs f1, 4(r3)
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stfs f2, 8(r3)
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stfs f3, 12(r3)
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stfs f4, 16(r3)
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stfs f5, 20(r3)
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stfs f6, 24(r3)
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stfs f7, 28(r3)
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stfs f8, 32(r3)
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stfs f9, 36(r3)
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stfs f10, 40(r3)
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stfs f11, 44(r3)
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stfs f12, 48(r3)
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stfs f13, 52(r3)
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stfs f14, 56(r3)
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stfs f15, 60(r3)
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stfs f16, 64(r3)
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stfs f17, 68(r3)
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stfs f18, 72(r3)
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stfs f19, 76(r3)
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stfs f20, 80(r3)
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stfs f21, 84(r3)
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stfs f22, 88(r3)
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stfs f23, 92(r3)
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stfs f24, 96(r3)
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stfs f25, 100(r3)
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stfs f26, 104(r3)
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stfs f27, 108(r3)
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stfs f28, 112(r3)
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stfs f29, 116(r3)
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stfs f30, 120(r3)
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stfs f31, 124(r3)
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/* Also save the FPSCR. */
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mffs f31
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stfs f31, 128(r3)
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#endif
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blr
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#endif /* configUSE_FPU. */
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#if configUSE_FPU == 1
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vPortRestoreFPURegisters:
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/* Enable APU and mark FPU as present. */
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mfmsr r0
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xor r30, r30, r30
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oris r30, r30, 512
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ori r30, r30, 8192
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or r0, r0, r30
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mtmsr r0
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#ifdef USE_DP_FPU
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/* Buffer address is in r3. Restore each flop register from an offset
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into this buffer.
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First the FPSCR. */
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lfs f31, 256(r3)
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mtfsf f31, 7
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lfd f0, 0(r3)
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lfd f1, 8(r3)
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lfd f2, 16(r3)
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lfd f3, 24(r3)
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lfd f4, 32(r3)
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lfd f5, 40(r3)
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lfd f6, 48(r3)
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lfd f7, 56(r3)
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lfd f8, 64(r3)
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lfd f9, 72(r3)
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lfd f10, 80(r3)
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lfd f11, 88(r3)
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lfd f12, 96(r3)
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lfd f13, 104(r3)
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lfd f14, 112(r3)
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lfd f15, 120(r3)
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lfd f16, 128(r3)
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lfd f17, 136(r3)
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lfd f18, 144(r3)
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lfd f19, 152(r3)
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lfd f20, 160(r3)
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lfd f21, 168(r3)
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lfd f22, 176(r3)
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lfd f23, 184(r3)
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lfd f24, 192(r3)
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lfd f25, 200(r3)
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lfd f26, 208(r3)
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lfd f27, 216(r3)
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lfd f28, 224(r3)
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lfd f29, 232(r3)
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lfd f30, 240(r3)
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lfd f31, 248(r3)
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#else
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/* Buffer address is in r3. Restore each flop register from an offset
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into this buffer.
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First the FPSCR. */
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lfs f31, 128(r3)
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mtfsf f31, 7
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lfs f0, 0(r3)
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lfs f1, 4(r3)
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lfs f2, 8(r3)
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lfs f3, 12(r3)
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lfs f4, 16(r3)
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lfs f5, 20(r3)
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lfs f6, 24(r3)
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lfs f7, 28(r3)
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lfs f8, 32(r3)
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lfs f9, 36(r3)
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lfs f10, 40(r3)
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lfs f11, 44(r3)
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lfs f12, 48(r3)
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lfs f13, 52(r3)
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lfs f14, 56(r3)
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lfs f15, 60(r3)
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lfs f16, 64(r3)
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lfs f17, 68(r3)
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lfs f18, 72(r3)
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lfs f19, 76(r3)
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lfs f20, 80(r3)
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lfs f21, 84(r3)
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lfs f22, 88(r3)
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lfs f23, 92(r3)
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lfs f24, 96(r3)
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lfs f25, 100(r3)
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lfs f26, 104(r3)
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lfs f27, 108(r3)
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lfs f28, 112(r3)
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lfs f29, 116(r3)
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lfs f30, 120(r3)
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lfs f31, 124(r3)
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#endif
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blr
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#endif /* configUSE_FPU. */
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
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#include "FreeRTOSConfig.h"
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern xTaskIncrementTick
|
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.extern vPortISRHandler
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|
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.global vPortStartFirstTask
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.global vPortYield
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.global vPortTickISR
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.global vPortISRWrapper
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.global vPortSaveFPURegisters
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.global vPortRestoreFPURegisters
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.set BChainField, 0
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.set NextLRField, BChainField + 4
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.set MSRField, NextLRField + 4
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.set PCField, MSRField + 4
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.set LRField, PCField + 4
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.set CTRField, LRField + 4
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.set XERField, CTRField + 4
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.set CRField, XERField + 4
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.set USPRG0Field, CRField + 4
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.set r0Field, USPRG0Field + 4
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.set r2Field, r0Field + 4
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.set r3r31Field, r2Field + 4
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.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
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.macro portSAVE_STACK_POINTER_AND_LR
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|
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/* Get the address of the TCB. */
|
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xor R0, R0, R0
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addis R2, R0, pxCurrentTCB@ha
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lwz R2, pxCurrentTCB@l( R2 )
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/* Store the stack pointer into the TCB */
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stw SP, 0( R2 )
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/* Save the link register */
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stwu R1, -24( R1 )
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mflr R0
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stw R31, 20( R1 )
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stw R0, 28( R1 )
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mr R31, r1
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.endm
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.macro portRESTORE_STACK_POINTER_AND_LR
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/* Restore the link register */
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lwz R11, 0( R1 )
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lwz R0, 4( R11 )
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mtlr R0
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lwz R31, -4( R11 )
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mr R1, R11
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/* Get the address of the TCB. */
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xor R0, R0, R0
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addis SP, R0, pxCurrentTCB@ha
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lwz SP, pxCurrentTCB@l( R1 )
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/* Get the task stack pointer from the TCB. */
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lwz SP, 0( SP )
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.endm
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vPortStartFirstTask:
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/* Get the address of the TCB. */
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xor R0, R0, R0
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addis SP, R0, pxCurrentTCB@ha
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lwz SP, pxCurrentTCB@l( SP )
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/* Get the task stack pointer from the TCB. */
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lwz SP, 0( SP )
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/* Restore MSR register to SRR1. */
|
||||
lwz R0, MSRField(R1)
|
||||
mtsrr1 R0
|
||||
|
||||
/* Restore current PC location to SRR0. */
|
||||
lwz R0, PCField(R1)
|
||||
mtsrr0 R0
|
||||
|
||||
/* Save USPRG0 register */
|
||||
lwz R0, USPRG0Field(R1)
|
||||
mtspr 0x100,R0
|
||||
|
||||
/* Restore Condition register */
|
||||
lwz R0, CRField(R1)
|
||||
mtcr R0
|
||||
|
||||
/* Restore Fixed Point Exception register */
|
||||
lwz R0, XERField(R1)
|
||||
mtxer R0
|
||||
|
||||
/* Restore Counter register */
|
||||
lwz R0, CTRField(R1)
|
||||
mtctr R0
|
||||
|
||||
/* Restore Link register */
|
||||
lwz R0, LRField(R1)
|
||||
mtlr R0
|
||||
|
||||
/* Restore remaining GPR registers. */
|
||||
lmw R3,r3r31Field(R1)
|
||||
|
||||
/* Restore r0 and r2. */
|
||||
lwz R0, r0Field(R1)
|
||||
lwz R2, r2Field(R1)
|
||||
|
||||
/* Remove frame from stack */
|
||||
addi R1,R1,IFrameSize
|
||||
|
||||
/* Return into the first task */
|
||||
rfi
|
||||
|
||||
|
||||
|
||||
vPortYield:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl vTaskSwitchContext
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
vPortTickISR:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl xTaskIncrementTick
|
||||
|
||||
#if configUSE_PREEMPTION == 1
|
||||
bl vTaskSwitchContext
|
||||
#endif
|
||||
|
||||
/* Clear the interrupt */
|
||||
lis R0, 2048
|
||||
mttsr R0
|
||||
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
vPortISRWrapper:
|
||||
|
||||
portSAVE_STACK_POINTER_AND_LR
|
||||
bl vPortISRHandler
|
||||
portRESTORE_STACK_POINTER_AND_LR
|
||||
blr
|
||||
|
||||
#if configUSE_FPU == 1
|
||||
|
||||
vPortSaveFPURegisters:
|
||||
|
||||
/* Enable APU and mark FPU as present. */
|
||||
mfmsr r0
|
||||
xor r30, r30, r30
|
||||
oris r30, r30, 512
|
||||
ori r30, r30, 8192
|
||||
or r0, r0, r30
|
||||
mtmsr r0
|
||||
|
||||
#ifdef USE_DP_FPU
|
||||
|
||||
/* Buffer address is in r3. Save each flop register into an offset from
|
||||
this buffer address. */
|
||||
stfd f0, 0(r3)
|
||||
stfd f1, 8(r3)
|
||||
stfd f2, 16(r3)
|
||||
stfd f3, 24(r3)
|
||||
stfd f4, 32(r3)
|
||||
stfd f5, 40(r3)
|
||||
stfd f6, 48(r3)
|
||||
stfd f7, 56(r3)
|
||||
stfd f8, 64(r3)
|
||||
stfd f9, 72(r3)
|
||||
stfd f10, 80(r3)
|
||||
stfd f11, 88(r3)
|
||||
stfd f12, 96(r3)
|
||||
stfd f13, 104(r3)
|
||||
stfd f14, 112(r3)
|
||||
stfd f15, 120(r3)
|
||||
stfd f16, 128(r3)
|
||||
stfd f17, 136(r3)
|
||||
stfd f18, 144(r3)
|
||||
stfd f19, 152(r3)
|
||||
stfd f20, 160(r3)
|
||||
stfd f21, 168(r3)
|
||||
stfd f22, 176(r3)
|
||||
stfd f23, 184(r3)
|
||||
stfd f24, 192(r3)
|
||||
stfd f25, 200(r3)
|
||||
stfd f26, 208(r3)
|
||||
stfd f27, 216(r3)
|
||||
stfd f28, 224(r3)
|
||||
stfd f29, 232(r3)
|
||||
stfd f30, 240(r3)
|
||||
stfd f31, 248(r3)
|
||||
|
||||
/* Also save the FPSCR. */
|
||||
mffs f31
|
||||
stfs f31, 256(r3)
|
||||
|
||||
#else
|
||||
|
||||
/* Buffer address is in r3. Save each flop register into an offset from
|
||||
this buffer address. */
|
||||
stfs f0, 0(r3)
|
||||
stfs f1, 4(r3)
|
||||
stfs f2, 8(r3)
|
||||
stfs f3, 12(r3)
|
||||
stfs f4, 16(r3)
|
||||
stfs f5, 20(r3)
|
||||
stfs f6, 24(r3)
|
||||
stfs f7, 28(r3)
|
||||
stfs f8, 32(r3)
|
||||
stfs f9, 36(r3)
|
||||
stfs f10, 40(r3)
|
||||
stfs f11, 44(r3)
|
||||
stfs f12, 48(r3)
|
||||
stfs f13, 52(r3)
|
||||
stfs f14, 56(r3)
|
||||
stfs f15, 60(r3)
|
||||
stfs f16, 64(r3)
|
||||
stfs f17, 68(r3)
|
||||
stfs f18, 72(r3)
|
||||
stfs f19, 76(r3)
|
||||
stfs f20, 80(r3)
|
||||
stfs f21, 84(r3)
|
||||
stfs f22, 88(r3)
|
||||
stfs f23, 92(r3)
|
||||
stfs f24, 96(r3)
|
||||
stfs f25, 100(r3)
|
||||
stfs f26, 104(r3)
|
||||
stfs f27, 108(r3)
|
||||
stfs f28, 112(r3)
|
||||
stfs f29, 116(r3)
|
||||
stfs f30, 120(r3)
|
||||
stfs f31, 124(r3)
|
||||
|
||||
/* Also save the FPSCR. */
|
||||
mffs f31
|
||||
stfs f31, 128(r3)
|
||||
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
#endif /* configUSE_FPU. */
|
||||
|
||||
|
||||
#if configUSE_FPU == 1
|
||||
|
||||
vPortRestoreFPURegisters:
|
||||
|
||||
/* Enable APU and mark FPU as present. */
|
||||
mfmsr r0
|
||||
xor r30, r30, r30
|
||||
oris r30, r30, 512
|
||||
ori r30, r30, 8192
|
||||
or r0, r0, r30
|
||||
mtmsr r0
|
||||
|
||||
#ifdef USE_DP_FPU
|
||||
|
||||
/* Buffer address is in r3. Restore each flop register from an offset
|
||||
into this buffer.
|
||||
|
||||
First the FPSCR. */
|
||||
lfs f31, 256(r3)
|
||||
mtfsf f31, 7
|
||||
|
||||
lfd f0, 0(r3)
|
||||
lfd f1, 8(r3)
|
||||
lfd f2, 16(r3)
|
||||
lfd f3, 24(r3)
|
||||
lfd f4, 32(r3)
|
||||
lfd f5, 40(r3)
|
||||
lfd f6, 48(r3)
|
||||
lfd f7, 56(r3)
|
||||
lfd f8, 64(r3)
|
||||
lfd f9, 72(r3)
|
||||
lfd f10, 80(r3)
|
||||
lfd f11, 88(r3)
|
||||
lfd f12, 96(r3)
|
||||
lfd f13, 104(r3)
|
||||
lfd f14, 112(r3)
|
||||
lfd f15, 120(r3)
|
||||
lfd f16, 128(r3)
|
||||
lfd f17, 136(r3)
|
||||
lfd f18, 144(r3)
|
||||
lfd f19, 152(r3)
|
||||
lfd f20, 160(r3)
|
||||
lfd f21, 168(r3)
|
||||
lfd f22, 176(r3)
|
||||
lfd f23, 184(r3)
|
||||
lfd f24, 192(r3)
|
||||
lfd f25, 200(r3)
|
||||
lfd f26, 208(r3)
|
||||
lfd f27, 216(r3)
|
||||
lfd f28, 224(r3)
|
||||
lfd f29, 232(r3)
|
||||
lfd f30, 240(r3)
|
||||
lfd f31, 248(r3)
|
||||
|
||||
#else
|
||||
|
||||
/* Buffer address is in r3. Restore each flop register from an offset
|
||||
into this buffer.
|
||||
|
||||
First the FPSCR. */
|
||||
lfs f31, 128(r3)
|
||||
mtfsf f31, 7
|
||||
|
||||
lfs f0, 0(r3)
|
||||
lfs f1, 4(r3)
|
||||
lfs f2, 8(r3)
|
||||
lfs f3, 12(r3)
|
||||
lfs f4, 16(r3)
|
||||
lfs f5, 20(r3)
|
||||
lfs f6, 24(r3)
|
||||
lfs f7, 28(r3)
|
||||
lfs f8, 32(r3)
|
||||
lfs f9, 36(r3)
|
||||
lfs f10, 40(r3)
|
||||
lfs f11, 44(r3)
|
||||
lfs f12, 48(r3)
|
||||
lfs f13, 52(r3)
|
||||
lfs f14, 56(r3)
|
||||
lfs f15, 60(r3)
|
||||
lfs f16, 64(r3)
|
||||
lfs f17, 68(r3)
|
||||
lfs f18, 72(r3)
|
||||
lfs f19, 76(r3)
|
||||
lfs f20, 80(r3)
|
||||
lfs f21, 84(r3)
|
||||
lfs f22, 88(r3)
|
||||
lfs f23, 92(r3)
|
||||
lfs f24, 96(r3)
|
||||
lfs f25, 100(r3)
|
||||
lfs f26, 104(r3)
|
||||
lfs f27, 108(r3)
|
||||
lfs f28, 112(r3)
|
||||
lfs f29, 116(r3)
|
||||
lfs f30, 120(r3)
|
||||
lfs f31, 124(r3)
|
||||
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
#endif /* configUSE_FPU. */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue