mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -1,318 +1,313 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
|
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* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.text
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.arm
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.set SYS_MODE, 0x1f
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.set SVC_MODE, 0x13
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.set IRQ_MODE, 0x12
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/* Hardware registers. */
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.extern ulICCIAR
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.extern ulICCEOIR
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.extern ulICCPMR
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/* Variables and functions. */
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.extern ulMaxAPIPriorityMask
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.extern _freertos_vector_table
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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.extern ulPortInterruptNesting
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.extern ulPortTaskHasFPUContext
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.global vPortRestoreTaskContext
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.macro portSAVE_CONTEXT
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/* Save the LR and SPSR onto the system mode stack before switching to
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system mode to save the remaining system mode registers. */
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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/* Push the critical nesting count. */
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LDR R2, ulCriticalNestingConst
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LDR R1, [R2]
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PUSH {R1}
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/* Does the task have a floating point context that needs saving? If
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ulPortTaskHasFPUContext is 0 then no. */
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LDR R2, ulPortTaskHasFPUContextConst
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LDR R3, [R2]
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CMP R3, #0
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/* Save the floating point context, if any. */
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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/*VPUSHNE {D16-D31}*/
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PUSHNE {R1}
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/* Save ulPortTaskHasFPUContext itself. */
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PUSH {R3}
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/* Save the stack pointer in the TCB. */
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LDR R0, pxCurrentTCBConst
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LDR R1, [R0]
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STR SP, [R1]
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.endm
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; /**********************************************************************/
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.macro portRESTORE_CONTEXT
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/* Set the SP to point to the stack of the task being restored. */
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LDR R0, pxCurrentTCBConst
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LDR R1, [R0]
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LDR SP, [R1]
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/* Is there a floating point context to restore? If the restored
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ulPortTaskHasFPUContext is zero then no. */
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LDR R0, ulPortTaskHasFPUContextConst
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POP {R1}
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STR R1, [R0]
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CMP R1, #0
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/* Restore the floating point context, if any. */
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POPNE {R0}
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/*VPOPNE {D16-D31}*/
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VPOPNE {D0-D15}
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VMSRNE FPSCR, R0
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/* Restore the critical section nesting depth. */
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LDR R0, ulCriticalNestingConst
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POP {R1}
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STR R1, [R0]
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/* Ensure the priority mask is correct for the critical nesting depth. */
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LDR R2, ulICCPMRConst
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LDR R2, [R2]
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CMP R1, #0
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MOVEQ R4, #255
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LDRNE R4, ulMaxAPIPriorityMaskConst
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LDRNE R4, [R4]
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STR R4, [R2]
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/* Restore all system mode registers other than the SP (which is already
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being used). */
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POP {R0-R12, R14}
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/* Return to the task code, loading CPSR on the way. */
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RFEIA sp!
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.endm
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/******************************************************************************
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* SVC handler is used to start the scheduler.
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*****************************************************************************/
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.align 4
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.type FreeRTOS_SWI_Handler, %function
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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LDR R0, vTaskSwitchContextConst
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BLX R0
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portRESTORE_CONTEXT
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/******************************************************************************
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* vPortRestoreTaskContext is used to start the scheduler.
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*****************************************************************************/
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.type vPortRestoreTaskContext, %function
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vPortRestoreTaskContext:
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/* Switch to system mode. */
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CPS #SYS_MODE
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portRESTORE_CONTEXT
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.align 4
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.type FreeRTOS_IRQ_Handler, %function
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FreeRTOS_IRQ_Handler:
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/* Return to the interrupted instruction. */
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SUB lr, lr, #4
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/* Push the return address and SPSR. */
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PUSH {lr}
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MRS lr, SPSR
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PUSH {lr}
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/* Change to supervisor mode to allow reentry. */
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CPS #SVC_MODE
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/* Push used registers. */
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PUSH {r0-r4, r12}
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/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
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for future use. r1 holds the original ulPortInterruptNesting value for
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future use. */
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LDR r3, ulPortInterruptNestingConst
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LDR r1, [r3]
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ADD r4, r1, #1
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STR r4, [r3]
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/* Read value from the interrupt acknowledge register, which is stored in r0
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for future parameter and interrupt clearing use. */
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LDR r2, ulICCIARConst
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LDR r2, [r2]
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LDR r0, [r2]
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/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
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future use. _RB_ Is this ever needed provided the start of the stack is
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alligned on an 8-byte boundary? */
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MOV r2, sp
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AND r2, r2, #4
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SUB sp, sp, r2
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/* Call the interrupt handler. */
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PUSH {r0-r4, lr}
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LDR r1, vApplicationIRQHandlerConst
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BLX r1
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POP {r0-r4, lr}
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ADD sp, sp, r2
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CPSID i
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DSB
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ISB
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/* Write the value read from ICCIAR to ICCEOIR. */
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LDR r4, ulICCEOIRConst
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LDR r4, [r4]
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STR r0, [r4]
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/* Restore the old nesting count. */
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STR r1, [r3]
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/* A context switch is never performed if the nesting count is not 0. */
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CMP r1, #0
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BNE exit_without_switch
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/* Did the interrupt request a context switch? r1 holds the address of
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ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
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use. */
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LDR r1, =ulPortYieldRequired
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LDR r0, [r1]
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CMP r0, #0
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BNE switch_before_exit
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exit_without_switch:
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/* No context switch. Restore used registers, LR_irq and SPSR before
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returning. */
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POP {r0-r4, r12}
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CPS #IRQ_MODE
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POP {LR}
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MSR SPSR_cxsf, LR
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POP {LR}
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MOVS PC, LR
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switch_before_exit:
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/* A context swtich is to be performed. Clear the context switch pending
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flag. */
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MOV r0, #0
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STR r0, [r1]
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/* Restore used registers, LR-irq and SPSR before saving the context
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to the task stack. */
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POP {r0-r4, r12}
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CPS #IRQ_MODE
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POP {LR}
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MSR SPSR_cxsf, LR
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POP {LR}
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portSAVE_CONTEXT
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/* Call the function that selects the new task to execute.
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vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
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instructions, or 8 byte aligned stack allocated data. LR does not need
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saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
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LDR R0, vTaskSwitchContextConst
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BLX R0
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/* Restore the context of, and branch to, the task selected to execute
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next. */
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portRESTORE_CONTEXT
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/******************************************************************************
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* If the application provides an implementation of vApplicationIRQHandler(),
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* then it will get called directly without saving the FPU registers on
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* interrupt entry, and this weak implementation of
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* vApplicationIRQHandler() will not get called.
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*
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* If the application provides its own implementation of
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* vApplicationFPUSafeIRQHandler() then this implementation of
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* vApplicationIRQHandler() will be called, save the FPU registers, and then
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* call vApplicationFPUSafeIRQHandler().
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*
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* Therefore, if the application writer wants FPU registers to be saved on
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* interrupt entry their IRQ handler must be called
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* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
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* FPU registers to be saved on interrupt entry their IRQ handler must be
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* called vApplicationIRQHandler().
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*****************************************************************************/
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.align 4
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.weak vApplicationIRQHandler
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.type vApplicationIRQHandler, %function
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vApplicationIRQHandler:
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PUSH {LR}
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FMRX R1, FPSCR
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VPUSH {D0-D15}
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PUSH {R1}
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LDR r1, vApplicationFPUSafeIRQHandlerConst
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BLX r1
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POP {R0}
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VPOP {D0-D15}
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VMSR FPSCR, R0
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POP {PC}
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ulICCIARConst: .word ulICCIAR
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ulICCEOIRConst: .word ulICCEOIR
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ulICCPMRConst: .word ulICCPMR
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pxCurrentTCBConst: .word pxCurrentTCB
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ulCriticalNestingConst: .word ulCriticalNesting
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ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
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ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
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vTaskSwitchContextConst: .word vTaskSwitchContext
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vApplicationIRQHandlerConst: .word vApplicationIRQHandler
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ulPortInterruptNestingConst: .word ulPortInterruptNesting
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vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
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.end
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.text
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.arm
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.set SYS_MODE, 0x1f
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.set SVC_MODE, 0x13
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.set IRQ_MODE, 0x12
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/* Hardware registers. */
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.extern ulICCIAR
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.extern ulICCEOIR
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.extern ulICCPMR
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/* Variables and functions. */
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.extern ulMaxAPIPriorityMask
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.extern _freertos_vector_table
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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.extern ulPortInterruptNesting
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.extern ulPortTaskHasFPUContext
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.global vPortRestoreTaskContext
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.macro portSAVE_CONTEXT
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/* Save the LR and SPSR onto the system mode stack before switching to
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system mode to save the remaining system mode registers. */
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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/* Push the critical nesting count. */
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LDR R2, ulCriticalNestingConst
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LDR R1, [R2]
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PUSH {R1}
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/* Does the task have a floating point context that needs saving? If
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ulPortTaskHasFPUContext is 0 then no. */
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LDR R2, ulPortTaskHasFPUContextConst
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LDR R3, [R2]
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CMP R3, #0
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/* Save the floating point context, if any. */
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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/*VPUSHNE {D16-D31}*/
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PUSHNE {R1}
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/* Save ulPortTaskHasFPUContext itself. */
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PUSH {R3}
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/* Save the stack pointer in the TCB. */
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LDR R0, pxCurrentTCBConst
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LDR R1, [R0]
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STR SP, [R1]
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.endm
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; /**********************************************************************/
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.macro portRESTORE_CONTEXT
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/* Set the SP to point to the stack of the task being restored. */
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LDR R0, pxCurrentTCBConst
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LDR R1, [R0]
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LDR SP, [R1]
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/* Is there a floating point context to restore? If the restored
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ulPortTaskHasFPUContext is zero then no. */
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LDR R0, ulPortTaskHasFPUContextConst
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POP {R1}
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STR R1, [R0]
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CMP R1, #0
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/* Restore the floating point context, if any. */
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POPNE {R0}
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/*VPOPNE {D16-D31}*/
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VPOPNE {D0-D15}
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VMSRNE FPSCR, R0
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/* Restore the critical section nesting depth. */
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LDR R0, ulCriticalNestingConst
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POP {R1}
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STR R1, [R0]
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/* Ensure the priority mask is correct for the critical nesting depth. */
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LDR R2, ulICCPMRConst
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LDR R2, [R2]
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CMP R1, #0
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MOVEQ R4, #255
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LDRNE R4, ulMaxAPIPriorityMaskConst
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LDRNE R4, [R4]
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STR R4, [R2]
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/* Restore all system mode registers other than the SP (which is already
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being used). */
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POP {R0-R12, R14}
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/* Return to the task code, loading CPSR on the way. */
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RFEIA sp!
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.endm
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/******************************************************************************
|
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* SVC handler is used to start the scheduler.
|
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*****************************************************************************/
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.align 4
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.type FreeRTOS_SWI_Handler, %function
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FreeRTOS_SWI_Handler:
|
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/* Save the context of the current task and select a new task to run. */
|
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portSAVE_CONTEXT
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LDR R0, vTaskSwitchContextConst
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BLX R0
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portRESTORE_CONTEXT
|
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|
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|
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/******************************************************************************
|
||||
* vPortRestoreTaskContext is used to start the scheduler.
|
||||
*****************************************************************************/
|
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.type vPortRestoreTaskContext, %function
|
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vPortRestoreTaskContext:
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/* Switch to system mode. */
|
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CPS #SYS_MODE
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portRESTORE_CONTEXT
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|
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.align 4
|
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.type FreeRTOS_IRQ_Handler, %function
|
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FreeRTOS_IRQ_Handler:
|
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|
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/* Return to the interrupted instruction. */
|
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SUB lr, lr, #4
|
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|
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/* Push the return address and SPSR. */
|
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PUSH {lr}
|
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MRS lr, SPSR
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PUSH {lr}
|
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|
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/* Change to supervisor mode to allow reentry. */
|
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CPS #SVC_MODE
|
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|
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/* Push used registers. */
|
||||
PUSH {r0-r4, r12}
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||||
|
||||
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
|
||||
for future use. r1 holds the original ulPortInterruptNesting value for
|
||||
future use. */
|
||||
LDR r3, ulPortInterruptNestingConst
|
||||
LDR r1, [r3]
|
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ADD r4, r1, #1
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STR r4, [r3]
|
||||
|
||||
/* Read value from the interrupt acknowledge register, which is stored in r0
|
||||
for future parameter and interrupt clearing use. */
|
||||
LDR r2, ulICCIARConst
|
||||
LDR r2, [r2]
|
||||
LDR r0, [r2]
|
||||
|
||||
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
|
||||
future use. _RB_ Is this ever needed provided the start of the stack is
|
||||
alligned on an 8-byte boundary? */
|
||||
MOV r2, sp
|
||||
AND r2, r2, #4
|
||||
SUB sp, sp, r2
|
||||
|
||||
/* Call the interrupt handler. */
|
||||
PUSH {r0-r4, lr}
|
||||
LDR r1, vApplicationIRQHandlerConst
|
||||
BLX r1
|
||||
POP {r0-r4, lr}
|
||||
ADD sp, sp, r2
|
||||
|
||||
CPSID i
|
||||
DSB
|
||||
ISB
|
||||
|
||||
/* Write the value read from ICCIAR to ICCEOIR. */
|
||||
LDR r4, ulICCEOIRConst
|
||||
LDR r4, [r4]
|
||||
STR r0, [r4]
|
||||
|
||||
/* Restore the old nesting count. */
|
||||
STR r1, [r3]
|
||||
|
||||
/* A context switch is never performed if the nesting count is not 0. */
|
||||
CMP r1, #0
|
||||
BNE exit_without_switch
|
||||
|
||||
/* Did the interrupt request a context switch? r1 holds the address of
|
||||
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
|
||||
use. */
|
||||
LDR r1, =ulPortYieldRequired
|
||||
LDR r0, [r1]
|
||||
CMP r0, #0
|
||||
BNE switch_before_exit
|
||||
|
||||
exit_without_switch:
|
||||
/* No context switch. Restore used registers, LR_irq and SPSR before
|
||||
returning. */
|
||||
POP {r0-r4, r12}
|
||||
CPS #IRQ_MODE
|
||||
POP {LR}
|
||||
MSR SPSR_cxsf, LR
|
||||
POP {LR}
|
||||
MOVS PC, LR
|
||||
|
||||
switch_before_exit:
|
||||
/* A context swtich is to be performed. Clear the context switch pending
|
||||
flag. */
|
||||
MOV r0, #0
|
||||
STR r0, [r1]
|
||||
|
||||
/* Restore used registers, LR-irq and SPSR before saving the context
|
||||
to the task stack. */
|
||||
POP {r0-r4, r12}
|
||||
CPS #IRQ_MODE
|
||||
POP {LR}
|
||||
MSR SPSR_cxsf, LR
|
||||
POP {LR}
|
||||
portSAVE_CONTEXT
|
||||
|
||||
/* Call the function that selects the new task to execute.
|
||||
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
|
||||
instructions, or 8 byte aligned stack allocated data. LR does not need
|
||||
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
|
||||
LDR R0, vTaskSwitchContextConst
|
||||
BLX R0
|
||||
|
||||
/* Restore the context of, and branch to, the task selected to execute
|
||||
next. */
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
/******************************************************************************
|
||||
* If the application provides an implementation of vApplicationIRQHandler(),
|
||||
* then it will get called directly without saving the FPU registers on
|
||||
* interrupt entry, and this weak implementation of
|
||||
* vApplicationIRQHandler() will not get called.
|
||||
*
|
||||
* If the application provides its own implementation of
|
||||
* vApplicationFPUSafeIRQHandler() then this implementation of
|
||||
* vApplicationIRQHandler() will be called, save the FPU registers, and then
|
||||
* call vApplicationFPUSafeIRQHandler().
|
||||
*
|
||||
* Therefore, if the application writer wants FPU registers to be saved on
|
||||
* interrupt entry their IRQ handler must be called
|
||||
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
|
||||
* FPU registers to be saved on interrupt entry their IRQ handler must be
|
||||
* called vApplicationIRQHandler().
|
||||
*****************************************************************************/
|
||||
|
||||
.align 4
|
||||
.weak vApplicationIRQHandler
|
||||
.type vApplicationIRQHandler, %function
|
||||
vApplicationIRQHandler:
|
||||
PUSH {LR}
|
||||
FMRX R1, FPSCR
|
||||
VPUSH {D0-D15}
|
||||
PUSH {R1}
|
||||
|
||||
LDR r1, vApplicationFPUSafeIRQHandlerConst
|
||||
BLX r1
|
||||
|
||||
POP {R0}
|
||||
VPOP {D0-D15}
|
||||
VMSR FPSCR, R0
|
||||
|
||||
POP {PC}
|
||||
|
||||
ulICCIARConst: .word ulICCIAR
|
||||
ulICCEOIRConst: .word ulICCEOIR
|
||||
ulICCPMRConst: .word ulICCPMR
|
||||
pxCurrentTCBConst: .word pxCurrentTCB
|
||||
ulCriticalNestingConst: .word ulCriticalNesting
|
||||
ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
|
||||
ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
|
||||
vTaskSwitchContextConst: .word vTaskSwitchContext
|
||||
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
|
||||
ulPortInterruptNestingConst: .word ulPortInterruptNesting
|
||||
vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
|
||||
|
||||
.end
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue